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Hello, I'm using the Xilinx tools under linux 32 bits ( a gentoo ) and I'm having a really big problem. Basically every Xilinx application based on java (chipscope, planahead, coregen) can just 'freeze' at anytime (usually pretty soon after I launch it). By freeze I mean the GUI completly stops responding and doesn't even refresh anymore. Since the Xilinx tools are more and more based on java, that means I'm really screwed. Anyone with the same symptoms or a diagnostic ? SylvainArticle: 100201
Roger Bourne skrev: > Thank you rbj > But I am looking for a set of equations for a CASCADED structure of > biquad filters. > > I.E. > If the biquad 2nd order (chebychev) IIR filters form a cascaded higher > order IIR filter structure, as to obtain a very sharp & immediate > response at the cutoff frequency, how would the filter coeffcients of > one filter be related to the other filters? I know from online applets > that for a 4x2nd order filter, that all 4 filters are different. > > Can you advise me? The usual way of designing discrete-time IIR filters from analog prototypes goes as follows: 1) Formulate a filter specification in discrete-time domain 2) Transform the discrete-time spec to continuous time 3) Transform general spec to normalized LP spec 4) Determine minimum order required to meet normalized spec 5) Compute coefficients in cascaded 1st and 2nd order sections 6) Transform from continuous time to discrete time 7) Transform from normalized LP filter to desired filter There are plenty of details to keep track of. The one recent text I am aware of that reviews this process in any detail for Butterworth, Cebyshev 1 and 2, as well as elliptic filters, is this one: http://www.amazon.com/gp/product/0071454241/sr=8-1/qid=1144225586/ref=sr_1_1/002-1409031-0693601?%5Fencoding=UTF8 RuneArticle: 100202
Hi Sylvain,
"Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com> wrote in
message news:1144221898.783029.239120@i39g2000cwa.googlegroups.com...
> Hello,
> I'm using the Xilinx tools under linux 32 bits ( a gentoo ) and
> I'm having a really big problem. Basically every Xilinx application
> based on java (chipscope, planahead, coregen) can just 'freeze'
> at anytime (usually pretty soon after I launch it). By freeze I mean
> the GUI completly stops responding and doesn't even refresh
> anymore.
What version of the Xilinx tools? What kernel? What JVM?
Xilinx only officially supports RHEL but I know lots of people (including
me) run it on other Linux flavours without any problems. I'd see what
difference there are between your system and an out-of-the-box RedHat
install, and go from there. (Tech support can probably tell you what the
requirements are.)
> Since the Xilinx tools are more and more based on java, that
> means I'm really screwed.
Actually, I'd disagree. Certainly Coregen as of ISE 8.1i is a native
application, with only small amounts of Java for legacy core GUIs. You're
right about the other two though. But there is certainly no policy at work
to increase the amount of Java used (if anything, the reverse is true).
Cheers,
-Ben-
Article: 100203Dale, I thank you for every suggestion, nothing is obvious to me. Yes, I decided to place the JTAG port on the board for both the DSP and the FPGA (one each and not in a chain) in order to have one more feature letting me understand if something is going wrong and how to solve it. What do you think about the PDS? On many other boards they use less different capacitor sizes, say just 0.01uF and 1uF, while I followed the Xapp623 guidelines, mainly because this is my first experience. Then, how did you handle M0-M2 signal? With a switch/jumper to GND or Vcc? Thanks again MarcoArticle: 100204
Hi, Has anyone tried XAPP264? - I have! and have been having immense difficulties. Firstly, the design will not simulate after Matlab R14 (7.0) versions ie. with service pack 2 etc. Then you get an error due to the perl script written to export the design from system generator to EDK. I am currently debugging this! - anyone tried??? I actually want to design a custom PLB slave Peripheral using System Generator. Anyone attempted this??? It seems Xilinx only want to support FSL. for Microblaze in System Generator. Cheers (an unhappy) Si P=2Es. I would like to thank anyone who even reads this =EF=81=8AArticle: 100205
Hi Louis, I built OPB peripheral with DMA included using create/import peripheral. Operation is very simple: write value to DMACR (control register) write source address to SA write destination address to DA write transfer length to LENGTH - this starts transfer Registers for DMA are at peripheral_base_address+0x400. Search for more information in DS416 and in generated peripheral header file (access addresses). Make it work GuruArticle: 100206
I had the same problems using parallel cable 3 - sometimes done pin did't go high. Now I am using Platform Cable USB and the problems are gone (and the programming is very fast). Cheers, GuruArticle: 100207
Hi Ben, > > I'm using the Xilinx tools under linux 32 bits ( a gentoo ) and > > I'm having a really big problem. Basically every Xilinx application > > based on java (chipscope, planahead, coregen) can just 'freeze' > > at anytime (usually pretty soon after I launch it). By freeze I mean > > the GUI completly stops responding and doesn't even refresh > > anymore. > > What version of the Xilinx tools? What kernel? What JVM? Sorry for the lack of Infos : - ISE Foundation 8.1 sp 3 - Chipscope 8.1.03 - PlanAhead 8.1.2 The JVM is each time provided with theses tools. It's the sun jre 1.5.0 but i'm not sure of the revision. I've tried with the latest sun jre as well with the same effects and blackdown jre is only 1.4.2 and doesn't work at all (normal, its not a 1.5) tnt@ritsuko ~ $ uname -a Linux ritsuko 2.6.14-gentoo-r5-ritsuko #3 SMP PREEMPT Sun Jan 1 22:48:38 CET 2006 i686 Intel(R) Pentium(R) D CPU 3.00GHz GenuineIntel GNU/Linux > Xilinx only officially supports RHEL but I know lots of people (including > me) run it on other Linux flavours without any problems. I'd see what > difference there are between your system and an out-of-the-box RedHat > install, and go from there. (Tech support can probably tell you what the > requirements are.) I don't know why but each time I try to open a webcase, I get a "Server Error" page at url : https://xapps2.xilinx.com/websupport/clearexp_cgi/?login=Login with a small sun favicon. > > Since the Xilinx tools are more and more based on java, that > > means I'm really screwed. > > Actually, I'd disagree. Certainly Coregen as of ISE 8.1i is a native > application, with only small amounts of Java for legacy core GUIs. You're > right about the other two though. But there is certainly no policy at work > to increase the amount of Java used (if anything, the reverse is true). Well, ok it may not be a policy. But it's still a fact ;) Indeed coregen has only some "ip customizer" but one of it is the v4 fx emac wrapper ;) And besides that, it works well. I can work with chipscope running on a remote machine using windows remote desktop and launching the cs_server.sh on my local machine. But for plan ahead it's a whole lot more annoying. And the weird thing is I never noticed that behavior in 7.1 ... Regards, SylvainArticle: 100208
PeterC wrote: > >Is this clk_in to clk0_out phase relationship shown in the behavioural >simulation accurate? > Allan Herriman replied: > > It's meant to make the phase of the feedback input (clkfb) the same as > the clock input (clkin) > One caution: the default DCM configuration inserts an intentional delay in the DCM feedback path, making the clkfb LEAD the input clock by about 1.5 ns in the V2 family (not sure about S3 numbers). This is done to insure zero hold at IOB inputs in the default SYSTEM_SYNCHRONOUS mode. This also used to cause 'clock creep' in cascaded DCM's, but the latest S/W might set the DCM to SOURCE_SYNCHRONOUS if it sees a cascade. The V2 delay element is described nicely in XAPP259 v1.0 (pp 4-5); however, the equivalent documention for S3, XAPP462 v1.1 (pp 32-34), is horribly confused by the notion that delaying feedback makes the output clock happen earlier. See also Answer Records 15350 and 13024 Simulation modeling of DCM delays over the years has been, er, quirky. For past threads, google comp.arch.fpga for "DCM SOURCE_SYNCHRONOUS" BrianArticle: 100209
Thanks for your response, but I am using Parallel Cable IV, so I guess the problem is not due to the parallel cable (I tried the Platform Cable USB as well).Article: 100210
Hello, My name is Julien, I work as Design engineer in France. I am currently implementing in Verilog an I2C controller on a Xilinx Spartan3, and I need to test it. With the application note XAPP333, Xilinx provides testbenches in VHDL but not in Verilog. Where can I get the testbenches in Verilog ? regards, JulienArticle: 100211
Hi Sylvain,
"Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com> wrote in
message news:1144237213.879794.79360@e56g2000cwe.googlegroups.com...
> - ISE Foundation 8.1 sp 3
> - Chipscope 8.1.03
> - PlanAhead 8.1.2
> The JVM is each time provided with theses tools. It's the sun jre 1.5.0
> but i'm not sure of the revision.
> I've tried with the latest sun jre as well with the same effects and
> blackdown jre is only 1.4.2 and doesn't work at all (normal, its not a
> 1.5)
Interesting. I guess you can run other Java apps without any problems,
right?
If this were Windows I'd probably diagnose that as some manifestation of DLL
hell, but I don't usually have problems like that with Linux. Maybe there is
a Java guru around somewhere who would know better...
> I don't know why but each time I try to open a webcase, I get a "Server
> Error" page at url :
>
> https://xapps2.xilinx.com/websupport/clearexp_cgi/?login=Login
Curious. I got a login prompt.
> > Actually, I'd disagree. Certainly Coregen as of ISE 8.1i is a native
> > application, with only small amounts of Java for legacy core GUIs.
You're
> > right about the other two though. But there is certainly no policy at
work
> > to increase the amount of Java used (if anything, the reverse is true).
> Well, ok it may not be a policy. But it's still a fact ;)
Touché. :-)
> Indeed coregen has only some "ip customizer" but one of it is the v4 fx
> emac wrapper ;) And besides that, it works well. I can work with
> chipscope running on a remote machine using windows remote desktop and
> launching the cs_server.sh on my local machine. But for plan ahead it's
> a whole lot more annoying.
> And the weird thing is I never noticed that behavior in 7.1 ...
Was that on the same gentoo system (i.e. did you just upgrade and now
everything is borked)?
Looking at the answers database it appears that in 7.1i there were some
problems with multi-threading in the Linux JNI that caused the GUIs to
freeze during core generation (because the UI thread had to be disabled).
This didn't actually cause anything to freeze indefinitely though (it would
come back when the core had been generated). Perhaps it's somehow related to
that? Hard to tell.
Cheers,
-Ben-
Article: 100212Bob Perlman wrote: > On 4 Apr 2006 20:00:24 -0700, "PeterC" <peter@geckoaudio.com> wrote: > > > > >Ralf Hildebrandt has described a dual-edge D-FF in his March 28th post > >- one page PDF is available at > >http://www.ralf-hildebrandt.de/publication/pdf_dff/pde_dff.pdf > > > >I'd like to hear opinions on the reliability of this circuit - can > >anyone see any issues with using this circuit. > > > >PeterC. > > This looks like the circuit that Gabor posted last May. It should > work just fine. It is the same circuit, but why are two of the three XOR gates drawn as 2-input multiplexers with an iverter? This doesn't help me visualize the circuit at all... > > Bob Perlman > Cambrian Design WorksArticle: 100213
bjzhangwn wrote: > Thanks,300mw is the total power,include the quiescent and the dynamic > powers,and the prequncy I use is not high,about 20Mhz,The LUTs I use > are about 5k for look up table,2k registers.I want to know if I can > make it work under 300mvw. Steve Knapp brought up an important point about static power. You may actually do better with one of the older series (Spartan 2e perhaps) made on 1.3 micron process. Static power can be quite high in the 90 nm process parts. At your operating frequency almost any FPGA will work. Good luck, GaborArticle: 100214
Maki wrote: > Hello friends, > > It appears that I can't download ispLever. I get a message that file > isn't available. > Is it working at Your side? Wherever You may be :o) > > Thanks, > Maki It works here in the U.S. Did you read and agree to the license terms and export control?Article: 100215
Hi, I want to know what approach you would recommend to compress an incoming DVI data stream (data width 24 bit, pixel clock 25-165MHz) from 24 bit colour depth to 16 bit colour depth. The DVI data are stored as 64 bit chunks into DDR memory at 133MHz. For higher resolutions (fPIX > fDDR) I would like to reduce the colour depth so that performance (frame rate) at the read side of the DDR memory (image display) is not downgraded in such a way that moved images judder. Are there algorithms for parallel data processing (24bit/16bit) you can recommend ? Any hints are appreciated. Rgds Andr=E9Article: 100216
If I wanted to just run a single clock and 16 synchronous data lines into a Stratix device is there no way to make this work? All the information I am finding uses the SERDES. I am interested in seeing something more like Xilinx and National were demonstrating last month with the Virtex but with a Stratix device.Article: 100217
I hard wired the mode signals according to the config mode you're using. In your case, serial slave, I believe. You don't need a switch or jumper. JTAG config mode is always available regardless of what you do with the mode pins. Setting them to JTAG mode only disables all other modes, unnecessarily. As far as the decoupling caps. I think following Xapp623 is overkill. It's a project by project thing, but we're in aerospace in about as noisy an environment as it gets. We use one 0805, 0.1uF, 50V cap per power pin on the FPGA (all rails). We use this approach for every IC on the board, which may also be a little overkill, but it's fairyl inexpensive. In retrospect, to save on board space, I wish I would've use 0402 caps. There's no reason not to, as long as your manufacturer can handle it. DaleArticle: 100218
Someone in my lab has been trying to get this working for more than a week. We've previously had success with the V2P's ICAP. The difficulty we're having in getting the V-4's ICAP working, combined with Xilinx's lack of support of a V-4 capable OPB ICAP controller makes me think either the tools don't currently support the V4's ICAP or there are silicon issues with one, or both, ICAPs. Why do they need two, anyway? Stephen Brac wrote: > I am trying to perform readback of the configuration for a Virtex-4. I > followed the steps in the configuration guide, but have had little > luck. The ICAP syncs up (output is 0xDF) and never enters ABORT when I > give it commands; however, when I disable the ICAP, switch to read > mode, and then re-enable the ICAP, the BUSY signal goes high, I do not > recieve any configuration data, and the ICAP output remains 0xDF. > > Has anyone experienced this problem and know a correction or had > success with readback and can inform me of their process? > > Thanks.Article: 100219
Hi all,
I am haveing trouble creating BSPs and Libraries using EDK7.1 for Linux
OS.
here is my software Platform settings
OS: linux_mvl31 1.01.a
memsize 0x8000000
plb frequency 100000000
connected peripherals : Rs232uart1, opb sysace, opb intc and ethernet
MAC
here is the error which i am getting while running the libgen
...............
........................
#--------------------------------------
# Linux BSP DRC...!
#--------------------------------------
Running generate for OS'es, Drivers and Libraries ...
#--------------------------------------
# Linux BSP generate...
#--------------------------------------
Running post_generate for OS'es, Drivers and Libraries ...
linux
linux/drivers
linux/drivers/char
linux/drivers/net
linux/drivers/net/xilinx_enet
linux/drivers/net/xilinx_enet/xemac.c
ERROR:MDT - ERROR FROM TCL:- linux_mvl31 () - bash: line 1:
/usr/local/EDK/sw/ThirdParty/bsp/linux_mvl31_v1_01_a/data/Ltypes:
Permission
denied
while executing
"exec bash -c "$ltypes $filename""
(procedure "xltype_file" line 14)
invoked from within
"xltype_file $entry"
(procedure "xltype_file" line 11)
invoked from within
"xltype_file $entry"
(procedure "xltype_file" line 11)
invoked from within
"xltype_file $entry"
(procedure "xltype_file" line 11)
invoked from within
"xltype_file $entry"
(procedure "xltype_file" line 11)
invoked from within
"xltype_file $linux"
(procedure "::sw_linux_mvl31_v1_01_a::post_generate" line 137)
invoked from within
"::sw_linux_mvl31_v1_01_a::post_generate 171701592"
ERROR:MDT - Error while running "post_generate" for processor
ppc405_0...
make: *** [ppc405_0/lib/libxil.a] Error 2
Done.
If anyone could throw light on where i amgoing wrong it will be helpful
and greatly appreciated.
with warm regards,
Chakra.
Article: 100220Stephen, Support for universities and schools is now done through the webcase system. If you submit a case, it should be answered. Do you have a case number? Austin Stephen Craven wrote: > Someone in my lab has been trying to get this working for more than a > week. We've previously had success with the V2P's ICAP. > > The difficulty we're having in getting the V-4's ICAP working, combined > with Xilinx's lack of support of a V-4 capable OPB ICAP controller > makes me think either the tools don't currently support the V4's ICAP > or there are silicon issues with one, or both, ICAPs. > > Why do they need two, anyway? > > Stephen > > > Brac wrote: > >>I am trying to perform readback of the configuration for a Virtex-4. I >>followed the steps in the configuration guide, but have had little >>luck. The ICAP syncs up (output is 0xDF) and never enters ABORT when I >>give it commands; however, when I disable the ICAP, switch to read >>mode, and then re-enable the ICAP, the BUSY signal goes high, I do not >>recieve any configuration data, and the ICAP output remains 0xDF. >> >>Has anyone experienced this problem and know a correction or had >>success with readback and can inform me of their process? >> >>Thanks. > >Article: 100221
Hi, I found that the delay value of the element FDDRCPE is 100 ns after running a timing simulation. Is it supposed to be so high? (to confirm it, I also ran a separate simulation of this single element and with different clk frequencies) FDDRCPE is "Dual Data Rate D Flip-Flop with Clock Enable and Asynchronous Preset and Clear", used when interfacing DDR with FPGA. It is present in the simlibs library. I'm using ISE 8.1 (and found the same thing in 7.1 too) If it is supposed to be that high, what may be the reason behind it? See a related post here: http://groups.google.co.in/group/comp.arch.fpga/browse_thread/thread/790b589a01726678/66426daa7240b82e?lnk=st&q=fddrcpe&rnum=3&hl=en#66426daa7240b82e Thanks and Regards, MilindArticle: 100222
Stephane, http://direct.xilinx.com/bvdocs/appnotes/xapp265.pdf Is the applicable note for VII/VII Pro family. Austin sjulhes wrote: > Hi, > > We have to interface a V2Pro with a DSP's communication ports which have > LVDS links up to 500Mhz ( taken from datasheet ). > > We have some experience on V2Pro LVDS I/O but at slow speed and we are > wondering what speed we will be able to reach with this LVDS DSP link. > > DSP and FPGA are on the same board at a reasonnable distance ( something > like 10-15 cm ). > > Does someone has a feedback on V2P high speed LVDS IO implementation ? > Are there special tips to use ? > > Any link is welcomed. > > Thanks for your help. > > Stephane. > >Article: 100223
try writing them? or use mixed lang simulation? AnttiArticle: 100224
I don't know if we do or not, but I'll check. In the past I had been rejected from WebCase support as a student, but I'll pass along that support is now available. Thank you, Stephen
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Threads starting:
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