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Messages from 103875

Article: 103875
Subject: Re: How do I use the DDS core in a verilog flow?
From: "xilinx_user" <barrinst@ix.netcom.com>
Date: 13 Jun 2006 15:25:31 -0700
Links: << >>  << T >>  << A >>

langwadt@ieee.org wrote:
> xilinx_user skrev:
>
> > langwadt@ieee.org wrote:
> > > xilinx_user skrev:
> > >
> > > > Aurelian Lazarut wrote:
> > > > > just rename, or move these *.v files (behavioral models) from your way,
> > > > > and make sure the edifs are into the working directory, and should work.
> > > > > Aurash
> > > > > / /\/\ Aurelian Lazarut
> > > > > \ \  / System Verification Engineer
> > > > > / /  \ Xilinx Ireland
> > > > > phone:	353 01 4032639
> > > > > fax:	353 01 4640324
> > > >
> > > > I am still having trouble.
> > > >
> > > > I have a working directory called "exhaust." In this directory I have
> > > > the following:
> > > >
> > > > xyz.v
> > > > sine_dds.edn
> > > >
> > > > File xyz.v contains the following:
> > > >
> > > > module xyz(CLK,WE,SCLK,WE,A,SINE);
> > > > input CLK,WE,SCLK;
> > > > input [4:0] A;
> > > > output [20:0] SINE;
> > > >
> > > >
> > > >
> > > > sine_dds sine_new(
> > > > 	.DATA(DATA),
> > > > 	.WE(WE),
> > > > 	.A(A),
> > > > 	.CLK(CLK),
> > > > 	.CE(CE),
> > > > 	.SCLR(SCLR),
> > > > 	.SINE(SINE));
> > > > endmodule
> > > >
> > > > When I try to synthesize xyz.v, I get the following error message:
> > > >
> > > > ERROR:HDLCompilers:87 - "xyz.v" line 10 Could not find module/primitive
> > > > 'sine_dds'
> > > >
> > > > line 10 is "sine_dds sine_new("
> > > >
> > > >
> > > > I am lost, and I do not know what I am doing wrong. By the way I am
> > > > using webpack 8.1
> > > >
> > > > Art
> > >
> > > Coregen should also have generated a sine_dds.v file, add that  to the
> > > project
> > >
> > > -Lasse
> >
> >
> > sine_dds.v is the simulation file. From what I understand it cannot be
> > used for sythesis - only the edif file. Besides Aurelian Lazarut
> > already stated that I need to remove these from the working direcotyr.
> > It would appear something else is going on.
>
> sine_dds.v has the module definition for synthesis and enclosed in
> translate_off/translate_on the stuff for simulation.
>
> but if you don't want to listen ... ;)
>
> -Lasse

Sir,

Your comment: "but if you don't want to listen ... ;) " is not helpful.
I originally had the .v file in  the directory and it did not work.
Aurelian Lazarut, who is a System Verification Engineer
for Xilinx Ireland said to remove them and make sure all the edif files
are in the working directory. As he works for Xilinx I am inclined to
take his word.

Just for the record, the comment in the .v file is: "This file cannot
be synthesized and should only be used with supported simulation
tools."

I am sorry you take offense but I am losing time in getting the answer
I need.


Article: 103876
Subject: Quartus 6.0 and VCS
From: Michael Laajanen <michael_laajanen@yahoo.com>
Date: Wed, 14 Jun 2006 01:00:57 +0200
Links: << >>  << T >>  << A >>
Hi,

Why is timing simulation with VCS-MX not supported?

/michael

Article: 103877
Subject: Re: FSM state minimization with ISE?
From: "JustJohn" <john.l.smith@titan.com>
Date: 13 Jun 2006 16:28:13 -0700
Links: << >>  << T >>  << A >>
Mike Treseler wrote:
> backhus wrote:
>
> > I just tried to minimize a simple statemachine with ISE8.1 and wondered
> > that there is no effect, while the machine itself is an ideal target for
> > state minimization. (It's a lecture example fur just that purpose)
>
> If state encoding is set to AUTO
> you are getting a one-hot encoding
> which is not optimum in this case.
> Might be a good subject for a lecture :)
>
> Quartus says
> 13 flops and 17 luts for one-hot
>   4 flops and 13 luts for binary
>
> What did you get?
>
>             -- Mike Treseler

(Interesting post. Eilert asks about ISE 8.1, Mike [who usually gives
good answers] responds with wrong info on AUTO setting, and odd info on
Quartus...it's way past April 1st)

Eilert,

   I agree with Mike that you should give your results. If you can't
get any improvement, maybe you already have the best you can get.

  For your posted circuit, XST in ISE 8.1 with global setting
"-fsm_encoding auto" gives:

 Number of Slice Flip Flops:             4
 Number of 4 input LUTs:                10
when compiled to a virtex2 (Assigned states are binary sequential).

Given 15 states, you can't do any better than 4 FFs!

Asking for "one-hot" gives:
 Number of Slice Flip Flops:            15
 Number of 4 input LUTs:                19

Eilert, RTFM (Read The Fine Manual). In the XST manual, you can find
out how to individually specify the state encoding, with a selection
of:

"auto, one-hot, compact, sequential, gray, johnson, speed1, and user".

Mike,
  Does Quartus really make a one-hot w/ 13 FFs for a 15 state machine?


Article: 103878
Subject: Re: FSM state minimization with ISE?
From: Tommy Thorn <tommy-usenet_AT_numba-tu.com@remove.this>
Date: Tue, 13 Jun 2006 16:44:55 -0700
Links: << >>  << T >>  << A >>
JustJohn wrote:
> (Interesting post. Eilert asks about ISE 8.1, Mike [who usually gives
> good answers] responds with wrong info on AUTO setting, and odd info on
> Quartus...it's way past April 1st)
...
> Given 15 states, you can't do any better than 4 FFs!
...
 >   Does Quartus really make a one-hot w/ 13 FFs for a 15 state machine?

I could be wrong, but I think you missed the point.  The OP's FSM is 
redundant (which is the whole point) and can be reduced to a smaller FSM 
with the same behaviour.  This minimization is similar to how you derive 
a DFSM from an NFSM (widely used in regexp).

Without having gone through the whole exercise, the Quartus results 
suggests that you can merge at least three state of the original machine.

Mike post was relevant and informative.

Tommy

Article: 103879
Subject: Re: FSM state minimization with ISE?
From: "JustJohn" <john.l.smith@titan.com>
Date: 13 Jun 2006 17:08:06 -0700
Links: << >>  << T >>  << A >>

Tommy Thorn wrote:
> I could be wrong, but I think you missed the point.  The OP's FSM is
> redundant (which is the whole point) and can be reduced to a smaller FSM
> with the same behaviour.  This minimization is similar to how you derive
> a DFSM from an NFSM (widely used in regexp).
>
> Without having gone through the whole exercise, the Quartus results
> suggests that you can merge at least three state of the original machine.
>
> Mike post was relevant and informative.
>
> Tommy

 Thanks Tommy! I stand corrected...
But note that the state minimization increases LUT usage...I suppose it
might decrease decoding H/W elsewhere... but how is does one specify
exactly what sort of optimization is wanted? Personally, I wouldn't
want states eliminated unless I explicitly said to do it.


Article: 103880
Subject: Re: FSM state minimization with ISE?
From: Tommy Thorn <tommy-usenet_AT_numba-tu.com@remove.this>
Date: Tue, 13 Jun 2006 17:14:41 -0700
Links: << >>  << T >>  << A >>
JustJohn wrote:
>  Thanks Tommy! I stand corrected...
> But note that the state minimization increases LUT usage...I suppose it
> might decrease decoding H/W elsewhere... but how is does one specify
> exactly what sort of optimization is wanted? Personally, I wouldn't
> want states eliminated unless I explicitly said to do it.

Where did you get the LUT usage increase from?  As we don't have the 
number of LUTs for the original FSM w/o minimization, I don't follow the 
conclusion.

AFAICT, state minimization should always result in fewer or same number 
of LUTs, assuming the same encoding strategy.

IMO, redundant FSM are unlikely when written by hand, but much more 
likely when autogenerated.

Tommy

Article: 103881
Subject: Re: FSM state minimization with ISE?
From: Tommy Thorn <tommy-usenet_AT_numba-tu.com@remove.this>
Date: Tue, 13 Jun 2006 18:01:08 -0700
Links: << >>  << T >>  << A >>
backhus wrote:
> Hi everybody,
> I just tried to minimize a simple statemachine with ISE8.1 and wondered 
> that there is no effect, while the machine itself is an ideal target for 
> state minimization. (It's a lecture example fur just that purpose)

I guess that ISE and Quartus just doesn't do state minimization 
(probably because real designs aren't redundant).

I was waiting for a compile, so I tried it by hand.  S8, S9, S10, S12, 
S13, and S14 are clearly identical so they can all be replaced by S8, 
which leads to new identical state etc.  My final machine had only six 
states:

    TYPE state IS (S0, S1, S3, S4, S7, S8);
    ....
          WHEN S0 => Y <= '0';
                     ns<= S1;
          WHEN S1 => Y <= '0';
		    IF (X = '0') THEN
                         ns<= S3;
                     ELSE
                         ns<= S4;
                     END IF;
          WHEN S3 => Y <= '0';
		    IF (X = '0') THEN
                         ns<= S7;
                     ELSE
                         ns<= S8;
                     END IF;
          WHEN S4 => Y <= '0'; ns <= S8;
          WHEN S7 => Y <= '0'; ns <= S0;
          WHEN S8 => IF (X = '0') THEN
                         Y <= '0';
                     ELSE
                         Y <= '1';
                     END IF;
                     ns <= S0;

Is this correct and was this the kind of optimization you had expected 
ISE to perform?

Tommy

Article: 103882
Subject: null waveform element and webpack
From: "nomalus" <danny.j.voils@intel.com>
Date: 13 Jun 2006 18:07:19 -0700
Links: << >>  << T >>  << A >>
Got a quick newbee question. I'm using some source files from the VHDL
cookbook which describe a simple CPU. Many of the files use null
waveform elements:

architecture behaviour of buffer_32 is
begin
	b_driver: process (en, a)
	begin
		if en = '1' then
			b <= a after Tpd;
		else
			b <= null after Tpd;
		end if;
	end process b_driver;
end behaviour;

This analyzes fine with GHDL, but when I try to synthesize this using
the Xilinx webpack, I get the following error:

Line 63. null waveform element is not supported.

Anyone know of a workaround for this?

Thanks in advance


Article: 103883
Subject: Re: FSM state minimization with ISE?
From: backhus <nix@nirgends.xyz>
Date: Wed, 14 Jun 2006 08:45:00 +0200
Links: << >>  << T >>  << A >>
Hi Tommy,
while your solution is not really correct(in s0 you have to branch into 
two states according to X), at least you got the point.
In fact States 7 to 10 and 11 to 14 are equivalent and each group can be 
reduced to on state. Furtermore states 3,4  and 5,6  are equivalent too.

After all it results in 7 States.

ISE Generates
15 FFs in OneHot and
4FFs (with 15states encoded) in the binary encodings.

Quartus seems to eliminate two states, possibly the pairs 3,4 and 5,6.
(Yes Mike, it is a subject for a lecture. Our students have to do the 
minimization. By pen&paper in the 3rd semester and with DesignCompiler 
in the higher semesters)


So, what I expected from ISE is that it performs at least as good as a 
3rd semester student. :-)

With OneHot the FFs should be reduced to 7 which saves over 50%. And the 
combinatonal Increase, well for this example I dobt that there is any 
significant.

For binary encoding only one FF is saved, but the encoding will fit into 
one LUT (3 Statebits + X) instead of two LUTs (4 Statebits + X) in the 
non-minimized solution.

(John, I mentioned in my first posting that dc does a minimization, so a 
saving in FFs could be expected. Furthermore I read the manual before 
and found a clear statement, that "Xilinx® recommends that you use
enumerated type encoding to specify the states and use the Finite State 
Machine (FSM) extraction commands to extract and encode the state 
machine as well as to perform state minimization and optimization 
algorithms." [ 8.1 synthesis and Simulation Design Guide, p.128])

The mentioned part about "extraction commands" seems to come from some 
older ABEL Manual for CPLDs. Everything else there describes HDL 
designs. Is it a copy&paste error of the manual editor?

So, the original Question still needs an answer. Is ISE capable of 
performing State minimization? The above cited manual says so, but the 
experiance holds against it.

Best regards
  Eilert

Tommy Thorn schrieb:
> backhus wrote:
>> Hi everybody,
>> I just tried to minimize a simple statemachine with ISE8.1 and 
>> wondered that there is no effect, while the machine itself is an ideal 
>> target for state minimization. (It's a lecture example fur just that 
>> purpose)
> 
> I guess that ISE and Quartus just doesn't do state minimization 
> (probably because real designs aren't redundant).
> 
> I was waiting for a compile, so I tried it by hand.  S8, S9, S10, S12, 
> S13, and S14 are clearly identical so they can all be replaced by S8, 
> which leads to new identical state etc.  My final machine had only six 
> states:
> 
>    TYPE state IS (S0, S1, S3, S4, S7, S8);
>    ....
>          WHEN S0 => Y <= '0';
>                     ns<= S1;
>          WHEN S1 => Y <= '0';
>             IF (X = '0') THEN
>                         ns<= S3;
>                     ELSE
>                         ns<= S4;
>                     END IF;
>          WHEN S3 => Y <= '0';
>             IF (X = '0') THEN
>                         ns<= S7;
>                     ELSE
>                         ns<= S8;
>                     END IF;
>          WHEN S4 => Y <= '0'; ns <= S8;
>          WHEN S7 => Y <= '0'; ns <= S0;
>          WHEN S8 => IF (X = '0') THEN
>                         Y <= '0';
>                     ELSE
>                         Y <= '1';
>                     END IF;
>                     ns <= S0;
> 
> Is this correct and was this the kind of optimization you had expected 
> ISE to perform?
> 
> Tommy

Article: 103884
Subject: Re: how to readback a frame
From: "Nicky" <harbinxiaoting@hit.edu.cn>
Date: 14 Jun 2006 00:09:35 -0700
Links: << >>  << T >>  << A >>

Vivian Bessler =E5=86=99=E9=81=93=EF=BC=9A

> Hi Nicky,
> Xtclsh is a tcl shell included with ISE.  The ChipScope user manual
> describes how to use it for JTAG operations.
>
> Vivian
>
> --
> Sandbyte
hi Vivian,
I have studied chipScope Manual, but I don't think using chipScope can
readback a frame. So I tried Jbits 3.0.As you mentioned, it only
support Virtex-II, but it doesn't matter, I can change my FPGA. Now, I
am trying to using Jbits upon a free software Hoplite. It seems can
readback configration data, modify and download it to FPGA, but I am a
beginner with both Jbits and Hoplite.Even though they supply a manual,
I still want a simple example of a real implememt. So, if you have any
suggention, I will be really thankful!

regards

sincerely
Nicky


Article: 103885
Subject: Re: FSM state minimization with ISE?
From: backhus <nix@nirgends.xyz>
Date: Wed, 14 Jun 2006 09:49:10 +0200
Links: << >>  << T >>  << A >>
Hi Tommy, John and Mike
I posted some results discussion as a reply to Tommys direct reply for 
my OP.
Mike, interesting result from Quartus. At least it seems to do some 
optimization. Is there anything in the synthesis report that gives 
information about what exactly was done to the FSM?


John, if a synthesis Tool optimizes away equivalent states you only will 
have to worry about it when you try to compare your timing sim with the 
behavioral sim. It causes some nasty work though, but from minimization 
one should expect area savings or speed increase, which might be useful 
if you are designing on the edge of performance.


Tommy, I mostly agree that handwritten/designed FSMs seldom have 
equivalent states. Because they are often (not always) quite small. But 
when one has to design a large and more complicated algorithm and want 
to keep the models source readable or for an easier analysis of the 
simulation results, then equivalent states may appear intended or 
accidental.
Autogeneration of FSMs is surely a source of such things.

Best regards
   Eilert


Tommy Thorn schrieb:
> JustJohn wrote:
>>  Thanks Tommy! I stand corrected...
>> But note that the state minimization increases LUT usage...I suppose it
>> might decrease decoding H/W elsewhere... but how is does one specify
>> exactly what sort of optimization is wanted? Personally, I wouldn't
>> want states eliminated unless I explicitly said to do it.
> 
> Where did you get the LUT usage increase from?  As we don't have the 
> number of LUTs for the original FSM w/o minimization, I don't follow the 
> conclusion.
> 
> AFAICT, state minimization should always result in fewer or same number 
> of LUTs, assuming the same encoding strategy.
> 
> IMO, redundant FSM are unlikely when written by hand, but much more 
> likely when autogenerated.
> 
> Tommy

Article: 103886
Subject: Re: how to readback a frame
From: Vivian Bessler <vivian.bessler.nospam@sandbyte.com>
Date: Wed, 14 Jun 2006 10:22:07 +0100
Links: << >>  << T >>  << A >>
Hi Nicky,
You can definitely use the tcljtag.tcl file included with ChipScope to 
readback a frame.  The library is documented in Chapter 5: Tcl/JTAG 
Interface.  You need to combine this user manual information with some 
of the Xilinx application notes on readback via JTAG.  JBITs may be a 
better bet since it supports readback as a basic feature.  For questions 
regarding JBITs your best to join JBits@yahoogroups.com.  My guess is 
that JBITs will offer you high-level readback functions.  For lower 
level stuff your probably better off using the tcljtag.tcl approach. 
Which approach you choose really depends on what your application is.

Vivian

--
Sandbyte

Article: 103887
Subject: Re: Current from FPGA pins to ADC
From: m_oylulan@hotmail.com
Date: 14 Jun 2006 02:44:53 -0700
Links: << >>  << T >>  << A >>

Peter Alfke wrote:
> Mees, don't worry about the currents, just make sure that the voltage
> ramges for FPGA and ADC are compatible.
> Peter Alfke, Xilinx
> =======
> m_oylulan@hotmail.com wrote:
> > I want to use a Spartan II chip to drive two ADCs. The ADC spec says
> > that the input current on the SCLK pin is +/-0.5uA max and 10nA
> > typically. Similary the input current on the CS pin is 10nA typically.
> > The absolute maximum ratings for the same ADC state that the maximum
> > input current to any pins (except supplies) is +/-10mA. I'm using the
> > LVTTL standard and can only specify the drive current to a minimum of
> > 2mA. Will I be doing the ADCs potential damage if I specify 2mA to
> > drive the SCLK and CS pins?
> >
> > Thanks,
> > Mees

Thanks for the responses.
I am not sure if anyone is still reading this, but I've tested
the ADC with worrying results. When I apply a sine wave to the input
of the ADC with no SCLK or CS signal from FPGA, I can clearly
see the sinewave on an oscilloscope. When I then use the FPGA
to drive the CS and SCLK pins, the pure sine wave input to the
ADC is no longer visible on the scope. What I see instead is what
appears to be a bouncing noisy signal with sharp peaks and troughs.
Similarly the ADC output consists of sharp periodic spikes. My SLCK
and CS signals don't look very clean on the scope. How can I improve
the quality of these if I need to drive the ADC from the FPGA? What
else should I consider to resolve this problem?

Thanks,

Mees


Article: 103888
Subject: Re: null waveform element and webpack
From: backhus <nix@nirgends.xyz>
Date: Wed, 14 Jun 2006 12:14:04 +0200
Links: << >>  << T >>  << A >>
Hi,
you are trying to synthesize a model that is only useful (and 
meaningful) for simulation.

For a deeper explanation of assigning the null-statement to a signal you 
better ask the guys at comp.lang.vhdl.

The synthesis tools ignore the after Statements, but can't ignore a 
missing assignment to signal b, so you get an error.

What value should be assigned to b when en ='0' ?
"null" is nothing physical, it can either be '0','1' or 'Z'.
So my best guess is :

  architecture behaviour of buffer_32 is
  begin
    b_driver: process (en, a)
    begin
      if en = '1' then
        b <= a ;
      else
        b <= (others=>'Z'); -- b may be a vector
      end if;
    end process b_driver;
  end behaviour;

Have a nice synthesis
   Eilert

nomalus schrieb:
> Got a quick newbee question. I'm using some source files from the VHDL
> cookbook which describe a simple CPU. Many of the files use null
> waveform elements:
> 
> architecture behaviour of buffer_32 is
> begin
> 	b_driver: process (en, a)
> 	begin
> 		if en = '1' then
> 			b <= a after Tpd;
> 		else
> 			b <= null after Tpd;
> 		end if;
> 	end process b_driver;
> end behaviour;
> 
> This analyzes fine with GHDL, but when I try to synthesize this using
> the Xilinx webpack, I get the following error:
> 
> Line 63. null waveform element is not supported.
> 
> Anyone know of a workaround for this?
> 
> Thanks in advance
> 

Article: 103889
Subject: ARM9 DDR interface
From: "subint" <subin.82@gmail.com>
Date: 14 Jun 2006 04:01:17 -0700
Links: << >>  << T >>  << A >>
Hai guys..

       I need to setup a V4MB board and interface it with ARM9 core. Is
Any one know the good materials or even code to interface a 16bit wide
DDR SDRAM with ARM9 core.
Regards
Subin


Article: 103890
Subject: Re: Current from FPGA pins to ADC
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Wed, 14 Jun 2006 14:01:05 +0200
Links: << >>  << T >>  << A >>
m_oylulan@hotmail.com schrieb:

> Thanks for the responses.
> I am not sure if anyone is still reading this, but I've tested
> the ADC with worrying results. When I apply a sine wave to the input
> of the ADC with no SCLK or CS signal from FPGA, I can clearly
> see the sinewave on an oscilloscope. When I then use the FPGA

I guess you are probing the ADC input. So far so good.

> to drive the CS and SCLK pins, the pure sine wave input to the
> ADC is no longer visible on the scope. What I see instead is what
> appears to be a bouncing noisy signal with sharp peaks and troughs.

Could may many problems. Is your probe connected properly? Properly 
ground connection? Is the layout done properly (ADC require special care 
to avoid crossing of digital and analog currents.)

> Similarly the ADC output consists of sharp periodic spikes. My SLCK
> and CS signals don't look very clean on the scope. How can I improve

Looks like bad probing. Probe properly.

> the quality of these if I need to drive the ADC from the FPGA? What
> else should I consider to resolve this problem?

Apply basic engineering. Proper probing, layout. try to use slow FPGA 
output with low drive current (4mA should do if clock frequencies are 
below say 50 MHz)

Regards
Falk

Article: 103891
Subject: Re: IDELAY clock spec. in Xilinx V4
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 14 Jun 2006 13:17:55 +0100
Links: << >>  << T >>  << A >>
Hi Guys,
OK, many thanks for that, it'd be cool if you could find out the actual 
speed.
Thanks again, Syms.

"Peter Alfke" <peter@xilinx.com> wrote in message 
news:1150229559.983503.310330@p79g2000cwp.googlegroups.com...
>I turned over some stones:
> The stepping of the IDELAY taps can definitely be done at the IDELAY
> output clock rate, or at 250 MHz, and probably even faster. It's just a
> counter driving a decoder, so I could imagine that it is even much
> faster. But 250 MHz is no problem...
> Peter Alfke, Xilinx Applications
> =================
> Austin Lesea wrote:
>> Symon,
>>
>> OK, I looked for it, and I can't find it.
>>
>> This clock is used for the control of the IDELAY block, and our usual
>> goal is to have control stuff be able to run at the fabric speed (~400
>> MHz), but I will go find out what it actually is.  Sometimes (rarely)
>> these sorts of interfaces can not run at the full fabric speed.
>>
>> Austin
>>
>>
> 



Article: 103892
Subject: ISE 7.1i reference design for Virtex-II PRO FF672 kit (Avnet)
From: "Vivek Menon" <vivek.menon79@gmail.com>
Date: 14 Jun 2006 05:56:25 -0700
Links: << >>  << T >>  << A >>
Hi..
I am trying to implement the Rocket I/O interface on the Xilinx
Virtex-II Pro FF672 kit from Avnet. The reference design is EDK based
and uses the powerPC. I would like to know the procedure for
implementing Rocket I/O on this board using the logic fabric ( I
presume that the power PC just slows down everything and moreover the
logic fabric would be better suited for my  application). I am using
the Fibre channel for connection. Aurora is not an option here due to
limited licenses.
So one option I am currently exploring is the Architecture wizard which
gives me a HDL interface for the Rocket I/O. But I am not sure about
exactly defining the .ucf file for the different pins. If anybody has a
pointer to this problem or some sort of info on the pinouts/ucf file,
please pass it on.
Thanks in advance,
Vivek


Article: 103893
Subject: Re: How do I use the DDS core in a verilog flow?
From: Joseph Samson <user@example.net>
Date: Wed, 14 Jun 2006 13:06:27 GMT
Links: << >>  << T >>  << A >>
xilinx_user wrote:
> Sir,
> 
> Your comment: "but if you don't want to listen ... ;) " is not helpful.
> I originally had the .v file in  the directory and it did not work.
> Aurelian Lazarut, who is a System Verification Engineer
> for Xilinx Ireland said to remove them and make sure all the edif files
> are in the working directory. As he works for Xilinx I am inclined to
> take his word.
> 
> Just for the record, the comment in the .v file is: "This file cannot
> be synthesized and should only be used with supported simulation
> tools."
> 
> I am sorry you take offense but I am losing time in getting the answer
> I need.
> 
Here is the recipe that always works for me:
I use the ISE GUI. When I have a CoreGen model instantiated in my 
Verilog, ISE leaves a place for the .xco file. In your example, your 
core is called sine_new, so there will be a sine_new.xco. Add that 
source to your project.

Among other files, CoreGen will generate sine_new.edn and sine_new.v . 
You should place these files in same directory as your *.ise file (the 
ISE project file). In general, you can't go wrong if you put every file 
that CoreGen creates into the directory that has your *.ise file.

---
Joe Samson
Pixel Velocity

Article: 103894
Subject: Re: How do I use the DDS core in a verilog flow?
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Wed, 14 Jun 2006 14:40:33 +0100
Links: << >>  << T >>  << A >>
I think Lasse is right here, the *.v file will act like a "blackbox 
placeholder" (or at least it should)
I have to admit that the message in the header is misleading that this 
file will be used for simulation only, hence the confusion.
however the "normal" flow will be to keep the *.xco file attached to the 
design tree, so Joe's suggestion will hold here.

Aurash

Joseph Samson wrote:

> xilinx_user wrote:
>
>> Sir,
>>
>> Your comment: "but if you don't want to listen ... ;) " is not helpful.
>> I originally had the .v file in  the directory and it did not work.
>> Aurelian Lazarut, who is a System Verification Engineer
>> for Xilinx Ireland said to remove them and make sure all the edif files
>> are in the working directory. As he works for Xilinx I am inclined to
>> take his word.
>>
>> Just for the record, the comment in the .v file is: "This file cannot
>> be synthesized and should only be used with supported simulation
>> tools."
>>
>> I am sorry you take offense but I am losing time in getting the answer
>> I need.
>>
> Here is the recipe that always works for me:
> I use the ISE GUI. When I have a CoreGen model instantiated in my 
> Verilog, ISE leaves a place for the .xco file. In your example, your 
> core is called sine_new, so there will be a sine_new.xco. Add that 
> source to your project.
>
> Among other files, CoreGen will generate sine_new.edn and sine_new.v . 
> You should place these files in same directory as your *.ise file (the 
> ISE project file). In general, you can't go wrong if you put every 
> file that CoreGen creates into the directory that has your *.ise file.
>
> ---
> Joe Samson
> Pixel Velocity



-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     

Article: 103895
Subject: boot mode pins on Spartan3
From: "Marco" <marco@marylon.com>
Date: 14 Jun 2006 07:12:51 -0700
Links: << >>  << T >>  << A >>
Hi,
on my AD Spartan3 board I have 3 jumpers selecting the boot mode M0-2.
They let you connect each pin to GND, so if you place no jumper on a
ceretain pin think you get a high signal ('1') on that mode pin. Why?
I was supposed to have internal pullups only on the I/Os, enabled
during the configuration stage by the HSWAP_EN and not also on those
M0-2 pins.
In my board should I do it the same way or shoud I consider a connector
in which jumpers could link those pins to Vcc for '1' or to GND for
'0'?
Thanks,
Marco


Article: 103896
Subject: Xilinx XST Error
From: "Alex McHale" <alexmchale@gmail.com>
Date: 14 Jun 2006 07:30:16 -0700
Links: << >>  << T >>  << A >>
At the bottom of this post is the code.

First, let me say that I have run this "program" through a TBW, and it
seems to simulate correctly.

Second, I'll describe what this module does (or at least, should do).
8 bytes (along with 5 address bits that are carried).  When 8 bytes
come in, it outputs all 8 at once in a 64 bit value (again, along with
the carried 5 bit address).

The latch line is mostly simply passed through, except that it is
additionally used to reset the buffer pointer.

Am I making this task overly complex?  If not, what's going on with it?

When I run the "implement design" task, I get the following warnings /
errors:

=========================================================================
*                            HDL Analysis
*
=========================================================================
Analyzing Entity <queue> (Architecture <behavioral>).
WARNING:Xst:790 - "C:/xilinx/tutorial/queue.vhd" line 46: Index
value(s) does not match array range, simulation mismatch.
INFO:Xst:1433 - Contents of array <data_buffer> may be accessed with an
index that exceeds the array size. This could cause simulation
mismatch.
ERROR:Xst:827 - "C:/xilinx/tutorial/queue.vhd" line 23: Signal
DATA_OUT<57> cannot be synthesized, bad synchronous description.

I'm indeed new to VHDL, and I'm just not clear on what the problem is
here.  Any help would be greatly, greatly appreciated.  I can supply a
zip of the project to anyone interested in helping enough for that.

Thanks!

Alex McHale

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity queue is
    Port ( DATA_IN : in  STD_LOGIC_VECTOR (7 downto 0);
           LATCH_IN : in  STD_LOGIC;
           CLOCK_IN : in  STD_LOGIC;
                          ADDRESS_IN : in STD_LOGIC_VECTOR (4 downto
0);
           DATA_OUT : out  STD_LOGIC_VECTOR (63 downto 0);
           LATCH_OUT : out  STD_LOGIC;
           CLOCK_OUT : out  STD_LOGIC;
                          ADDRESS_OUT : out STD_LOGIC_VECTOR (4 downto
0));
end queue;

architecture Behavioral of queue is
        type ram_type is array (0 to 7) of STD_LOGIC_VECTOR (7 downto
0);
        signal data_buffer : ram_type := ("00000000", "00000000",
"00000000",
"00000000", "00000000", "00000000", "00000000", "00000000");
        signal buffer_write_offset : STD_LOGIC_VECTOR (3 downto 0) :=
"0000";
        signal address_buffer : STD_LOGIC_VECTOR (4 downto 0) :=
"00000";
begin
        process (CLOCK_IN, LATCH_IN)
        begin
                if rising_edge( LATCH_IN ) then
                        buffer_write_offset <= "0000";
                        LATCH_OUT <= '1';
                elsif falling_edge( LATCH_IN ) then
                        LATCH_OUT <= '0';
                elsif rising_edge( CLOCK_IN ) then
                        CLOCK_OUT <= '0';

                        if buffer_write_offset = "0000" then
                                DATA_OUT( 7 downto 0 ) <= data_buffer(
0 );
                                DATA_OUT( 15 downto 8 ) <= data_buffer(
1 );
                                DATA_OUT( 23 downto 16 ) <=
data_buffer( 2 );
                                DATA_OUT( 31 downto 24 ) <=
data_buffer( 3 );
                                DATA_OUT( 39 downto 32 ) <=
data_buffer( 4 );
                                DATA_OUT( 47 downto 40 ) <=
data_buffer( 5 );
                                DATA_OUT( 55 downto 48 ) <=
data_buffer( 6 );
                                DATA_OUT( 63 downto 56 ) <=
data_buffer( 7 );
                                ADDRESS_OUT <= address_buffer;
                                CLOCK_OUT <= '1' after 1ns;
                        end if;

                        data_buffer( conv_integer( buffer_write_offset
) ) <= DATA_IN after
5ns;
                        address_buffer <= ADDRESS_IN after 5ns;
                        buffer_write_offset <= (buffer_write_offset +
1) and "0111" after
10ns;
                end if;
        end process;
end Behavioral;


Article: 103897
Subject: Re: boot mode pins on Spartan3
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Wed, 14 Jun 2006 07:35:26 -0700
Links: << >>  << T >>  << A >>
Marco wrote:
> Hi,
> on my AD Spartan3 board I have 3 jumpers selecting the boot mode M0-2.
> They let you connect each pin to GND, so if you place no jumper on a
> ceretain pin think you get a high signal ('1') on that mode pin. Why?
> I was supposed to have internal pullups only on the I/Os, enabled
> during the configuration stage by the HSWAP_EN and not also on those
> M0-2 pins.
> In my board should I do it the same way or shoud I consider a connector
> in which jumpers could link those pins to Vcc for '1' or to GND for
> '0'?
> Thanks,
> Marco
> 

All Xilinx devices have weak (10kohm+)internal pullups on the
configuration mode select pins.  The HSWAP_EN pin only enables/disable
the pullup on the non-dedicated pins during configuration.

If you do not connect this pin to anything else on the PCB that might
cause a current drain (like an LED) you do not need to add a dedicate
pullup resistor.

Ed McGettigan
--
Xilinx Inc.

Article: 103898
Subject: Re: boot mode pins on Spartan3
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Wed, 14 Jun 2006 15:54:40 +0100
Links: << >>  << T >>  << A >>
connect the mode pins to ground for '0' or leave them open (not 
connected) for a '1' logic
Aurash
Marco wrote:

>Hi,
>on my AD Spartan3 board I have 3 jumpers selecting the boot mode M0-2.
>They let you connect each pin to GND, so if you place no jumper on a
>ceretain pin think you get a high signal ('1') on that mode pin. Why?
>I was supposed to have internal pullups only on the I/Os, enabled
>during the configuration stage by the HSWAP_EN and not also on those
>M0-2 pins.
>In my board should I do it the same way or shoud I consider a connector
>in which jumpers could link those pins to Vcc for '1' or to GND for
>'0'?
>Thanks,
>Marco
>
>  
>


-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     

Article: 103899
Subject: Re: boot mode pins on Spartan3
From: "Marco" <marco@marylon.com>
Date: 14 Jun 2006 07:58:53 -0700
Links: << >>  << T >>  << A >>
Thanks Ed,
Marco



Ed McGettigan ha scritto:

> Marco wrote:
> > Hi,
> > on my AD Spartan3 board I have 3 jumpers selecting the boot mode M0-2.
> > They let you connect each pin to GND, so if you place no jumper on a
> > ceretain pin think you get a high signal ('1') on that mode pin. Why?
> > I was supposed to have internal pullups only on the I/Os, enabled
> > during the configuration stage by the HSWAP_EN and not also on those
> > M0-2 pins.
> > In my board should I do it the same way or shoud I consider a connector
> > in which jumpers could link those pins to Vcc for '1' or to GND for
> > '0'?
> > Thanks,
> > Marco
> >
>
> All Xilinx devices have weak (10kohm+)internal pullups on the
> configuration mode select pins.  The HSWAP_EN pin only enables/disable
> the pullup on the non-dedicated pins during configuration.
>
> If you do not connect this pin to anything else on the PCB that might
> cause a current drain (like an LED) you do not need to add a dedicate
> pullup resistor.
> 
> Ed McGettigan
> --
> Xilinx Inc.




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