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Messages from 110225

Article: 110225
Subject: ISO plb_temac driver for linux 2.4
From: "corley" <rdcorle@gmail.com>
Date: 12 Oct 2006 08:21:44 -0700
Links: << >>  << T >>  << A >>
Does anyone have the source tree for the plb_temac (ver 2.00) driver
under linux 2.4?  I am using the plb_temac on the Xilinx ML403 board.
(Also using EDK 7.1)


Article: 110226
Subject: Re: VGA timing
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 12 Oct 2006 16:22:52 +0100
Links: << >>  << T >>  << A >>
icegray@gmail.com writes:

> Hi everbody,

Hi,

> I wanna implement VGA core at 1024x768x75Hz (15" LCD Monitor) on
> Spartan3E starter kit. I have got a few question. I have tried to find
> some detialed documents for VGA timing But I can't. There are 640x480
> and 800x600 but there is no document for more resolution and refresh
> rate.

Googling vga timings gives this as the first hit, which has 1024x768
at the bottom:
http://www.epanorama.net/documents/pc/vga_timing.html
This might also be useful:
http://www.tldp.org/HOWTO/XFree86-Video-Timings-HOWTO/magic.html

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

   

Article: 110227
Subject: Re: Altera Quartus II 5.1 SP2 fails on MIF/HEX reconfig
From: "radarman" <jshamlet@gmail.com>
Date: 12 Oct 2006 08:34:56 -0700
Links: << >>  << T >>  << A >>
Subroto Datta wrote:
> Hi Radarman,
>
>    This is probably a bug in Quartus II 5.1 SP1. If you have an support
> incident opened email me the number so that we can verify it with the
> design, or zip the project archive  and emailit to me separately. We can ley
> you know if this has been fixed in 6.0 or if it is still a problem fix it
> for 6.1.
>
> Thanks,
> Subroto Datta
> Altera Corp.
>
> "radarman" <jshamlet@gmail.com> wrote in message
> news:1160531029.492131.266030@m7g2000cwm.googlegroups.com...
> >I posted a service request with Altera on this, but I thought I would
> > see if anyone else has seen this problem.
> >
> > I have written a small 8-bit microcomputer system for my Altera DE2
> > board. The system has  16kB ROM that I preinitialize with an intel .hex
> > format file.
> >
> > The design takes quite a while to fit because I want to operate it at a
> > relatively high clock rate (100MHz), so I turned on smart-compile. Now
> > that the basic hardware is functioning, and I am only changing the ROM
> > image, I would expect to simply recompile and let Quartus read in the
> > new .hex file.
> >
> > However, when I try to recompile, I get an error:
> > Internal Error: Sub-system: QATM, File: qatm_mif_update.cpp, Line: 554
> > RAM/CAM MIF reconfig failed
> > Quartus II Version 5.1 Build 216 03/06/2006 SJ Web Edition
> > Service Pack Installed:  2
> >
> > Note, the fitter doesn't (seem) to have a problem reading the .hex
> > file. I can manually rerun the fitter, and it appears to work just
> > fine. I believe the fitter is working properly because the address
> > patterns seems consistent with a hang - not an uninitialized memory.
> >
> > This is on a Windows XP workstation. The project files are mounted from
> > a file server on drive Y:.
> >
> > Thanks!
> >

The same problem occurs in 6.0, but I discovered that it works if I
convert my .hex file to .mif. For some reason, it doesn't like my .hex
initialization files.

Just out of curiosity, is there a command line utility that will
convert from .hex to .mif? I could add it to my build scripts.

Thanks!


Article: 110228
Subject: Re: Am I blind or? (Virtex-4 issues)
From: "Antti" <Antti.Lukats@xilant.com>
Date: 12 Oct 2006 08:42:16 -0700
Links: << >>  << T >>  << A >>
Peter Ryser schrieb:

> Sylvain is right. In Virtex-4 the user can control CCLK and the Done pin
> through the STARTUP block. This feature was added in combination with
> the USR_ACCESS_VIRTEX4 port.
>
> The combination allows for uniform access to data appended to the
> configuration bitstream in all configuration modes (master/slave
> serial/selectmap and JTAG). Independent of the configuration mode the
> data will always show up the exact same way which makes it much easier
> for a user to use.
>
> XAPP719 explains how that feature can be used to configure the PPC
> caches from a Platform Flash. However, that's only one possible use
> case. Other use case do not involve the PPC but are for loading
> persistent user data.
>
> - Peter
>
Dear Peter,

I know very well that
1) STARTUP provides access to CCLK and DONE
2) USR_ACCESS can be used for many nice thing

however if it is required to read the DIN from the FPGA
fabric then it doesnt help ASFAIK ?

I could get pieces of data from external memory if
it is specially prepared, i know.

but in my case i really need the DIN as it available
in ALL OTHER Xilinx FPGA's ***EXCEPT*** Virtex-4

the configuration is provided in master serial mode
from external SPI flash, the Flash DO goes to FPGA DIN
SCK to CCLK

everything would be fine, but in virtex-4 the DIN is no
longer accessible or is there some trick ??

Antti


Article: 110229
Subject: Coregen GMII embedded ethernet MAC
From: "Rune D. Jørgensen" <RUNE_dahl@hotmailREMOVE_THIS.com>
Date: 12 Oct 2006 15:55:22 GMT
Links: << >>  << T >>  << A >>
I have been trying to implement Virtex-4 Tri-Mode Embedded Ethernet MAC 
Wrapper v4.3(GMII) from coregen in ISE. All guides tell me to use a VHO-
file, which should contain an instantiation template, but coregen doesn't 
create such template file for this core. And the template in ISE is blank. 
I should also get an edn or ngc netlist file which isn't there either.

The user guide specifies that I should use the "v4_emac_v4_3.vhd" as 
instantiation template, but that file is the lowest level wrapper, which 
means that it doesn't include the GMII interface and clock generators that 
resides in the higher layer wrappers.

Which files do I need from the generated coregen library? 


Any help or comment is highly appreciated!


Data:
ISE 8.2i SP3.
IP update 2.
Board: AVnet/memec Virtex4-sf363-10

-- 
Rune D. Jørgensen
Denmark

Article: 110230
Subject: Re: Altera Quartus II 5.1 SP2 fails on MIF/HEX reconfig
From: "Subroto Datta" <sdatta@altera.com>
Date: 12 Oct 2006 09:08:51 -0700
Links: << >>  << T >>  << A >>
Google hex2mif. I cannot personally vouch for the correctness of these
hex2mif converters but you can try. Anyway thanks for the lead and I
will follow up on it.

- Subroto Datta
Altera Corp.

On Oct 12, 8:34 am, "radarman" <jsham...@gmail.com> wrote:
> Subroto Datta wrote:
> > Hi Radarman,
>
> >    This is probably a bug in Quartus II 5.1 SP1. If you have an support
> > incident opened email me the number so that we can verify it with the
> > design, or zip the project archive  and emailit to me separately. We can ley
> > you know if this has been fixed in 6.0 or if it is still a problem fix it
> > for 6.1.
>
> > Thanks,
> > Subroto Datta
> > Altera Corp.
>
> > "radarman" <jsham...@gmail.com> wrote in message
> >news:1160531029.492131.266030@m7g2000cwm.googlegroups.com...
> > >I posted a service request with Altera on this, but I thought I would
> > > see if anyone else has seen this problem.
>
> > > I have written a small 8-bit microcomputer system for my Altera DE2
> > > board. The system has  16kB ROM that I preinitialize with an intel .hex
> > > format file.
>
> > > The design takes quite a while to fit because I want to operate it at a
> > > relatively high clock rate (100MHz), so I turned on smart-compile. Now
> > > that the basic hardware is functioning, and I am only changing the ROM
> > > image, I would expect to simply recompile and let Quartus read in the
> > > new .hex file.
>
> > > However, when I try to recompile, I get an error:
> > > Internal Error: Sub-system: QATM, File: qatm_mif_update.cpp, Line: 554
> > > RAM/CAM MIF reconfig failed
> > > Quartus II Version 5.1 Build 216 03/06/2006 SJ Web Edition
> > > Service Pack Installed:  2
>
> > > Note, the fitter doesn't (seem) to have a problem reading the .hex
> > > file. I can manually rerun the fitter, and it appears to work just
> > > fine. I believe the fitter is working properly because the address
> > > patterns seems consistent with a hang - not an uninitialized memory.
>
> > > This is on a Windows XP workstation. The project files are mounted from
> > > a file server on drive Y:.
>
> > > Thanks!The same problem occurs in 6.0, but I discovered that it works if I
> convert my .hex file to .mif. For some reason, it doesn't like my .hex
> initialization files.
>
> Just out of curiosity, is there a command line utility that will
> convert from .hex to .mif? I could add it to my build scripts.
> 
> Thanks!- Hide quoted text -- Show quoted text -


Article: 110231
Subject: Re: Xilinx coregen fifo
From: nbg2006@gmail.com
Date: 12 Oct 2006 09:43:22 -0700
Links: << >>  << T >>  << A >>
Thanks for the reply . I was making the silly  mistake of writing the
word twice but now I corrected it .The simulations are proper but when
i writie it onto the fpga  and check it using chipscope it gives me
data on every second sample of plb clock instead of every sample. I am
reading the fifo using plb clock but in chipscope pro I see a new data
every second sample which ruins my whole state machine inputs .i.e the
data output of fifo is maintained for 2 cycles inspite of me reading it
every cycle .
 I use plb clock for the chipscope pro samples.


Peter Alfke wrote:
> If your clock rate is reasonable, then I suspect incorrect timing
> (set-up and hold) between the WE and the write clock, so that you are
> actually writing on each clock edge (although you want to write only on
> every other one.)
> That means you write every word twice, and thus it looks as if the
> reading is at half speed.
> Peter Alfke, Xilinx
> =============
> nbg2006@gmail.com wrote:
> > I generated a fifo with block rams with two independent clocks and a
> > symmetric widths and depths.  the fifo manual digrams state that with
> > read enable high the data can be read out of the fifo every clock
> > cycle.
> > The wr_en signal is running at a half of the write cycle frequency .i.e
> > the valid data is present on the input bus every second cycle of write
> > clock. Now once the data has been written I disable the wr_en . I
> > enable the read enable and the signal is kept at constant high till the
> > fifo becomes empty.
> > I simulated the fifo and it turns out that the fifo ouputs the data
> > every second cycle with a constant high on the rd_en  pin.
> >
> > Is there something to be tweaked to make it output every clock cycle or
> > is that the peak performance?


Article: 110232
Subject: VirTex 4 mini Module
From: Eli Hughes <emh203@psu.edu>
Date: Thu, 12 Oct 2006 13:08:59 -0400
Links: << >>  << T >>  << A >>
Has anyone her had experience with this Board?  I really like these 
small modules.... Wish there were more out there.  I just want to here 
some feedback on the design or if you have had any software/hardware 
problems.

-Eli

Article: 110233
Subject: SPAM -- FPGA image processing camera
From: "JeffM" <jeffm_@email.com>
Date: 12 Oct 2006 10:11:22 -0700
Links: << >>  << T >>  << A >>
arobe100@ jaguar.com wrote:
>[SPAM] introduction of a series of modules [SPAM SPAM SPAM SPAM]

Posted from sci.electronics.design

Your Usenet history doesn't indicate a malicious pattern
http://groups.google.com/groups/search?filter=0&enc_author=4ZDzEhMAAAB4paES7Dmm4vuWn4F5UkiUWMj6vob75xS36mXc24h6ww&scoring=d
so I'll assume ignorance on your part.

http://groups.google.com/group/sci.electronics/msg/13651a897337a7a9?q=Charters+misc.industry.electronics.marketplace+Discussions+Advertisement+only-advertise+sci.electronics.design-Electronic-circuit-design

"How NOT to Advertise on Usenet" by Joel K. Furr
http://66.102.9.104/search?q=cache:CMU1z-5ywJ4J:shopsite.com/help/4.1/sc/lte/usenet.html+rude.to.advertise.*.*+*-*-*-*-*-*-the-word-forsale-or-marketplace-in-their-names+preserve.*.culture.of.open.discussion+reads-an-advertisement+*.most.pervasive.form.*.*.*.*-*+How-*-to-Advertise-on-Usenet+biz+hated+rude+lose-*-account

Continued spamming will get you one of these:
http://groups.google.com/groups/search?q=Bad-vendor+SPAMs-Usenet
http://groups.google.com/group/sci.electronics.components/msg/d1dbdc7529aed7ec?q=zz-zz+great.idea+Bad-vendor


Article: 110234
Subject: Re: Xilinx coregen fifo
From: "Peter Alfke" <peter@xilinx.com>
Date: 12 Oct 2006 10:31:22 -0700
Links: << >>  << T >>  << A >>
I am sure you are making another "silly mistake".
Just keep debugging it, carefully and methodically...
Peter Alfke
==============
nbg2006@gmail.com wrote:
> Thanks for the reply . I was making the silly  mistake of writing the
> word twice but now I corrected it .The simulations are proper but when
> i writie it onto the fpga  and check it using chipscope it gives me
> data on every second sample of plb clock instead of every sample. I am
> reading the fifo using plb clock but in chipscope pro I see a new data
> every second sample which ruins my whole state machine inputs .i.e the
> data output of fifo is maintained for 2 cycles inspite of me reading it
> every cycle .
>  I use plb clock for the chipscope pro samples.
>
>
> Peter Alfke wrote:
> > If your clock rate is reasonable, then I suspect incorrect timing
> > (set-up and hold) between the WE and the write clock, so that you are
> > actually writing on each clock edge (although you want to write only on
> > every other one.)
> > That means you write every word twice, and thus it looks as if the
> > reading is at half speed.
> > Peter Alfke, Xilinx
> > =============
> > nbg2006@gmail.com wrote:
> > > I generated a fifo with block rams with two independent clocks and a
> > > symmetric widths and depths.  the fifo manual digrams state that with
> > > read enable high the data can be read out of the fifo every clock
> > > cycle.
> > > The wr_en signal is running at a half of the write cycle frequency .i.e
> > > the valid data is present on the input bus every second cycle of write
> > > clock. Now once the data has been written I disable the wr_en . I
> > > enable the read enable and the signal is kept at constant high till the
> > > fifo becomes empty.
> > > I simulated the fifo and it turns out that the fifo ouputs the data
> > > every second cycle with a constant high on the rd_en  pin.
> > >
> > > Is there something to be tweaked to make it output every clock cycle or
> > > is that the peak performance?


Article: 110235
Subject: How much function of FPGA Editor is open in webpack?
From: "fl" <rxjwg98@gmail.com>
Date: 12 Oct 2006 10:31:47 -0700
Links: << >>  << T >>  << A >>
Hi,
New to Xilinx webpack 8.2. I find FPGA Editor is helpful in
understanding FPGA structure. FPGA Editor is an advanced feature, I
know. Although I don't want to learn much about that, I still want to
have the basic application. It seems the Manual Route function in FPGA
Editor is not open in webpack (I can use the Auto Route, though), or I
don't find the trick? I have read its help and manuals with no answer.
And where I can know the exact function and power of the webpack, in a
brochure?

Thank you very much.


Article: 110236
Subject: Re: How much function of FPGA Editor is open in webpack?
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 12 Oct 2006 10:55:54 -0700
Links: << >>  << T >>  << A >>
fl,

http://toolbox.xilinx.com/docsan/xilinx7/help/iseguide/html/ise_imp_strategies_using_fpga_editor.htm

might help...

Austin

fl wrote:
> Hi,
> New to Xilinx webpack 8.2. I find FPGA Editor is helpful in
> understanding FPGA structure. FPGA Editor is an advanced feature, I
> know. Although I don't want to learn much about that, I still want to
> have the basic application. It seems the Manual Route function in FPGA
> Editor is not open in webpack (I can use the Auto Route, though), or I
> don't find the trick? I have read its help and manuals with no answer.
> And where I can know the exact function and power of the webpack, in a
> brochure?
> 
> Thank you very much.
> 

Article: 110237
Subject: Re: SPAM -- FPGA image processing camera
From: Mike Harrison <mike@whitewing.co.uk>
Date: Thu, 12 Oct 2006 18:20:45 GMT
Links: << >>  << T >>  << A >>

An FPGA based camera platform would seem to be entirely on-topic and of potential interest for this
NG.  I certainly don't have a problem with people posting info on _relevant_ new products.  

Article: 110238
Subject: Re: Functional Languages in Hardware
From: Mike Treseler <mike_treseler@comcast.net>
Date: Thu, 12 Oct 2006 11:23:02 -0700
Links: << >>  << T >>  << A >>
backhus wrote:

> You can use Matlab.
> but it is mostly limited to DSP Design and only available for XILINX
> FPGAs. Follow this link for more Information:
> http://www.xilinx.com/ise/optional_prod/system_generator.htm
> 
> Also there are HDCaml and Confluence. And it seems they are open source.
> http://www.confluent.org/


or MyHDL
http://myhdl.jandecaluwe.com

or single-process VHDL
http://home.comcast.net/~mike_treseler/


        -- Mike Treseler

Article: 110239
Subject: Re: Xilinx MicroBlaze 4.00.a source codes released by Xilinx !?
From: "Jon Beniston" <jon@beniston.com>
Date: 12 Oct 2006 11:23:16 -0700
Links: << >>  << T >>  << A >>

avionion@gmail.com wrote:
> the pcores flder is empty now :(
> can anyone email me the origianl zip file which has pdf and zip file in
> it?

Hmm. Would that be legal?

The files all have their copyright in tact, but by placing something on
the web, have you implicitly given someone the right to copy (if not to
distribute further copies, at least to retain the copy for yourself)?

Good luck to anyone trying to port it though ;-)

Cheers,
Jon


Article: 110240
Subject: Glitches in post-layout (PAR) simulation
From: "Manny" <mloulah@hotmail.com>
Date: 12 Oct 2006 11:51:09 -0700
Links: << >>  << T >>  << A >>
Hey all,

I've managed to synthesize a particular DSP core on Actel's fusion
FPGA. I'm using this as a benchmark to assess their suitability for
further integration. I'm a bit new when it comes to Actel. Anyway, it
seems that when running post-PAR simulation I end up having a periodic
pattern of 1ns wide glitches in my output signal every like 4 or
slightly less sampling periods. My design is fully synchronous. I have
no clue whatsoever about the source of the glitches. I even tried to
leave some temporal margin before doing the final output assignment
(for thigs to settle down) but it didn't work. Would really appreciate
it if anybody can give me an insight on possible problematic sources.
I'm yet to run my design in hardware as I'm still waiting for the kit
to arrive.

Thanks in advance guys.

Cheers,


Article: 110241
Subject: Re: SPAM -- FPGA image processing camera
From: fpga_toys@yahoo.com
Date: 12 Oct 2006 11:59:15 -0700
Links: << >>  << T >>  << A >>

JeffM wrote:
http://groups.google.com/group/sci.electronics/msg/13651a897337a7a9?q=Charters+misc.industry.electronics.marketplace+Discussions+Advertisement+only-advertise+sci.electronics.design-Electronic-circuit-design
>
> "How NOT to Advertise on Usenet" by Joel K. Furr
> http://66.102.9.104/search?q=cache:CMU1z-5ywJ4J:shopsite.com/help/4.1/sc/lte/usenet.html+rude.to.advertise.*.*+*-*-*-*-*-*-the-word-forsale-or-marketplace-in-their-names+preserve.*.culture.of.open.discussion+reads-an-advertisement+*.most.pervasive.form.*.*.*.*-*+How-*-to-Advertise-on-Usenet+biz+hated+rude+lose-*-account

That's all good and gret but we have a number of vendors in the C.A.F
forum regularly spamming by the comon definition, from Xilinx to
various vendors like John Adair's frequent posts for Enterpoint. The
cross posting is mostly likely the offense people care about.


Article: 110242
Subject: New Electronic Design Web site
From: Patrick Johnson <PJohnson_TechnoScope@nospam.com>
Date: Thu, 12 Oct 2006 15:08:33 -0400
Links: << >>  << T >>  << A >>
We're launching a new web site for electronics design:

http://www.ElectronicDesignNet.com

The site is just about to launch, and we would be interested in 
receiving any (constructive) suggestions or comments.

Thanks much,

The ElectronicDesignNet Team

Article: 110243
Subject: Re: Trying to get plb_temac working
From: "funkrhythm" <rimas@cnmat.berkeley.edu>
Date: 12 Oct 2006 12:13:39 -0700
Links: << >>  << T >>  << A >>
i am using EDK 8.1... it sounds like 7.1 didn't have the driver for the
plb_temac (which is in the BSP generated by 8.1 in
drivers/net/xilinx_gige)

-rimas

corley wrote:
> Is anyone using linux 2.4 with the plb_temac?  And what about EDK 7.1?
> I am having difficulty finding a linux driver for the plb_temac with
> 2.4.
>
> Rimas, when you say that you used the xilinx_gige driver, will that
> work for the plb_temac?  What about the xparameters*.h defines where
> they use _XTEMAC_ rather than _XGEMAC_?
>
> -cy
>
> funkrhythm wrote:
> > i used the branch of the ppc kernel mentioned here
> >
> > http://www.stanford.edu/~malechen/linux_on_fpga.htm
> >
> > and copied over the files from the BSP
> >
> > then what i did was to edit the Makefile in the drivers/net directory
> > and change the references from xilinx_enet to xilinx_gige, and select
> > the regular xilinx driver in the menuconfig
> >
> > -rimas
> >
> > p.s. if the PVR (processor version register) in your mini-module is
> > 0x20011430 make sure you apply patches to turn off caching or you will
> > have problems.  more info here:
> >
> > http://www.xilinx.com/xlnx/xil_ans_display.jsp?iCountryID=1&iLanguageID=1&getPagePath=20658&BV_SessionID=@@@@0781667753.1159381366@@@@&BV_EngineID=ccccaddimemlhmicefeceihdffhdfjf.0
> >
> > Benedikt Wildenhain wrote:
> > > Hello,
> > >
> > > On Wed, Sep 13, 2006 at 05:15:24PM -0700, funkrhythm wrote:
> > > > Benedikt Wildenhain wrote:
> > > > > Now I want to try sending some IP packets accross the wire, but both
> > > > > xilnet and lwip insist on using either opb_ethernet or -lite. Are there
> > > > > any adjusted versions for one of these?
> > > > don't know about that, i am running linux on the V4FX12 and the EDK
> > > > generates an ethernet driver (xilinx_gige) that works with the
> > > > PLB_TEMAC
> > > How did you compile a matching kernel? I tried to compile a 2.4 kernel
> > > (I tried several branches, but finally got farest with the branch from
> > > bee2.eecs.berkeley.edu as it already has integrated the xilinx_gige
> > > driver) with the BSP for Montavista Linux 3.1. As (menu|x)config doesn't
> > > offer my board I set CONFIG_MEMEC_2VPX=y, tried to compile it with
> > > support for uartlite (for the serial console) and xilinx_gige, but
> > > linking the kernel fails with
> > >


Article: 110244
Subject: Re: SPAM -- FPGA image processing camera
From: "JeffM" <jeffm_@email.com>
Date: 12 Oct 2006 12:33:08 -0700
Links: << >>  << T >>  << A >>
JeffM wrote:
::Posted from sci.electronics.design
>>http://groups.google.com/group/sci.electronics/msg/13651a897337a7a9?q=Charters+misc.industry.electronics.marketplace+Discussions+Advertisement+only-advertise+sci.electronics.design-Electronic-circuit-design
>>
>>"How NOT to Advertise on Usenet" by Joel K. Furr
>>http://66.102.9.104/search?q=cache:CMU1z-5ywJ4J:shopsite.com/help/4.1/sc/lte/usenet.html+rude.to.advertise.*.*+*-*-*-*-*-*-the-word-forsale-or-marketplace-in-their-names+preserve.*.culture.of.open.discussion+reads-an-advertisement+*.most.pervasive.form.*.*.*.*-*+How-*-to-Advertise-on-Usenet+biz+hated+rude+lose-*-account
>
fpga_toys@ yahoo.com wrote:
>That's all good and gret but we have a number of vendors in the C.A.F
>forum regularly spamming by the [common] definition, from Xilinx to
>various vendors like John Adair's frequent posts for Enterpoint.
>
Yeah.  The words "appropriate" and "acceptable" spring to mind.

>The cross posting is mostly likely the offense people care about.
>
You caught the core of my point; I hope the OP does likewise.
(As I specifically mentioned
that I was posting from sci.electronics.design,
I find it curious that you removed that group from your cross-posting.)


Article: 110245
Subject: Re: Glitches in post-layout (PAR) simulation
From: Mike Treseler <mike_treseler@comcast.net>
Date: Thu, 12 Oct 2006 13:15:28 -0700
Links: << >>  << T >>  << A >>
Manny wrote:
> Anyway, it
> seems that when running post-PAR simulation I end up having a periodic
> pattern of 1ns wide glitches in my output signal every like 4 or
> slightly less sampling periods. My design is fully synchronous. 

What happens if you slow down the clock?
Did static timing pass?

     -- Mike Treseler

From jon@ffconsultancy.com Thu Oct 12 13:41:00 2006
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From: Jon Harrop <jon@ffconsultancy.com>
Subject: Re: Functional Languages in Hardware
Newsgroups: comp.lang.functional,comp.arch.fpga
Followup-To: comp.lang.functional
Date: Thu, 12 Oct 2006 21:41:00 +0100
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shidan wrote:
> Are there any functional languages  that can be compiled to hardware at
> the same or greater level of abstraction than languages like Mitrion-C
> and Handel-C. Is it all research or is there anything that is practical?

A friend of mine did SAFL:

  http://citeseer.ist.psu.edu/599193.html

Another awesome project! :-)

I predict that such things will become more widespread in the future with
the advent of printed electronics, when spending millions on chip design is
no longer economically viable. That'll happen in the next decade or so...

-- 
Dr Jon D Harrop, Flying Frog Consultancy
Objective CAML for Scientists
http://www.ffconsultancy.com/products/ocaml_for_scientists

Article: 110246
Subject: Re: longest webcase record -- understandably so
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Fri, 13 Oct 2006 10:01:54 +1300
Links: << >>  << T >>  << A >>
colin wrote:

> Jim
> 
> I'm using a coolrunner II (which I said in my first email).
> I think they are the only CPLDs that support SSTL but if anyone knows
> of another familly then I'd love to take a look.
> 
> I'm fairly certain that the IO config isn't removed during boundary
> scan because I can read the functional state of pins using JTAG and so
> can chipscope for FPGAs.

Failing a definitive reply from Xilinx, you could always just test it ?
IP threshold is a fairly easy thing to check, especially if you have
all the read-pathway working.

-jg


Article: 110247
Subject: Re: VirTex 4 mini Module
From: "Anonymous" <someone@microsoft.com>
Date: Thu, 12 Oct 2006 21:21:24 GMT
Links: << >>  << T >>  << A >>
I've worked quite a bit with mine. The only real problem I had was that the
silicon rev on the fx12 is old enough that there is a problem with the cache
on the PPC. Lost about a week trying to get Linux to run because I didn't
realize there was a silicon bug.

I've done my own design now, based largely on the mini-module and with the
new silicon it's running linux 2.6 just fine at 100 Mhz.

Oh, also, the mini-module docs may drive you to using u-boot to bring up the
linux kernel. In my experience it's just as easy to make a .bin from your
kernel and jump to it directly from stage1_loader.

-Clark


"Eli Hughes" <emh203@psu.edu> wrote in message
news:eglsrb$ndu$1@f04n12.cac.psu.edu...
> Has anyone her had experience with this Board?  I really like these
> small modules.... Wish there were more out there.  I just want to here
> some feedback on the design or if you have had any software/hardware
> problems.
>
> -Eli



Article: 110248
Subject: Re: New Electronic Design Web site
From: "jacko" <jackokring@gmail.com>
Date: 12 Oct 2006 14:43:23 -0700
Links: << >>  << T >>  << A >>

Patrick Johnson wrote:
> We're launching a new web site for electronics design:
>
> http://www.ElectronicDesignNet.com
>
> The site is just about to launch, and we would be interested in
> receiving any (constructive) suggestions or comments.
>
> Thanks much,
>
> The ElectronicDesignNet Team

i would be interested in construction contractors, who build to design
and ship. didn't try the distributors list, as i have no built design
yet. does such a service exsist?

cheers


Article: 110249
Subject: Re: Glitches in post-layout (PAR) simulation
From: "Manny" <mloulah@hotmail.com>
Date: 12 Oct 2006 15:04:27 -0700
Links: << >>  << T >>  << A >>
Actually static timing did pass. As far as I could infer, these
glitches are due to long routing propagation delays and only consitute
negligible time (1ns) relative to the clock period. So they are pretty
much clock independent. In my testbench, I added an explicit intertial
delay (2ns) when assigning my output signal. Now everything is ok but I
still get warning messages in simulation. Was wondering whether it'll
have any noticeable impact when running in hardware?

Cheers,
-Manny

Mike Treseler wrote:
> Manny wrote:
> > Anyway, it
> > seems that when running post-PAR simulation I end up having a periodic
> > pattern of 1ns wide glitches in my output signal every like 4 or
> > slightly less sampling periods. My design is fully synchronous.
>
> What happens if you slow down the clock?
> Did static timing pass?
> 
>      -- Mike Treseler




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