Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi Peter Alfke, > Present generation: Spartan3 plus external PLL for higher freq. and > less jitter.( <100 ps) That's cheating! I've been pounding my brains all day how to get those jitter specs just by doing DDS. Hmmm... with the 10Gbps MGTs you should theoretically be able to get jitter down to less than ~2ps. The lower frequencies might pose a problem though. Interesting idea though. Best regards, BenArticle: 87926
This is with reference to page 33 of Xilinx's Spartan 3 Family: Functional Description. Paraphrasing from the documentaion: "To power the Dual-purpose config. pins apply 3.3v to VCCO_4 and VCCO_5. For the Dedicated Configuration pins apply 2.5V to the VCCAUX lines. In order to acheive 3.3V tolerance, the dedicated inputs requires series resistors that limit the incoming current to 10mA or less". OK. So on my board, I have hard-wired all the VCCO banks to 3.3V, VCCAUX to 2.5V and VCCINT to 1.2V. Am I am missing something here or why would use resistors on the Dedicated pins which are already operating at 2.5V while the dual-purpose pins are 3.3V. I know it something really small print I have forgotten to catch. I appriciate all your help. Thanks Yaju N ------- BYU ECEN Dept. Provo UtahArticle: 87927
On Wed, 3 Aug 2005 15:15:22 -0700, "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote: >> http://home.comcast.net/%7Emike_treseler/uart.vhd > >Wow, that's an interesting use of procedures to automatically >restructure a program. > >I brought the question of async vs. sync reset to the group awhile ago, >and someone told me (they should harp in here to get credit), that with >an async reset you may have metastable issues when your reset goes >inactive, which sort of defeats the purpose of having a reset. So this >sold me on sync resets, end of story. Actually this is a false compromise. There is a perfectly safe way of synchronizing the reset to your local cock(s) so that there is no chance of metastability regardless of the reset release time. This way you can continue to use async resets.Article: 87928
Ben, I started out with "all in the FPGA". Then I found out that the $5.- LCD diplay has its own built-in micro, and the 1 ppm oscillator costs more than the FPGA, as do case and power supply together. As does the pc-board with the regulators. That's were I became pragmatic and decided to design something useful first, FPGA-centric second. That's also the answer to Jim's suggestion. How many people need ultra-pure sinewaves at ultra-precise and ultra-low frequency? Most of our boxes get used as LVDS clock sources between 50 and 500 MHz, where they are an ideal fit. Peter AlfkeArticle: 87929
Allrite. I guess I just needed to use Google rather than google groups to answer this. I found the answer on Xilinx Answers Database. The resistor is used to drop voltages of the incoming signals to the dedicated pins (operating at 2.5V) which might come from a 3.3V source. The VCCO is kept at 3.3V so that the dual config pins can be operated at the corresponding voltage. For reference of others the 3.3V tolerant configuration schematics are at : http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&getPagePath=20477&BV_SessionID=@@@@1563068618.1123110651@@@@&BV_EngineID=ccchaddffjghjflcefeceihdffhdfkf.0 -Yaju Would it hurt Xilinx to update its data sheets with all the relevant information? Maybe they should just release the Spartan -3 Architecture :). If it is protected by patents, why would it hurt to make it open source. Ok, don' answer that. That was my meek attempt at sarcasm. Sorry.Article: 87930
Peter Alfke wrote: > Ben, I started out with "all in the FPGA". Then I found out that the > $5.- LCD diplay has its own built-in micro, and the 1 ppm oscillator > costs more than the FPGA, as do case and power supply together. As does > the pc-board with the regulators. > That's were I became pragmatic and decided to design something useful > first, FPGA-centric second. That's the best approach - a significant use of these is for education, and if you can "show what's possible" with external PLL, and what is also possible without it, that's worth quite a lot to designers. > That's also the answer to Jim's suggestion. > How many people need ultra-pure sinewaves at ultra-precise and > ultra-low frequency? That would depend on how seriously you wanted to court Audio designers. If they are not on your radar, then there is probably still an educational element of "showing what's possible" again, and having a crack at seeing what noise/distortion floor you can achieve - again with some off-fpga help, like an analog switch for the Switching DAC integrator. -JGArticle: 87931
Hi Cyd, I confess I have never used a V2 Pro but looking in the datasheet the DCM supports the frequency synthesizer which can output a multiplied clock on CLKFX. If you are not using the DLL then the minimum input clock is 1MHz, not 24MHz. (the 24MHz spec applies when using the DLL). Perhaps also read the Xilinx application note XAPP462. I found it easy to read and it answered all my questions. XAPP462 is for the spartan 3 DCM though...probably there is an equivalent app note for the V2 Pro DCM.... Regards Andrew cyd wrote: > I am looking for some help in regards to a 20 MHz modulation clock that > needs to set the timing in the Virtex_II_Pro. I was investigating > running the modulation clock into a DCM; However, the minimum input > frecquency for CLKIN is 24MHz. The 20 MHz modulation clock needs to > establish the timing in the FPGA for synchronizing the 80MHz ADC and > for digital mixing of the modulation frequency. If I can not use a DCM, > how do I create the synchronous timing for my subsystems 80MHz and > digital mixing?Article: 87932
Hi, I am currently using the evaluation open-core FIR compiler and NCO compiler in the design and when I use these I am not able to perform incremental synthesis. Does anyone know if you can perform incremental synthesis with these cores once the cores are licensed? as synthesis steps are taking upwards of 20-30 minutes at the moment and it is becoming quite painful not having incremental systhesis. Regards, Paul SolomonArticle: 87933
Hello Everyone I am a final year student at Manukau Institute of Technology.I am doing my honours research project on Evolvable Harwdware. Xilinx has developed GeneticFPGA toolkit. On one of the FPGA newsgroups I read that it is free for download once you send a request email to the address JBits@xilinx.com. I couldn't find it on the Xilinx website.Also I did send an email on this jbits address a few times but did not get any reply. I would be really grateful if you could send me the link to download GeneticFPGA toolkit. Thank you Ankit ParikhArticle: 87934
>The EARLY Pentiums were architected by a single person. >Need I say more ?:-) > Jim Thompson Well, a name would be nice. The story I hear is that Frederico Faggin was the last guy to single-handedly design a uP (Z-80).Article: 87935
"Nenad" <n_uzunovic@yahoo.com> wrote in message news:1123093399.809751.93300@g43g2000cwa.googlegroups.com... > hi there, > > i am new in these thing as well, so i might not be correct. > > i would recomend to try to set the global clock to jtag clk. > > right click on "Generate Programming File" -> properties -> startup > options > and then set FPGA startup clock to JTAG > > cheers That got rid of the clock warning message, but it has now gone up to 262 differences on verify. The (very simple) design still seems to work though. Perhaps I'm doing something else wrong. I don't need to set any jumpers or switches on the ML401 for direct JTAG config, do I? ThanksArticle: 87936
<apsolar@rediffmail.com> schrieb im Newsbeitrag news:1123124714.708645.319430@g49g2000cwa.googlegroups.com... > Hello Everyone > I am a final year student at Manukau Institute of Technology.I am doing > my honours research project on Evolvable Harwdware. Xilinx has > developed GeneticFPGA toolkit. On one of the FPGA newsgroups I read > that it is free for download once you send a request email to the > address JBits@xilinx.com. I couldn't find it on the Xilinx website.Also > I did send an email on this jbits address a few times but did not get > any reply. > I would be really grateful if you could send me the link to download > GeneticFPGA toolkit. > Thank you > Ankit Parikh > NOWHERE. if you search with Google you only find references to year 1999 ! so its possible as dead as JBits and no chanc to get hold on it. AnttiArticle: 87937
Hi, I was wanting to know if there was a way to auto-generate a mif or hexout file in quartus (or in general verilog) based on the set parameters in a verilog file? The application is for a NCO function that used a memory lookup (for sin table) approach rather that cordic. The sin table can be auto generated by a perl script that I can write in which I can manually set the memory depth and amplitude resolution (which are parameters of the NCO) however I would like the module to allow the end user to set an arbitrary bit width and phase angle width and at synthesis time have a script or some other clever code generate the required memory file for me. If anyone has any ideas how to achieve this kind of trickery I would apreciate the advise. Regards Paul SolomonArticle: 87938
Symon wrote: > "Marc Randolph" <mrand@my-deja.com> wrote in message > news:1123071787.753397.21140@z14g2000cwz.googlegroups.com... > > > > In your other message, you mentioned that the nets "are routed as very > > loosely coupled traces where each trace has a 50 ohm characteristic > > impedance". I'd think you'd want a fairly tightly coupled 100 ohm > > differential pair. How loosely are they coupled? Are the _p and _n > > legs close to the same length? > > > Hi Marc, > The coupling between them doesn't matter if the individual lines are 50 ohms > and the propagation time. How can the electricity know the difference > between that and a 100 ohm diff pair, or indeed, all the hybrid combinations > in between? Howdy Symon, The main point of tigher coupling is so that anything that affects one leg will also affect the other leg - allowing it to be cancelled out by the differential receiver. I don't know exactly what his definite of loosely coupled is, but if it is "loose" enough that an aggressor signal could affect one leg of the pair much more than the other, it throws out the main benefit of using differential pairs in the first place. > JF, > You should check the datasheet or call the manufacturer to make sure you > don't need the put any DC bias on the optics' rx CML port. Normally it's > something like Vicm, input common mode voltage. If he's using the more common internally AC-coupled transcievers (which I got the impression from the first post that he is), any external DC-biasing is not going to have an affect on his signals. They do make DC-coupled transceivers though, so it is worth checking to make sure that JF didn't end up with some. I realize the chances of it are very low, but I assume JF has ruled out the possibility this is just a bad transciever. Regards, MarcArticle: 87939
Ankit, click on http://en.wikipedia.org/wiki/Evolvable_hardware and google Adrian Thompson. The Xilinx devices he used, the 6200 family, is dead. No hardware, no software. The family dies for lack of commercial interest. My feeling is that some smart academics have explored this field already, and I have seen no progress over the past 5 years. I would pick another subject... Peter AlfkeArticle: 87940
"Paul Solomon" <psolomon@tpg.com.au> wrote in message news:42f1abf0$1@dnews.tpgi.com.au... > Hi, > > I was wanting to know if there was a way to auto-generate a mif or hexout > file in quartus (or in general verilog) based on the set parameters in a > verilog file? > > The application is for a NCO function that used a memory lookup (for sin > table) approach rather that cordic. The sin table can be auto generated by > a perl script that I can write in which I can manually set the memory > depth and amplitude resolution (which are parameters of the NCO) however I > would like the module to allow the end user to set an arbitrary bit width > and phase angle width and at synthesis time have a script or some other > clever code generate the required memory file for me. > > If anyone has any ideas how to achieve this kind of trickery I would > apreciate the advise. > > Regards > > Paul Solomon > Or at the very least, if there was a way to select a memory file which is set in a defparam blah.init_file = "sin_lut_32_16.mif"; further up in the file there is a parameter A = 32, B = 16; etc so it would be nice to be able to do something like... defparam blah.init_file = "sin_lut_$(PARAMETER_A)_$(PARAMETER_B).mif"; is there any form of string substitution such as above available in verilog? Regards, Paul SolomonArticle: 87941
>> The designer software is available as silver edition for free. This >> edition is OK for smaller devices. >Well, how small? I'm using the eX64 (64 dedicated flip-flops, 3000 system >gates) Well it is now the Gold edition of Libero/Designer that is free, and that will cope with all devices upto 300,000 gates, and a couple of the larger APA3 devices. So it would be worth downloading and trying to import your design. If your design is purely VHDL then it is fairly easy just to import the .vhd files and go from there. If there are any ACTGen macros, these are .gen files, then you can also import those and then generate the .vhd files for them, or find out what there are and create your own VHDL files. If there are any ViewDraw schematics in the design, these are .1 files, then it is a little complicated, but can be done.Article: 87942
Fred Marshall wrote: > <jjlindula@hotmail.com> wrote in message > news:1123083687.394543.131660@g49g2000cwa.googlegroups.com... > > Hello, to be brief SE involves > controlling your design processes - isn't there a VP Engineering to set > policy? Isn't there a way to communicate what's working and not working? > It must be a really overdone project to need a *person* dedicated to this. In R&D, there is no such thing as "policy" or "corporal memory". I have never met a "scientist" or "researcher" who did acknowledge that skill and competence were personal attributes, that each person have to make an effort to gain for themselves or communicate to others. "What do you mean I can do better? I am a professor at [insert your favourite university or R&D organization here], for crying out loud!" > reproducability - I think you mean produceability. Not necessarily. Some attention to reproduceable results would keep certain not entirely all that good techniques from enetering the scene. Remember, R&D is all about "publish or perish." Making a second check of those "brilliant" results might lose a much cited paper. "Never measure twice." > Just part of good > engineering with adequate discussion with the manufacturing folks. Not a > special discipline / position. The common R&D argument is that "we do this only once, there is no need to build a system around this activity." > integration planning - the system guru takes the lead and, unless the guru > does it all alone (which is common) then it's a group activity. Again, since an R&D activity usually is done only once, or a couple of times at most, no one see the need for systematic planning. These are the factors that in my experience separate R/D from engineering. In R&D, stuff like the above are generally considered "waste of time and talent". > To make a point: > It is told that a Japanese company licensed the production of an American > engine. They took the original drawings and began production. But they > couldn't build engines with those drawings! Why? Because at that time, the > Japanese built all the parts to exceptional tolerances so there could be > virtually 100% interchangeability. And, because at that time, the Americans > had built the parts to looser tolerances and were willing to do some mixing > and matching of parts, they didn't recognize that the dimensions in the > drawings were "wrong" - that is, a working engine could not be assembled out > of a set of parts that were perfect according to the drawings. I don't know > if the story is true but it's sure interesting..... Heh, that's my average experience when I try to make some algorithm or technique work, be it from an academic paper or an in-house technical report: The documentation doesn't work. Either there are typos, the key tricks are left out or "documentation" is taken to mean "a short general description of a concept". I don't think I have ever implemented a technique based on a single document "and the references therein". I always had to go to other literature, and more often than not, do the complete derivations myself to make sure I got it right. RuneArticle: 87943
"Marc Randolph" <mrand@my-deja.com> writes: > Symon wrote: > > "Marc Randolph" <mrand@my-deja.com> wrote in message > > news:1123071787.753397.21140@z14g2000cwz.googlegroups.com... > > > > > > In your other message, you mentioned that the nets "are routed as very > > > loosely coupled traces where each trace has a 50 ohm characteristic > > > impedance". I'd think you'd want a fairly tightly coupled 100 ohm > > > differential pair. How loosely are they coupled? Are the _p and _n > > > legs close to the same length? > > > > > Hi Marc, > > The coupling between them doesn't matter if the individual lines are 50 ohms > > and the propagation time. How can the electricity know the difference > > between that and a 100 ohm diff pair, or indeed, all the hybrid combinations > > in between? > > Howdy Symon, > > The main point of tigher coupling is so that anything that affects one > leg will also affect the other leg - allowing it to be cancelled out by > the differential receiver. I don't know exactly what his definite of > loosely coupled is, but if it is "loose" enough that an aggressor > signal could affect one leg of the pair much more than the other, it > throws out the main benefit of using differential pairs in the first > place. > But most of the aggressors are likely to be other PCB traces, and they are *not* going to couple symmetrically onto the pair. My understanding is that you just can't couple PCB traces that well. The main benefit of using differential pairs for signals is off-board using twisted pair cabling. So long as your PCB traces match in delay (not length), you've got what you can out of them. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 87944
ERROR:Xst: 1706 - Node <_n0925<19>>, from parent <cs_control_logic>, has no source for port <_n1921<19>> Dear All, When synthesising my VHDL code in the Xilinx ISE tool I get this error (see above). I am clueless to what it means or what it is referring to. Anyone got any ideas? Kind Regards SimonArticle: 87945
>>I brought the question of async vs. sync reset to the group awhile ago, >>and someone told me (they should harp in here to get credit), that with >>an async reset you may have metastable issues when your reset goes >>inactive, which sort of defeats the purpose of having a reset. So this >>sold me on sync resets, end of story. > > Actually this is a false compromise. There is a perfectly safe way of > synchronizing the reset to your local cock(s) so that there is no > chance of metastability regardless of the reset release time. This way > you can continue to use async resets. If you generate a synchronous reset signal then connect that to the asynch reset input of the registers in your design, can you be sure that the tools include this path in the timing analysis? It be a reasonable assumption of those designing the timing analysis tools that anything going to an asynchronous input doesn't need to be included. Could you be caught out doing this? BTW, I'm playing devil's advocate here as I've been using this technique myself for a while, I'm just checking it's as bulletproof as I assumed it was. Nial.Article: 87946
On Thu, 4 Aug 2005 11:57:51 +0100, "Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote: >> synchronizing the reset to your local cock(s) nooooo, you really don't want to do that at all. Jolly painful. >If you generate a synchronous reset signal then connect that to the asynch >reset input of the registers in your design, can you be sure that the tools >include this path in the timing analysis? > >It be a reasonable assumption of those designing the timing analysis tools >that anything going to an asynchronous input doesn't need to be included. > >Could you be caught out doing this? > >BTW, I'm playing devil's advocate here as I've been using this technique myself >for a while, I'm just checking it's as bulletproof as I assumed it was. See the recent thread "Bulletproofing CPLD Design" on comp.lang.vhdl for further suggestions from me and others on this issue. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 87947
"Jim Thompson" <thegreatone@example.com> wrote in message news:tqv1f19en0pj7rclndiq6r8uvn0mbg3uho@4ax.com... > > > The EARLY Pentiums were architected by a single person. Need I say > more ?:-) > > ...Jim Thompson Is this the one that couldn't divide very well. I.e., had the floating point bug? ClayArticle: 87948
Hi Peter I am half way through this topic.So I have to finish it up. Have you read Adrian Thompson's PHD thesis.I guess it would contain some valuable information.Do you know where I could get it.Or do you have any other suggestions for me. Thanks Ankit Peter Alfke wrote: > Ankit, > click on > http://en.wikipedia.org/wiki/Evolvable_hardware > and google Adrian Thompson. > The Xilinx devices he used, the 6200 family, is dead. No hardware, no > software. > The family dies for lack of commercial interest. > My feeling is that some smart academics have explored this field > already, and I have seen no progress over the past 5 years. > I would pick another subject... > Peter AlfkeArticle: 87949
On Thu, 4 Aug 2005 15:47:16 +1000, "Paul Solomon"
<psolomon@tpg.com.au> wrote:
>Hi,
>
>I was wanting to know if there was a way to auto-generate a mif or hexout
>file in quartus (or in general verilog) based on the set parameters in a
>verilog file?
>
>The application is for a NCO function that used a memory lookup (for sin
>table) approach rather that cordic. The sin table can be auto generated by a
>perl script that I can write in which I can manually set the memory depth
>and amplitude resolution (which are parameters of the NCO) however I would
>like the module to allow the end user to set an arbitrary bit width and
>phase angle width and at synthesis time have a script or some other clever
>code generate the required memory file for me.
>
>If anyone has any ideas how to achieve this kind of trickery I would
>apreciate the advise.
Here's just one possible idea - not tested, but I think it will work.
Here's your parameterisable module:
module Wotsit(a,d);
parameter nA = 8; // number of address bits
parameter nD = 10; // number of data bits
input [nA-1:0] a;
output [nD-1:0] d;
always @a
d = <some function of a, will synthesise to ROM>;
`ifndef SYNTHESIS
// this line is executed for simulation only
initial $display("Wotsit_instance %m: nA=%0d, nD=%0d", nA, nD);
`endif
endmodule
Now, when you simulate, you get a line in the transcript that
has all the relevant information in it. Get a Perl or Tcl script
to process the transcript to extract those lines and munge them
to construct the appropriate memory file, with an appropriate
file name.
There's an urgent need for a little Perl or Tcl utility that
will convert among all the various memory-image formats that
we EDA folk need - Verilog $readmemb, Xilinx and Altera
memory formats, Intel hex and so on. Perhaps someone has
already done it?
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z