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Sorry Ray , I now understand what you meant at the beginning, its my fault I've got mixed up with my notation ( and was looking at a different aspect) . The counter relationship is between the nco_nominal count (theoretical) calculated from the delta phase and the measured count (using the external stable reference 10^-15 precision and counting rising edges on 125MHz reference clock for nco). The external clock uses 10MHz and I've purposely change its timebase to 1.6ms. My intention is to get the ratio between nominal/measured and adjust the delta phase accordantly. Now as Ulrich mentioned I I'm using integer counters and I'll need to continue evaluating the resolutions ( I will post back with results ) I did further research , this is what I've came up with ( with help from my senior engineer) The following looks too simple to be true. However, it uses constant division whereas we need variable division. http://www.codecomments.com/archive378-2005-4-441345.html Who said arithmetic was difficut in an FPGA ;-) It's just an example. It can be further optimized. It's a parallel full speed solution... -- Divide a 24 bits unsigned by 1.122 -- Author : Bert Cuzeau -- not overly optimized (yet under 150 LCs of plain logic) LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; -- --------------------------------------- Entity DIVBYR is -- Divide a 24 bits by 1.122 -- --------------------------------------- Port ( Clk : In std_logic; -- Main System Clock Rst : In std_logic; -- Asynchronous reset, active high D : in unsigned (23 downto 0); -- use std_logic_vector ! Q : out unsigned (23 downto 0) -- use std_logic_vector ! ); -- end; -- --------------------------------------- Architecture RTL of DIVBYR is -- --------------------------------------- begin process (Rst,Clk) begin if Rst='1' then Q <= (others=>'0'); elsif rising_edge (Clk) then Q <= to_unsigned( (to_integer(D) * 7301 / 8192 ),24); end if; end process; end RTL; The following is an algorithm for division. http://klabs.org/DEI/Arithmetic/division/leon_division/leon_division.htm http://www.inria.fr/rrrt/rr-4494.html has a paper giving some insight into division at the end of the paper (attached RR-4494.pdf). Also JustJohn comments , sorry I meant the 1.6ms was the basetime to count the measured local oscillator , actual drift ( from what I've calculated will need to be adjusted a least every 8ms , that's when the local clock becomes one cycle out of phase. Ray Andraka wrote: > luca_grossi@hotmail.com wrote: > > > Really appreciate everyone's input , the specifies are a little > > different to my first understand of the problem but never the less > > useful information ( I'm just an undergrad , still learning the > > ropes) . Ben with your response , I'm unable to make count1 2^N > > because its actually the measured result that will vary depending on > > the drift of the oscillator, if the formula was the other way around it > > would make the problem much easier , using your solution. > > Peter , I can't use the external clock reference because the nco > > utilizes a rocketio mgt component and the specifics require the local > > 125MHz clock to drive it ,, only with hardware changes can I change > > this " and for the time been isn't really the most viable option , > > hence implementing compensator circuit. > > Ray , similar to Bens answer , the problem is , the denominator is > > measured , thus varying > > > > So delta2 = (nominal/ measured) * delta1 > > > > One solution is to do a lookup table and also utilize linear > > interpolation between points. Count of NCO (which is measured count of > > local oscillator) corresponds to a particular delta correction phase. > > > > Please feel free to ask more question if anything is un clear.. Also > > you future references are there custom cores available for divisions? > > > > Perhaps I am missing a few things here. You have both clocks, no? If > you do, you don't need the frequency measurement from somewhere else, > you use the clocks themselves and the counter arrangement I described. > > A more conventional approach would be to not worry about the specific > delta, but instead nudge it up or down with feedback derived from the > frequency or phase error at the NCO output (mix the NCO with the signal > and determine the phase/frequency offset from the resulting beat). > Properly done, it will self adjust without ever having to compute the > delta value. > > The sample rate through your NCO is fixed by the clock (I think you said > it is a 125 MHz clock). The signal's center frequency is determined by > the transmitter, but you don't have access to exact transmitter > frequency (besides, it will drift). As a result, you need to vary the > phase increment for the NCO in order to match the transmitter's carrier.Article: 110701
Mike Treseler wrote: > Sorry I rained on your parade. > Trial and error synthesis using a logic analyzer works also. > I guess I spent too many years hooking up those > little clip leads and waiting for a trigger. Not only are HP16xxx logic analyzers cheap on eBay these days, but making one out of an FPGA is yet another fun project.Article: 110702
visit this page http://digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Programmable&Cat=Programmable%20Logic u will find very good $99 boards including spartan 3 starter kit. On Oct 18, 9:33 pm, samiam <samiamSPAMT...@spamalert.com> wrote: > Figured this was the place to ask (comp.arch.embedded or comp.arch.fpga) > > Whats the cheapest board to study VHDL on? > > Ideally Id like an FPGA based board with a few inputs (dip > switches,toggles?), some outputs (parallel or serial connector, some > leds) < $100 > > I am looking on ebay now, and I see one or two boards well above $100. > Any suggestions? > > Thanks in advanceArticle: 110703
Thanks Mr. Coesel, Mr Adair, Mr. Amontec, Mr. Basili and Mr. Schreib for taking time and responding to my quiry. I am pleasantly surprised that the spirit of parting knowledge is still alive and healthy. I went back and I constrained the clock to 60Mhz. Used Chipscope, Mapped for Speed rather than area, constrained DCM and finally it turns out that the tool as of now is not supporting what I am trying to do and it will be fixed in a service pack. I sincerely appreciate your inputs. Roger. jtw wrote: > Have you properly specified the input/output timing constraints? Most of > the effort is spent defining internal timing constraints, but the I/O can be > messed up--even if it meet the specifications you've given it, if they > aren't correct! (The rate may be correct, but the offset may not.) > > What is the clock phase uncertainty for the incoming signals? What is the > setup/hold time on the device the FPGA sends data to? > > Xilinx FPGAs (4k, V2, probably many others) let you adjust the delay > (coarsely) on your inputs; you get to select drive strength and fast/slow on > the outputs. Are the settings appropriate for your device's environment? > > Also, there are the physical board issues: how far from nominal are the > voltages? How noise are the voltage and ground planes? Even at 50 MHz, you > could create quite a bit of simultaneous switching noise if the chip isn't > bypassed correctly, or .... > > Also, "doesn't work" can mean many things; you may want to insert some test > circuity (Chipscope, or something similar, perhaps) to characterize the > failure. If you identify "where" the failure occurs, "why" might not be far > behind. And then it is often (but not always) just a quick jog to "fixed." > > Jason > > "Nico Coesel" <nico@puntnl.niks> wrote in message > news:4537c0f0.1286740364@news.kpnplanet.nl... > > "Roger" <hpsham@gmail.com> wrote: > > > >>A design is built to work at 50MHz, but the deisgn when tested works > >>only at 48MHz. What > >>should we do to make the design meet specific timing constraint .i.e. > >>to make the design to make it work at 50 MHz? > >>Thanks > > > > Are you sure all signals are covered by timing constraints? Don't > > forget connections which connect IO cells to internal flipflops. These > > should be constrained as well. > > > > -- > > Reply to nico@nctdevpuntnl (punt=.) > > Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 110704
Hi Tommy Thanks for the info. Yes I found your posts about 2mins after I sent one out (after searching and finding nothing current). That's the problem with info on the web... it's often out of date and finding the right stuff can be needle in haystack. I think I will go for a CoreDuo with 4MB. Marc > Marc, why didn't you try to google for the answer? This question is > asked every other week on comp.arch.fpga. I only reply because I have > some new numbers. > > marc_ely wrote: > > Has anyone recently done any benchmarking of Windows PC's for Xilinx > > ISE Compiles? > > No, but I have for Quartus which is very similar. > > > Is ISE multithreaded? > > No and not for a while to come. > > > Can it use multiple processors (or cores)? > > Nope. > > > Do big CPU caches help? > > Oh yeah, but once you have that, core frequency is all that matters. > > I recently went from an Athlon 64 2.0 GHz/1 MiB L2$ to a E6600 Core 2 > Duo 2.4 GHz/4 MiB L2$. For my benchmark, the time for Synth/P&R went > from 12m34/33m40 to ~6m/~15m, thus more then double the P&R > performance. When overclocked to 3.3 GHz the result scaled to > 5m54/11m12, thus 3X the P&R performance. Other experiments confirm that > it scales linearly with frequency (assuming memory scales equally). > > I have expensive memory, but from my experiments the benchmark results > showed very little sensitivity to memory bandwidth and latency. > > The 4 MiB Core 2 Duo is a very fast chip for FPGA work, probably the > fastest x86 available, but it's still not fast enough to reduce the > compilation times to an acceptable level. > > TommyArticle: 110705
Hi Luca,
<luca_grossi@hotmail.com> wrote in message
news:1161325258.276230.112390@m7g2000cwm.googlegroups.com...
> The counter relationship is between the nco_nominal
> count (theoretical) calculated from the delta phase and the measured
> count (using the external stable reference 10^-15 precision and
> counting rising edges on 125MHz reference clock for nco). The external
> clock uses 10MHz and I've purposely change its timebase to 1.6ms. My
> intention is to get the ratio between nominal/measured and adjust the
> delta phase accordantly.
I think I must still be misunderstanding something fundamental. Let me see
if I've got this straight.
You have two clocks but you don't know their exact frequencies. You have the
ability to count rising edges of these clocks, presumably by sampling them
using a third, higher-speed clock and detecting 0-1 transitions. Every time
you see a transition on clock A, you increment counter A. Every time you see
a transition on clock B, you increment counter B. The ratio A/B is the
number you're looking for.
So, at some point in time you have to start your counters at 0, right? And
at some later point in time you have to stop both the counters and calculate
the ratio, right?
So, why not monitor counter B and when it reaches some predetermined
convenient value, e.g. 65536, stop counting and call that your sample
period?
I don't see how it matters which clock is supposed to be the "nominal" and
which is the "measured" clock, if you're really measuring both of them. That
is, instead of asking the question "how many rising edges of clock B do I
see in this fixed time period", you should ask "how long does it take for me
to see 65536 rising edges of clock B"?
Definitely must be missing something. :)
-Ben-
Article: 110706Hi! The datasheet of the Xilinx PCIe endpoint core states that an 8-lane configuration requires an FX60. The size of the core does not justify this. The 4-lane configuration supports FX20. What is the reason for this requirment? I suspect that all lanes must be on the same side of the FPGA or a similar constraint. But the datasheet does not state anything like that. Would be good to know that for doing a board layout.... Kolja SulimmaArticle: 110707
> > Just so you know. You ought to not activate the EDK until you have > learned VHDL and are ready to start building systems for only the next > 90 days. I have pragmatic reasons for wanting to go open source in my > designs (e.g. opencores.org) so the wasted activation was no great loss > for me. > > -- > David M. Palmer dmpalmer@email.com (formerly @clark.net, @ematic.com) yes, opensource is always better. (i dont know why xilinx does not give out EDK for free, so that lot of student will learn it in the universities and apply the knowledge at workplaces, thereby increasing xilinx's profits). but still there are no opensource intergrated development solutions as EDK and platform studio provides. i checked impulseC and it seems great, but costs around $5000. and there is an opensource lib collection called "SystemC". im not qite sure its role yet.Article: 110708
Ray Andraka wrote: > Zorjak wrote: > > > Hi. > > I am trying to write generic VHDL code for FIR filter. generic > > parametars should be word_length, filter_order. Can anybody help me > > how to input filter coeficients. I tought something like, read > > coeficitients from file and write it in some LUT table. Could it be > > done (or something similar)? > > > > Thanks for help > > > > If it is synthesizable code, it can't go and read files. What you can > do though is have a helper function that converts your coefficient file > into a VHDL package containing the coefficient constants. Write that > package to a file, and then include that file with the rest of the > design when you compile the design. The helper function can be > non-synthesizable VHDL, C, Matlab or any other programming language you > feel like using. Alternatively, you can cut and paste your coefficients > into a VHDL package or directly into a constant array in your code. > > You can also pass the coefficients into the entity through a generic by > defining an integer_array type in a top level package, referring to that > package in the library declarations, and then putting the int_array in > the generics like this: > > component matrix > generic( > coefs: int_array:= ( > -62465, -8923, 24026, 39814, 41873, 33635, 18534, > 0,-18534,-33636,-41873,-39813,-24025, 8925, 62468, > 48188, 27536, 10061)); > port( > clk : in std_logic; > > Leaving the integer array unconstrained allows you to put in an > arbitrary number of coefficients (must be more than 1). Thanks for your answer Ray I am using Altera Quartus|| software and I've seen there thet some *.mif files are using for ram initialization so I thought could I do something similar with my FIR filter. Can you help me with that helper function if it isnt to much that I am asking. I am VHDL beginer and I am not very familiar with it so any lkind of help would used me. If is to much that I asking, sory. Thanks againArticle: 110709
the "E" in DSP48E stands for enhanced, at allows way more fun with the DSP48 block like today I had to stay home (catched cold) and did think lets try out the SIMD mode and the result is done: a 4 Channel 12 Bit PWM unit that uses 0 (Zero) Slices 0 (Zero) LUTs 0 (Zero) FF's sure it uses 1 DSP48E it was pretty fun excercise - doing 3 channel PWM with DSP48E would be piece of cake, but getting 4 channels working was a bit more brainwork. ;) Antti http://groups.google.com/group/virtex5Article: 110710
I had the same problem... what FPGA are you using? I am using the spartan 3e starter kit. I spent some time looking around the web and I found a site which explains how to append the "root=" command properly; here is a link: http://www.ucdot.org/article.pl?sid=03/01/11/1049210&mode=thread However, even though I followed the instructions, I still got a new error: ********* location VFS test name = </dev/root> Micr VFS fs_name = <ext2>ash probe(0x21000000 VFS fs_name = <romfs> 21000000 VFS root name <1f:01> ********* arena open of 1 failed!evice at location zero VFS: tried fs_name = <ext2> err = -19 Hope this helps; if you make any progress please let me know. Thanks, Scott Nortman David Ashley wrote: > Francesco wrote: > > Hi I'm trying to porting uclinux using microblaze 4.0. > > When I try to run the OS I've got the following error message. > > > > Kernel panic: VFS: Unable to mount root fs on 1f:00 > > > > Does anybody had a similar problem? > > > > Thanks in advance, > > Francesco > > > > Linux is up but it can't mount the root > partition. What is your kernel command line? > What is the "root=xxx" specifically. That device > number 1f:00 seems screwy. It's not listed in > include/linux/major.h. > > -Dave > > -- > David Ashley http://www.xdr.com/dash > Embedded linux, device drivers, system architectureArticle: 110711
Anyone happen to know if there are any problems with sdf simulation for Spartan-3? This works a lot of the time for me, but I get occasional setup failures, with messages like # ** Warning: /X_SFF SETUP Low VIOLATION ON I WITH RESPECT TO CLK; Generally, everything else fails soon after a setup violation. The sdf file doesn't contain any triplets, despite various docs saying that it does. It contains single delay values, which are presumably the maximums. That means that I can't try sdftyp or sdfmax options in the simulator. What I'm doing is: - STA passes. I'm driving the device inputs with lots of slack over the worst-case numbers reported by trce - I'm running netgen with default options on the post-PAR NCD - sdf options to ModelSim are: # vsim +no_path_edge +ntc_warn +splitsuh +pulse_int_e/0 +pulse_int_r/0 +multisource_int_delays +transport_int_delays +nowarnTFMPC +pulse_e/0 +pulse_r/0 +sdf_nocheck_celltype +sdf_verbose +transport_path_delays -quiet -sdfmax /TESTBENCH/DUT=dev_timing.sdf -t ps ...etc. - XC3S1000-FG676-4, Webpack 8.2i, no service packs Thanks - EvanArticle: 110712
On Thu, 19 Oct 2006 10:46:24 +0200, Zara <me_zara@dea.spamcon.org> wrote: >On Thu, 19 Oct 2006 10:33:07 +0200, Zara <me_zara@dea.spamcon.org> >wrote: > >>On Thu, 19 Oct 2006 09:50:03 +0200, Zara <me_zara@dea.spamcon.org> >>wrote: >> >>>This is not strictly a call for help, it is more of a warning to >>>everyone. >><...> >> Continuing with the tale (please forgive me if I strip all teh contents from previous messages): Now I do have a double Xilinx installation (8.1 and 8.2), with 8.1 working perfectly. If I communicate with 8.2 XMD to a core created with 8.2, everything is fine, so there seesm to be no problem with XMD itself (al leats with ParallelCable III, tests with Platfrom USB are delyed until I stabilize the design). When I upgrade the design (a copy of it, of course) to 8.2, the following modules are automatically upgraded: OPB, OPB_MDM, LMB, BRAM_BLOCK, DCM, OPB_INTC. The following are not upgraded: MICROBLAZE, LMB_BRAM_IF_CNTRL And the design stops working, with MDM blocking before ending the inital protocol with the opb_mdm. Only once I could connect to it, and there I saw that some randomly distributed bits of an external ram failed to obey orders. As the connection to RAM is doen through my own designed IP, I suppose there has been some change with OPB bus that forces tihis failure. In fact, it seems that something may be running a little slower and timing is failing, without warning in spite of my putting constraints over all extern clock feedbacks. Next chapter: Unupgrading the upgraded modules, will it be possible? Stay connected!Article: 110713
I'm implementing some Image Processing algorithms in VHDL, I'm testing these algorithms on the FPGA Spartan IIE xc2s200E. Is there any way to use the JTAG pins of the xc2s200E for user I/O? I want to download data from the PC, via a Parallel Port to JTAG Port on the xc2s200E.Article: 110714
Adriano wrote: > I'm implementing some Image Processing algorithms in VHDL, I'm testing > these algorithms > on the FPGA Spartan IIE xc2s200E. Is there any way to use the JTAG pins > > of the xc2s200E for user I/O? I want to download data from the PC, via > a Parallel Port > to JTAG Port on the xc2s200E. not directly but you can use the BSCA primitive to implement some custom gateway that passes the data to your ip core AnttiArticle: 110715
Hi, I have a design that connects a Spartan 3e running a Microblaze soft-core with an SPI unit attached to the OPB bus to a 16 Bit DAC unit (DAC8534). The data I send to the DAC unit has the bit order reversed. The SPI_OPB pheripheral has no way of reversing the shift out order from what I can see. Below is a program snippet of sending data to the dac unit: ------------------------------------------------------------------------------------------------------------------------- // Select the DAC Unit XSpi_mSetSlaveSelectReg(XPAR_SPI_DAC_BASEADDR, SPI_DAC_SELECT); // Set the message data. send_data[0]=0x20; // Control Register send_data[1]=0x0F; // Upper 8 bit value send_data[2]=0x0F; // Lower 8 bit value // Send the message data. spi_transfer(send_data, 3); // Deselect the DAC Unit XSpi_mSetSlaveSelectReg(XPAR_SPI_DAC_BASEADDR, SPI_NONE_SELECT); ------------------------------------------------------------------------------------------------------------------------- The data sent to the dac unit appears as 0xF0F0 instead of 0x0F0F disregarding the control byte. Does anyone know of how I can reverse the bit order at a minimal overhead cost. Can you give an example of bit order reversing? Thanks, Aaron CurtinArticle: 110716
Sorry, but I'm a very beginner of the FPGA technologies. What does "the BSCA primitive" mean exactly? Do you know any examples that they could help me?? Thanks. Antti ha scritto: > Adriano wrote: > > I'm implementing some Image Processing algorithms in VHDL, I'm testing > > these algorithms > > on the FPGA Spartan IIE xc2s200E. Is there any way to use the JTAG pins > > > > of the xc2s200E for user I/O? I want to download data from the PC, via > > a Parallel Port > > to JTAG Port on the xc2s200E. > > not directly but you can use the BSCA primitive to implement > some custom gateway that passes the data to your ip core > > AnttiArticle: 110717
On 20 Oct 2006 07:45:22 -0700, "Aaron Curtin" <acurtin@modspike.com> wrote: >Hi, I have a design that connects a Spartan 3e running a Microblaze >soft-core with an SPI unit attached to the OPB bus to a 16 Bit DAC unit >(DAC8534). The data I send to the DAC unit has the bit order reversed. > The SPI_OPB pheripheral has no way of reversing the shift out order >from what I can see. Below is a program snippet of sending data to the >dac unit: >------------------------------------------------------------------------------------------------------------------------- >// Select the DAC Unit >XSpi_mSetSlaveSelectReg(XPAR_SPI_DAC_BASEADDR, SPI_DAC_SELECT); > >// Set the message data. >send_data[0]=0x20; // Control Register >send_data[1]=0x0F; // Upper 8 bit value >send_data[2]=0x0F; // Lower 8 bit value > >// Send the message data. >spi_transfer(send_data, 3); > >// Deselect the DAC Unit >XSpi_mSetSlaveSelectReg(XPAR_SPI_DAC_BASEADDR, SPI_NONE_SELECT); >------------------------------------------------------------------------------------------------------------------------- > >The data sent to the dac unit appears as 0xF0F0 instead of 0x0F0F >disregarding the control byte. Does anyone know of how I can reverse >the bit order at a minimal overhead cost. Can you give an example of >bit order reversing? > >Thanks, >Aaron Curtin You may use a look-up table of 256 bytes. Or you may use two look-up tables of 16 bytes, one for low nibble and one for high-nibble Or you could use the trick of intergchanging adjacebts bits, then bit pairs... x= ( (x&0x55)<<1) | ((x&0xaa)>>1); x= ( (x&0x33)<<2) | ((x&0xcc)>>2); x= ( (x&0x0F)<<4) | ((x&0xF0)>>4); Whichever pelases you most ZaraArticle: 110718
"Adriano" <adrianotamburo@libero.it> schrieb im Newsbeitrag news:1161355598.926990.281240@i3g2000cwc.googlegroups.com... > Sorry, but I'm a very beginner of the FPGA technologies. What does "the > BSCA primitive" mean exactly? > Do you know any examples that they could help me?? > > Thanks. > > Antti ha scritto: > >> Adriano wrote: >> > I'm implementing some Image Processing algorithms in VHDL, I'm testing >> > these algorithms >> > on the FPGA Spartan IIE xc2s200E. Is there any way to use the JTAG pins >> > >> > of the xc2s200E for user I/O? I want to download data from the PC, via >> > a Parallel Port >> > to JTAG Port on the xc2s200E. >> >> not directly but you can use the BSCA primitive to implement >> some custom gateway that passes the data to your ip core >> >> Antti > sorry BSCAN it allows user logic to added into JTAG chain. its mostly 'advanced' topic - so there arent much easy to use examples. you can download the xilinx picoblaze stuff some of the files there use the BSCAN to load BRAMs over jtag anttiArticle: 110719
Matthew Hicks wrote: (top posting fixed) > > "Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message > news:qeuej25n60a6fi2nci8vvhji1d9sremond@4ax.com... > >>On 18 Oct 2006 03:15:59 -0700, "Jai" <jaywant.kolhe@gmail.com> wrote: >> >> >>>Hello all, >>>I want to implement integrator using vhdl, all xilinx logic core, is >>>it available or anyone worked on this topic? >> >>It's very easy... >> -- VHDL code snipped -- >> >>But the hard part is up to you... >>* when should you reset? >>* what size vector should you provide for "sigma"? >> >>Tell us more about what you want to do. Do you want a leaky >>integrator, or an unbounded one like mine? And so on... >>-- > > > For that to be a time integrator wouldn't you need to multiply your sigma > result with the period of the clock. Of course, this approximates the wave > as a series of rectangles of width T. You could do something more complex > by drawing a line between two consecutive samples and use that line to make > two rectangle with width T/2 opposed to the larger rectangle. Or you could > get really fancy and do polynomial interpolation to build finer grain > estimates. > Fancier integrator approximations only make sense if delay isn't an issue -- if the application really is agnostic to delay and sensitive to error then the OP should get a book on differential equations that includes a numerical analysis chapter. If this is going to work in a closed-loop feedback system it's exactly appropriate, and the time scaling will come out in the wash when the integration gain is chosen. If it's going into a demodulator in a communications system, or something like that, then it's more than good enough; any degradation due to 'imperfect' integration will be washed away by signal noise. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/ "Applied Control Theory for Embedded Systems" came out in April. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 110720
Hi all! We've some custom boards with i486 processor, some RAM, some dual port ram and other stuff (interrupt controller, buffers, I/O transceiver and so on). I'm investigating the opportunity to replace all of those discrete ICs with soft/hard IP (cycle accurate), and syntesize the system in an FPGA (Altera or Xilinx). Actually I don't care about costs and efforts that are involved in this approach. The goal is to get a replacement for that processor without re-writing the operating system and any other kernel routines. Any suggestions?Article: 110721
Kevin wrote: > If you have multiple paths to license files defined in your > LM_LICENSE_FILE variable you could have problems. You mentioned that > you had 2 versions of ispLEVER on your system, one with a valid license > and one with an expired license. Depending on the ordering of the > paths pointing to the 2 license.dat files in the environment variable, > flexLM may be finding the feature line in the expired license and > generating an error without even looking at the valid license. FlexLM > can be configured to search the license files until it finds a license > file that includes the feature line it is looking for, and either > starting the software when a valid license is found or generating a > license error when an expired license is found, either way stopping the > search as soon as it finds the feature line. FlexLM can also be > configured to continue searching for a valid license feature even after > it has found an invalid feature. The original software vendors, Mentor > Graphics in the case of ModelSim, configuration of the license > generation software, determine all this. I have always found that > regardless of the software tools and licenses adding all licenses into > one file and having a single path defined in the LM_LICENSE_FILE > variable is the best way to avoid these issues. Actually as I explained there was no mention of the old file path in lm_license_file or anywhere else in my system registery. It seems that ModelSim has some method of saving license file path outside of environment variables or other registry keys.Article: 110722
enavacchia@virgilio.it schrieb: > Hi all! > > We've some custom boards with i486 processor, some RAM, some dual port > ram and other stuff (interrupt controller, buffers, I/O transceiver and > so on). I'm investigating the opportunity to replace all of those > discrete ICs with soft/hard IP (cycle accurate), and syntesize the > system in an FPGA (Altera or Xilinx). > > Actually I don't care about costs and efforts that are involved in this > approach. The goal is to get a replacement for that processor without > re-writing the operating system and any other kernel routines. > > Any suggestions? there isnt any 486 class ips asfaik, some 86 maybe 286 cores do exist but if you need 486 cycle accurate its not so easy task AnttiArticle: 110723
enavacchia@virgilio.it wrote: > Hi all! > > We've some custom boards with i486 processor, some RAM, some dual port > ram and other stuff (interrupt controller, buffers, I/O transceiver and > so on). I'm investigating the opportunity to replace all of those > discrete ICs with soft/hard IP (cycle accurate), and syntesize the > system in an FPGA (Altera or Xilinx). > > Actually I don't care about costs and efforts that are involved in this > approach. The goal is to get a replacement for that processor without > re-writing the operating system and any other kernel routines. > > Any suggestions? > So you want to mimic the i486 on an FPGA, with accurate cycle timings? This sounds like a *huge* project if you can't just buy the IP off the shelf from Intel. How fast is the i486? I think you'd have no problem with replacing all the support IO with an fpga. The problem is the i486 itself. I'm assuming this is because Intel has end-of-lifed the i486 or something. Can't you go with a newer cpu that is i486 compatible? Same as the PC industry, it's all backwards compatible. Doesn't even have to be made by Intel. AMD, VIA, Transmeta, National, etc. If you can make minor tweaks to the OS your life will get very much easier. Once you get the cpu in a stable state, everything runs the same. Even if you don't have source for the OS it would be easier reverse engineering the binary, modifying the initialization of the CPU, and running with that, than trying to make a perfect i486 clone somehow. Software is always easier to work with than hardware. That's about all I can come up with. Need more input. -Dave -- David Ashley http://www.xdr.com/dash Embedded linux, device drivers, system architectureArticle: 110724
> - "netlist shematic" (where do I find/how do I generate this?) still lost on this part, even more lost after talking with someone about it. > - "waveforms from timing simulation" (are these sythesis specific, or > are these just my modelsim simulation waveforms?) same, I must be missing something very important here, from my understanding they are not modelsim simulation waveforms, but still don't know where to start. > and he also asks for the min/max clock freq, with slack times after a) > sythesis, b) mapping and c) p&r > > I will have to define a clock period I assume? Do I enter this via the > constraint editor? If so, maybe a syntax example of how I might do > this? After that I just need to view the timing reports after each > process (a,b and, c)? I've defined a timing constraint and I am able to come up with min/max/slack, but I don't understand how to get it after each of the three steps above (still).
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