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Messages from 11350

Article: 11350
Subject: Re: PCI Core In FPGA
From: alz <alz@lanminds.com>
Date: Wed, 05 Aug 1998 17:01:27 -0700
Links: << >>  << T >>  << A >>
Austin,

You're right !!  Technically it is a O/S driver.  I called it pci for
there are utilities set to specifically target the pci bus.  I like to
stay away from any Microsoft DDK and avoid the ring 3 to ring 0 
transition every time I want to access the pci bus.  If you know how to
write your own VxD or Kernel Mode driver... then you probably don't need
to purchase a set of utilities.  If you use the DDK from Microsoft you
will have to context switch every time you call your driver.

Al

Austin Franklin wrote:
> 
> > You will need pci drivers.  After checking out every software driver
> > commercially available, I've found www.tetradyne.com to be the easiest
> > and most straightforward.
> 
> Wouldn't you need O/S drivers?  There is nothing specific about a PCI
> driver over any other device (ISA, EISA etc) driver, except you need to get
> the boards address from the O/S or the BIOS...  I'm curious why you call it
>  PCI driver...
> 
> Thanks,
> 
> Austin
Article: 11351
Subject: Re: PCI Core In FPGA
From: paul@mrad.com.au (Paul Teagle)
Date: 6 Aug 1998 01:16:46 GMT
Links: << >>  << T >>  << A >>
Speaking of PCI cores, has anyone actually used (or attempted to use) the Altera core ? Any real bad stories/problems/didn't work & company went broke, that sort of thing.

We use Altera here extensively, and need to do a PCI interface. I had anticipated using the Altera pci_a core, but this newsgroup has a few rumblings about difficulty of use etc.

I don't particularly want to climb the learning curve for another manufacturer (Xilinx) if I can possibly help it.

regards,

Paul Teagle


Article: 11352
Subject: Re: Delay Element for async design.
From: allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman)
Date: Thu, 06 Aug 1998 01:46:22 GMT
Links: << >>  << T >>  << A >>
On Wed, 05 Aug 1998 10:38:01 GMT, ems@nospam.riverside-machines.com
(ems) wrote:
[snip]
>This gives you a best-case delay of 34% of the worst-case delay, ie. a
>spread of 3-1 if you're actually using the fastest part, and
>considerably worse if you're using a slow part. It also ignores
>routing delays (you may end up placing by hand, to keep routing delays
>at a small percentage of logic delays).

I just received a timing report for an XC5206 design that had been
converted to hardwire.  The report specified maximum and minimum
delays.
In most cases, the minimum delays were 20-25% of the maximum delays.

These in turn were about half of the original FPGA delays for the
longer nets.  So, if you want chip-chip compatibility over FPGA and
hardwire, you should allow for at least a 10:1 spread of delays. 
YMMV.

> I love these threads - it always gives somebody the opportunity
> to tell you that asynchronous design is impossible and
> shouldn't be done.. :)

Not impossible.  Just more "fun" than synchronous design.

Bye,
Allan.
Article: 11353
Subject: Re: PCI Core In FPGA
From: "Austin Franklin" <dark9room@ix.netcom.com>
Date: 6 Aug 1998 02:22:26 GMT
Links: << >>  << T >>  << A >>
Al,

Thanks, that was well put.  PCI access is basically just accessing memory
(that is if you are memory mapped, and most if not 99.99999% are).  What's
specifically targeted to the PCI bus, as opposed to just any other memory
location, in the utilities (aside from configuration that is)?  You seem to
know quite a bit about this, and I appreciate your technical experience.

Austin


alz <alz@lanminds.com> wrote in article <35C8F10F.BE5@lanminds.com>...
> Austin,
> 
> You're right !!  Technically it is a O/S driver.  I called it pci for
> there are utilities set to specifically target the pci bus.  I like to
> stay away from any Microsoft DDK and avoid the ring 3 to ring 0 
> transition every time I want to access the pci bus.  If you know how to
> write your own VxD or Kernel Mode driver... then you probably don't need
> to purchase a set of utilities.  If you use the DDK from Microsoft you
> will have to context switch every time you call your driver.
> 
> Al
> 
> Austin Franklin wrote:
> > 
> > > You will need pci drivers.  After checking out every software driver
> > > commercially available, I've found www.tetradyne.com to be the
easiest
> > > and most straightforward.
> > 
> > Wouldn't you need O/S drivers?  There is nothing specific about a PCI
> > driver over any other device (ISA, EISA etc) driver, except you need to
get
> > the boards address from the O/S or the BIOS...  I'm curious why you
call it
> >  PCI driver...
> > 
> > Thanks,
> > 
> > Austin
> 
Article: 11354
Subject: Re: Silicore VHDL 8-bit RISC uC core for FPGA
From: "Richard B. Katz" <stellare@erols.com>
Date: Wed, 05 Aug 1998 22:51:44 -0400
Links: << >>  << T >>  << A >>
Wade D. Peterson wrote:

> >>I'd like to hear more about coding to protect against radiation
> >>induced errors.  Could you elaborate on that?  Is this a redundancy
> >>thing?
> >Correct, it is very simple, in my case I changed each FF to three FF with a
> >majority voting system on the output. Thus if any FF is changed due to
> >radiation effects (e.g. heavy protons) the majority voting system will output
> >the correct value (majority is always right??). The possibility of two FF being
> >hit at the same time or before the FF is used is relative small. Adding these
> >extra two FF is done automatically by most synthesis tools (Actel, Synplicity,
> >Synopsys).
>
> That's pretty clever.  Never heard of that before. Any idea what they
> call that technique?  I looked in my synthesis package manual, but
> didn't see anything.

It's an implementation of TMR or triple modular redundancy.  Three was chosen to
minimize the overhead and it makes the probability of failure, from multiple ions,
extremely low.  The calculations and basic circuits are published in IEEE
Transactions on Nuclear Science, Dec., '94, "SEU Hardening of ...".  Actel has an
on-line app note based on this article.  Slides from the '94 presentation as well as
the app note is at http://rk.gsfc.nasa.gov.  Also, descriptions of the s/w to do the
TMR implementation, based on above, is compiled and described on the rk... www site
for actel, synplicity, and synopsys.  Examplar also has something, it's in beta i
believe, and they said they would send it out.

for this to work, you need to have a solid, free-running clock.  a clock upset from
radiation will do it in.  a static clock, such as a simple bus decode and store into
a register will also fail, eventually, as two errors can accumulate.  structures
need to have a running clock with the voter in the feedback loop for a holding
register or a j-k flip-flop.  it turns out that the voter fits nicely into an actel
logic module, which is based on a 4:1 mux (the original design, from ancient times,
was based on the 54ls253)..  for certain common structures, such as shift registers,
the mux can be triplicated and 'combined' (act 1,2,3,3200dx, xl) with the f-f for no
overhead and no loss in speed.  SX is a bit different.  when you run the numbers,
even a low-speed clock will do fine for 'refresh' or 'self-scrubbing', verified by
ground radiation tests and works for the same reason that memory scrubbing works
(unless you choose a memory chip with the wrong physical architecture, but that's
another story).

rk

Article: 11355
Subject: Re: [Q] motor control onto an FPGA
From: leslie.yip@asmpt.com
Date: Thu, 06 Aug 1998 07:11:29 GMT
Links: << >>  << T >>  << A >>
Yes, to design a motion controller in FPGA is not too difficult but the
effort is quite demanding. It will be better to use an CPU (typically DSP)
and a FPGA (like motion encoder interface, pattern generator or other
filters) together. My company uses them to work well on large precise
automatic bonding machine. To take a glance at the motion controller, visit
National Semiconductor's web site: the data sheet & application notes about
LM629.

Leslie Yip

In article <35C77D65.E2549B2E@ids.net>,
  Ray Andraka <no_spam_randraka@ids.net> wrote:
>
>
> Andy Peters wrote:
>
> > Paul Oh <paul@moray.cs.columbia.edu> wrote in article
> > <Pine.GSO.3.96.980727124610.6724A-100000@moray.cs.columbia.edu>...
> >
> > > I am newbie to FPGA.  I am looking into programming my own silicon.
> >  Can
> > > any one give pointers (books, websites) into developing motion
> > control
> > > IC's?
> > >
> > > Specifially: PID (proportional-integral-derivative) control
> > > Trapezoidal motion profiles
> >
> > IMHO:
> >
> > If you're serious about PID loops, etc, forget the FPGA and use a
> > microcontroller or one of the new fast cheap DSPs.  You'll be glad
> > you did.
> >
> > If you're serious about motion control, forget rolling your own and
> > buy an off-the-shelf solution, like CompuMotor or something like
> > that.  You'll be glad you did.
> >
> > > PS: I have *never* programmed FPGA's before (I am a mechie).  I
> > have a
> > > high-level understanding of the design process: Essentially you
> > burn an
> > > FPGA just like an EPROM right using schematic CAD or C-like
> > programming
> > > languages right? I intend to use Xilinx's development
> > > board/tools.  I do have a good grasp on logic, digital design,
> > control
> > > systems, programming and embedded micros though.
> >
>
> Motor controls are not extraordinarily difficult to implement in FPGAs.
> However, you should have a background in motion control before attempting
> to roll your own, as there are many pitfalls for the neophyte.  If you
> intend to use an FPGA only for the motion control, and your control
> algorithm is one that is supported by off the shelf chips, you'd be
> better off using the canned solution.  However, if you intend to
> integrate custom logic in with the controller, or have an algorithm not
> supported by the off-the-shelf solution, the FPGA may be a good idea.
>
> As for the FPGA design, the design is captured either as a schematic or
> in one of several textual hardware description languages.  If the desired
> clock rates are low, you can get away with sloppy design practices using
> either entry method.  As your required performance and/or density
> increases, good design technique, knowledge of the FPGA architecture and
> the idiosyncracies of the synthesis engine (if a hardware description
> language is used) become more important for a successful design.
>
> The hardware description languages (predominantly VHDL, Verilog and Abel)
> used for FPGAs are rather different than C, and will probably add another
> steep learning curve to your task.
>
> The captured design is translated, mapped, placed and routed by the FPGA
> tools.  Translation converts the entered design into a database
> understandable by the tools.  Mapping breaks the design into logic units
> consistent with the device architecture, and usually includes some logic
> optimization.  The place and route assigns the mapped logic to locations
> in the FPGA then turns on switches in the routing matrix to make the
> connections between logic blocks.  If the designer understands the device
> architecture, he can bias the entered design to take advantage of device
> features.  This combined with pre-placing logic blocks (floorplanning)
> can result in substantially better results in terms of both performance
> and area (number of cells used).  The resulting placement and routing is
> converted into a bitstream that is loaded into the device.  In that
> respect, the design flow is more like compiling a higher level language
> into machine code.  That machine code (or in this case the bit stream) is
> what gets loaded into the eprom or FPGA.
>
> > As for designing FPGAs, check out the web sites of Xilinx or Altera
> > or Actel or any of the other FPGA vendors.  And be prepared to climb
> > a somewhat steep learning curve.
> >
> > -andy
> >
> > --
> > Andy Peters
> > Sr. Electrical Engineer
> > National Optical Astronomy Observatories
> > apeters@noao.edu.NOSPAM
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka
>
>

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
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Article: 11356
Subject: Re: TRISTATE in FPGA
From: iman@mercury.news.pacific.net.sg ( Imanuddin Amril Account)
Date: 06 Aug 1998 07:27:59 GMT
Links: << >>  << T >>  << A >>
In article <w05emv1srvr.fsf@clpc20.comlab> Jamie Lokier <spamfilter.aug1998@tantalophile.demon.co.uk> writes:

 
   Wouldn't be nice of the synthesis tools could map this into working
   non-tristate logic when there aren't enough tristate resources, or when
   use of tristate impedes routing?

That's cool :-)

I solved my problem ready. Thanks for discussion that open my eyes 
larger to understand the fpga architecture.

Actually I have five components using tristate. All four components 
are using 8 tristate to drive single bus (8 lines), but another one 
occupies very large numbers, i.e five buses (8 lines each). So, total 
tristate for this "BIG" guy is 5x8 = 40 tristates. And the error comes
from this component *only*.

As a solution, I changed all the tristates to 2-input "AND" gate 
construct and "OR" all the five outputs to drive single 8-lines bus.

So far so good. I did success PPR.

Rgds
-- 
-iman
===============================================
= Watch the transformation or be a part of it =
===============================================
Article: 11357
Subject: Re: Silicore VHDL 8-bit RISC uC core for FPGA
From: Stephen Maudsley <Stephen.Maudsley@esgem.com>
Date: Thu, 06 Aug 1998 09:48:40 +0100
Links: << >>  << T >>  << A >>
Hans wrote:

> In article <6q9lol$q2c$1@news1.tc.umn.edu>, peter299@maroon.tc.umn.edu says...
> >
> >nospam_ees1ht@ee.surrey.ac.uk (Hans) wrote:
> >
> >>Not really in a lot of application you want to develop your own core, in my
> >>case I added coding to protect against radiation induced errors.
> >>Hans
> >
> >I'd like to hear more about coding to protect against radiation
> >induced errors.  Could you elaborate on that?  Is this a redundancy
> >thing?
> Correct, it is very simple, in my case I changed each FF to three FF with a
> majority voting system on the output. Thus if any FF is changed due to
> radiation effects (e.g. heavy protons) the majority voting system will output
> the correct value (majority is always right??). The possibility of two FF being
> hit at the same time or before the FF is used is relative small.

Is there a minimum placing distance between the FF so that events are independent?
--
Stephen Maudsley  Stephen.Maudsley@esgem.com
Esgem Limited  http://www.esgem.com
Tel: +44-1453-521626 Mobile: +44-370-810991




Article: 11358
Subject: Re: PCI Core In FPGA
From: ems@nospam.riverside-machines.com (ems)
Date: Thu, 06 Aug 1998 09:46:04 GMT
Links: << >>  << T >>  << A >>
On Wed, 05 Aug 1998 16:55:59 -0700, alz <alz@lanminds.com> wrote:

>Austin,
>
>You're right !!  Technically it is a O/S driver.  I called it pci for
>there are utilities set to specifically target the pci bus.  I like to
>stay away from any Microsoft DDK and avoid the ring 3 to ring 0 
>transition every time I want to access the pci bus. 

not so. most of what the user sees from the driver is simply a memory
window. the normal procedure is:

(1) the user loads the driver
(2) the user then calls a driver routine which returns the virtual
addresses of any memory regions used by the card
(3) the user now has full and direct R/W access to these memory
regions

you can't do this without a driver (certainly in 9x/NT - don't know
about 3.1). any pci utilities that you may be able to buy are simply
drivers that carry out the plug'n'pray and memory mapping functions
for you.

i can't think of any specific ring 3/ring 0 transitions which have a
significant (or any) impact on a user. however, there are issues
related to scheduling information transfers between the driver and the
user (at interrupt time, for example).

>If you know how to
>write your own VxD or Kernel Mode driver... then you probably don't need
>to purchase a set of utilities.  If you use the DDK from Microsoft you
>will have to context switch every time you call your driver.

it can be useful to have third-party software to carry out initial
testing, and to carry out testing which is independent of your own
driver. but, if you have any complexity at all in your hardware (ie.
interrupts or DMA), then you'll have to write your own driver. this
isn't particularly difficult (on '95, anyway - i haven't done a '98 or
NT driver yet). the major problem is that micro$oft's documentation is
next to useless. however, if you want, you can buy third-party
development systems which automate much of the process.

evan

Article: 11359
Subject: Re: Silicore VHDL 8-bit RISC uC core for FPGA
From: "Richard B. Katz" <stellare@erols.com>
Date: Thu, 06 Aug 1998 07:40:24 -0400
Links: << >>  << T >>  << A >>
Stephen Maudsley wrote:

> Hans wrote:
>

<snip>

> > Correct, it is very simple, in my case I changed each FF to three FF with a
> > majority voting system on the output. Thus if any FF is changed due to
> > radiation effects (e.g. heavy protons) the majority voting system will output
> > the correct value (majority is always right??). The possibility of two FF being
> > hit at the same time or before the FF is used is relative small.
>
> Is there a minimum placing distance between the FF so that events are independent?
> --
> Stephen Maudsley  Stephen.Maudsley@esgem.com
> Esgem Limited  http://www.esgem.com
> Tel: +44-1453-521626 Mobile: +44-370-810991

for discrete sram chips where the flip-flops are tightly packed, this is a concern,
and 'multiple bit upset' is a real consideration (see paper by R. Koga from aerospace
corporation).  a good sram chip for the radiation environment would have an
architecture to support effective radiation hardness achieved by coding schemes.  x1
chips, for example, are obvious solutions.  for the x4 or x8 devices, the logical bits
in a word should be physically separated (i.e., micron 128kx8, hitachi 32kx8).  micron
used to be a military provider.  hitachi, in the 128kx8 and i believe the 512kx8 also
put logical bits physically together, which will defeat the corrective power of the
hamming codes or a tmr which has similar characteristics.  in this case a reed-solomon
could would be used, but is inconvenient since it's a block code.  data shows that
these sort of chips do have multiple bit errors and it's not just a theoretical thing.

another consideration is the circuit design of the cell.  excluding access
transistors, a 4-T storage cell should be used.  if a 2-T + 2-R configuration is used,
where the value of R is EXTREMELY high (as in commercial SRAMs), then a single heavy
ion strike can cause a tad of leakage resulting in a 'stuck bit' with obvious
implications on error correcting coding schemes.  again, this is seen in real data.

what does this mean for fpga?  well, it depends on the device architecture and
layout.  for devices with sram the work previously done for discrete sram chips needs
to be applied, carefully, both in circuit design and layout.

hope this helps,

rk

Article: 11360
Subject: Negative pulse form Altera FPGA's ?
From: Botond Kardos <Kardos.Botond@hu.innomed.NOSPAM>
Date: Thu, 06 Aug 1998 09:07:31 -0400
Links: << >>  << T >>  << A >>
Hi everybody,
   I would like to do the following in a Flex10K or 8K dvice:
   A nCAS signal needs to be generated for an EDO DRAM. I would like to
start the nCAS signal at a given clock edge and gate the data bus at te
next one. To maintain some setup times the nCAS has to be as close to
the clock as possible and must be deasserted before the next psoitive
clock edge.
   It's quite simple to do this in a Flex FPGA using IOBs:

              I----I    I----I
   clock: ----I    I----I    I--
               I-----I   I-----I
   CAS:   -----I     I---I     I---

   The clock-to-CAS delay is the shortest if the CAS signal comes out of
an IOB register that clocks a '1' on the positive edge and gets cleared
after the negative edge (of course the clear signal is very short).
   My question is: is there a way to generate the inverse of the CAS
signal ?

   Thx for any help,
   Botond

-- 
Botond Kardos  -  at Innomed Medical Inc. in Hungary
eMail: Kardos.Botond@hu.innomed.NOSPAM
phone/fax: (0036 1) 351-2934
fax: (0036 1) 321-1075
      To get my real address just put the domain
      name in reverse order and remove 'nospam'.
      x@1.2.3 -> x@2.1
Article: 11361
Subject: Re: [Q] motor control onto an FPGA
From: tronsmith@my-dejanews.com
Date: Thu, 06 Aug 1998 14:30:45 GMT
Links: << >>  << T >>  << A >>
In article <6q82kh$5vr$1@news-1.news.gte.net>,
  sja@gte.net (Steven J. Ackerman) wrote:
> On Mon, 27 Jul 1998 12:52:22 -0400, Paul Oh
> <paul@moray.cs.columbia.edu> wrote:
>
> Check out National Semiconductor's LM628/629 motion controller ICs.
>

Analog Devices also has a part that looks very slick, I think
the P/N is ADM300 or ADM330. It incorporates PWMs, DSP w/ Prom'd monitor and
math routines, I think an A/D or two, timers, all good stuff.
A lot easier to develop algorithms with than a standalone FPGA.

I've been doing a motor control app in FPGA coupled w/ processor.
FPGA handles low order functions (PWMs, position decoders,
timing of A/D conversion for current sensors) while processor
handles 'higher functions' such as PID control. FPGA is used
in this case for multiple motor control, but for a single
device, I'd go with a single chip dedicated controller as
suggested above.

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
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Article: 11362
Subject: AD: Reading Secured Devices
From: gangli@mediaone.net (Gang Li)
Date: Thu, 06 Aug 1998 15:18:12 GMT
Links: << >>  << T >>  << A >>
If you have a secured device, such as a GAL, PAL, microcontroller, and
FPGA, with the contents of which you are interested in recovering and
providing the contents are not copyrighted (or you are the copyright
holder), we may be able to help you. We also have reader/analyzer for
reading/analyzing various secured GAL's and PAL's.

Please call: 1-404-228-1693 for further details.
Article: 11363
Subject: Re: PCI Core In FPGA
From: alz <alz@lanminds.com>
Date: Thu, 06 Aug 1998 09:05:29 -0700
Links: << >>  << T >>  << A >>
Evan,

> i can't think of any specific ring 3/ring 0 transitions which have a
> significant (or any) impact on a user. however, there are issues
> related to scheduling information transfers between the driver and the
> user (at interrupt time, for example).


For computer graphics the ring3/ring0 transition is significant.  Every
graphics chip company around avoids ring3/ring0 transitions in their
drivers.

Al
Article: 11364
Subject: Re: PCI Core In FPGA
From: alz <alz@lanminds.com>
Date: Thu, 06 Aug 1998 09:57:19 -0700
Links: << >>  << T >>  << A >>
Paul,

Check out www.plda.com   They have a very easy to implement pci core.
The core is limited to Altera devices only.

Al


Paul Teagle wrote:
> 
> Speaking of PCI cores, has anyone actually used (or attempted to use) the Altera core ? Any real bad stories/problems/didn't work & company 
went broke, that so
> 
> We use Altera here extensively, and need to do a PCI interface. I had anticipated using the Altera pci_a core, but this newsgroup has a few 
rumblings about dif
> 
> I don't particularly want to climb the learning curve for another manufacturer (Xilinx) if I can possibly help it.
> 
> regards,
> 
> Paul Teagle
Article: 11365
Subject: Re: PCI Core In FPGA
From: "Austin Franklin" <dark9room@ix.netcom.com>
Date: 6 Aug 1998 17:34:18 GMT
Links: << >>  << T >>  << A >>


alz <alz@lanminds.com> wrote in article <35C9E06F.5985@lanminds.com>...
> Paul,
> 
> Check out www.plda.com   They have a very easy to implement pci core.
> The core is limited to Altera devices only.

Do you know if it uses two pins (which is a violation of the PCI spec) on
some of the control signals?  This is why the Altera core is not PCI
compliant.

Austin

Article: 11366
Subject: Re: PCI Core In FPGA
From: Barry Brown <barry@sr.hp.nospam.com>
Date: Thu, 06 Aug 1998 16:21:42 -0700
Links: << >>  << T >>  << A >>
John Chambers wrote:
> 
> I'm considering moving some of my boards to the PCI interface.  Can you
> recommend a PCI interface chip to do simple IO.  My application is
> little more than a DIO board with interrupts.
> 

www.vcubed.com
   .plxtech.
   .amcc.
   .anchorchips.
-- 
Barry A. Brown
Microwave Instruments Division
Hewlett-Packard Company
****  Remove the "nospam" from my email address  *****
Article: 11367
Subject: Re: PCI Core In FPGA
From: Al Zimmerman <alz@RayCast.com>
Date: Thu, 06 Aug 1998 16:29:34 -0700
Links: << >>  << T >>  << A >>
Austin,

You're right !!  

Al


Austin Franklin wrote:
> 
> alz <alz@lanminds.com> wrote in article <35C9E06F.5985@lanminds.com>...
> > Paul,
> >
> > Check out www.plda.com   They have a very easy to implement pci core.
> > The core is limited to Altera devices only.
> 
> Do you know if it uses two pins (which is a violation of the PCI spec) on
> some of the control signals?  This is why the Altera core is not PCI
> compliant.
> 
> Austin
Article: 11368
Subject: Re: Delay Element for async design.
From: Rickman <spamgoeshere4@yahoo.com>
Date: Thu, 06 Aug 1998 22:14:06 -0400
Links: << >>  << T >>  << A >>
ems wrote:
> 
> On Sun, 26 Jul 1998 02:10:51 GMT, Eddie Ng <ngeddie@tor.shaw.wave.ca>
> wrote:
> 
> >Dear All,
> >    I'm using Altera FLEX 10K series FPGA right now and I need to
> >implement an delay element that would do ideally pure delay or
> >not-too-bad inertial delay.  Much like a series of even-numbered
> >inverters in series to introduce propagation delay but with accurate
> >delay time, preferrably "programmable" or "parameterizable".
> >    I'm using it to implement an asynchronous micropipeline structure in
> >which delay is added on the control signals to match/exceed the delay on
> >the bundled data lines to meet the bundled contrains.
> 
> I love these threads - it always gives somebody the opportunity to
> tell you that asynchronous design is impossible and shouldn't be
> done.. :)
...snip...
> This gives you a best-case delay of 34% of the worst-case delay, ie. a
> spread of 3-1 if you're actually using the fastest part, and
> considerably worse if you're using a slow part. It also ignores
> routing delays (you may end up placing by hand, to keep routing delays
> at a small percentage of logic delays).

One source of variation that you left out is changes (over the lifetime
of a part) in the detail design and techology of a part. Xilinx
published an app note on this and indicated that they reserve the right
to alter the internal workings of a part to make it more manufacturable.
So even if you make the logic delay dominate over routing delay, the
logic delay of any given portion of the chip may be greatly accelerated. 

For example, they may reduce the feature size of the part and end up
making the H block much faster than the F or G blocks relative to the
old design. The new part will still meet spec, but some paths of your
design may become much faster than the others. 

As you point out, implementing this circuit in an FPGA is most likely a
testbench. But it is a pretty poor testbench for this particular
circuit. 

But all of our comments are relative to the Xilinx. I don't know the
Altera 10K so well, but don't they have much more deterministic routing?
This may make it more pratical if the routing delay dominates. 


-- 

Rick Collins

rickman@XYwriteme.com

remove the XY to email me.
Article: 11369
Subject: Re: Silicore VHDL 8-bit RISC uC core for FPGA
From: peter299@maroon.tc.umn.edu (Wade D. Peterson)
Date: Fri, 07 Aug 1998 06:44:23 GMT
Links: << >>  << T >>  << A >>

>> > Correct, it is very simple, in my case I changed each FF to three FF with a
>> > majority voting system on the output. Thus if any FF is changed due to
>> > radiation effects (e.g. heavy protons) the majority voting system will output
>> > the correct value (majority is always right??). The possibility of two FF being
>> > hit at the same time or before the FF is used is relative small.
>>
>> Is there a minimum placing distance between the FF so that events are independent?
>> --
>> Stephen Maudsley  Stephen.Maudsley@esgem.com
>> Esgem Limited  http://www.esgem.com
>> Tel: +44-1453-521626 Mobile: +44-370-810991

>for discrete sram chips where the flip-flops are tightly packed, this is a concern,
>and 'multiple bit upset' is a real consideration (see paper by R. Koga from aerospace
>corporation).  a good sram chip for the radiation environment would have an
>architecture to support effective radiation hardness achieved by coding schemes.  x1
>chips, for example, are obvious solutions.  for the x4 or x8 devices, the logical bits
>in a word should be physically separated (i.e., micron 128kx8, hitachi 32kx8).  micron
>used to be a military provider.  hitachi, in the 128kx8 and i believe the 512kx8 also
>put logical bits physically together, which will defeat the corrective power of the
>hamming codes or a tmr which has similar characteristics.  in this case a reed-solomon
>could would be used, but is inconvenient since it's a block code.  data shows that
>these sort of chips do have multiple bit errors and it's not just a theoretical thing.

>another consideration is the circuit design of the cell.  excluding access
>transistors, a 4-T storage cell should be used.  if a 2-T + 2-R configuration is used,
>where the value of R is EXTREMELY high (as in commercial SRAMs), then a single heavy
>ion strike can cause a tad of leakage resulting in a 'stuck bit' with obvious
>implications on error correcting coding schemes.  again, this is seen in real data.

>what does this mean for fpga?  well, it depends on the device architecture and
>layout.  for devices with sram the work previously done for discrete sram chips needs
>to be applied, carefully, both in circuit design and layout.

>hope this helps,

>rk

So how do you test for radiation?  Off the top of my head it would
seem that you would need some kind of calibrated particle beam or
reactor or something.  Stick the board in there and see if it keeps
working.  Are there commercial test labs that do that sort of thing?

Regards,

Wade Peterson
Silicore Corporation, www.silicore.net


Article: 11370
Subject: Re: Delay Element for async design.
From: ems@nospam.riverside-machines.com (ems)
Date: Fri, 07 Aug 1998 10:54:53 GMT
Links: << >>  << T >>  << A >>
On Thu, 06 Aug 1998 22:14:06 -0400, Rickman <spamgoeshere4@yahoo.com>
wrote:

>As you point out, implementing this circuit in an FPGA is most likely a
>testbench. But it is a pretty poor testbench for this particular
>circuit. 

true enough, and anyone who wants to do this is going to have to take
their chances with process mods. the problem is that there's a fair
amount of interest, academically and commercially, in developing this
sort of circuit. the only practical way to quickly and cheaply
prototype your ideas is in an fpga. sure, it might be better to do
it discretely, with properly specced components, but that might
involve learning some electronics...  :)

evan

Article: 11371
Subject: Re: PCI Core In FPGA
From: ems@nospam.riverside-machines.com (ems)
Date: Fri, 07 Aug 1998 10:56:17 GMT
Links: << >>  << T >>  << A >>
On Thu, 06 Aug 1998 09:05:29 -0700, alz <alz@lanminds.com> wrote:

>> i can't think of any specific ring 3/ring 0 transitions which have a
>> significant (or any) impact on a user. however, there are issues
>> related to scheduling information transfers between the driver and the
>> user (at interrupt time, for example).
>
>
>For computer graphics the ring3/ring0 transition is significant.  Every
>graphics chip company around avoids ring3/ring0 transitions in their
>drivers.

it doesn't matter what sort of chip or board you're putting on the
bus. the vast majority of windows pci drivers will not require the use
of signalling mechanisms, which would involve ring0/ring3 transitions,
between the driver and the user.

the only point in most drivers, after initialisation, at which a
transition occurs, is when a hardware interrupt arrives (and the S3
card in my test system doesn't even generate interrupts). your ring 0
driver will receive control fairly quickly, and will then schedule
some sort of information transfer to the user code. this will involve
another transition, but this is part of the normal scheduling
mechanisms and so isn't relevant. in short, ring0/ring3 transitions
simply aren't relevent, whether or not you're using interrupts.

what you're thinking about may be the issue of virtualising the PC
display. there are circumstances in which the OS will create multiple
virtual copies of physical display memory, and will then trap any
accesses to this memory, so that display drivers can pretend that they
have exclusive control over the display. this isn't an issue with pci
drivers, and you still need the ddk, or an equivalent, to write your
pci driver.

evan

Article: 11372
Subject: Re: Silicore VHDL 8-bit RISC uC core for FPGA
From: "Richard B. Katz" <stellare@erols.com>
Date: Fri, 07 Aug 1998 08:04:45 -0400
Links: << >>  << T >>  << A >>
Wade D. Peterson wrote:

<some serious snipping>

> So how do you test for radiation?  Off the top of my head it would
> seem that you would need some kind of calibrated particle beam or
> reactor or something.  Stick the board in there and see if it keeps
> working.  Are there commercial test labs that do that sort of thing?
>
> Regards,
>
> Wade Peterson
> Silicore Corporation, www.silicore.net

exactly.  there are a number of facilities available capable of doing that sort of
testing.  there's a good tutorial/primer on the aerospace corporation site at:

    http://www.aero.org/activities/seet/

rk

Article: 11373
Subject: Employment opportunities in NEC Development Center, Princeton, NJ
From: Zoran Miljanic <zoran@ccrl.nj.nec.com>
Date: Fri, 07 Aug 1998 09:47:03 -0400
Links: << >>  << T >>  << A >>
Employment opportunities in NEC Development Center, Princeton, NJ

VHDL/Verilog RTL design of advanced communication processor  

Requirement:
B.Sc./M.Sc. or Ph.D. in EE and 3+ years hands-on experience in high
speed digital VLSI design. Experience in the CPU  microarchitecture
definition and the design of RISC type microprocessors. 

If interested please contact Zoran Miljanic at zoran@ccrl.nj.nec.com
Article: 11374
Subject: Re: Negative pulse form Altera FPGA's ?
From: Tullio Grassi <Tullio.Grassi@cern.ch>
Date: Fri, 07 Aug 1998 17:07:11 +0200
Links: << >>  << T >>  << A >>
Botond Kardos wrote:
> 
> Hi everybody,
>    I would like to do the following in a Flex10K or 8K dvice:
>    A nCAS signal needs to be generated for an EDO DRAM. I would like to
> start the nCAS signal at a given clock edge and gate the data bus at te
> next one. To maintain some setup times the nCAS has to be as close to
> the clock as possible and must be deasserted before the next psoitive
> clock edge.
>    It's quite simple to do this in a Flex FPGA using IOBs:
> 
>               I----I    I----I
>    clock: ----I    I----I    I--
>                I-----I   I-----I
>    CAS:   -----I     I---I     I---
> 
>    The clock-to-CAS delay is the shortest if the CAS signal comes out of
> an IOB register that clocks a '1' on the positive edge and gets cleared
> after the negative edge (of course the clear signal is very short).
>    My question is: is there a way to generate the inverse of the CAS
> signal ?
> 
>    Thx for any help,
>    Botond
> 
> --
> Botond Kardos  -  at Innomed Medical Inc. in Hungary
> eMail: Kardos.Botond@hu.innomed.NOSPAM
> phone/fax: (0036 1) 351-2934
> fax: (0036 1) 321-1075
>       To get my real address just put the domain
>       name in reverse order and remove 'nospam'.
>       x@1.2.3 -> x@2.1


If I haven't misunderstoood, you need just to connect the
D input of the FF to GND, and the ASET input of the FF to 
a NOR feeded by clock and by the output of the FF (that is
the inverse of CAS).
-- 
                                      Tullio
 
Doctoral student -  Univ. of Padova / Cern (Geneva)
Home page:   http://nicewww.cern.ch/~tgrassi


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