Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 15300

Article: 15300
Subject: Re: Power Estimiation - report.zip (0/1)
From: Richard Guerin <guerin2@home.com>
Date: Thu, 18 Mar 1999 01:46:17 GMT
Links: << >>  << T >>  << A >>
It would be nice to be able to graphically display calculated average
power (either cumulative or by node) as an analog waveform in ModelSim
:-)  ... PE for us cheap guys ;-)


> There follows below (attached) a zipped toggle report from ModelSim.

<snip>
 
> "All" it then requires is for the P&R tool to take the die, and
> annotate the necessary physical charactaristics, and your wish can
> come true with some parsing and simple math. So I wonder which FPGA
> vendor will have the (4/3 pi r cubed)'s to make that data available,
> or provide a tool to parse such a netlist and report power back.
Article: 15301
Subject: Re: Xilinx Spartan configuration troubles
From: Jeff Hunsinger <huns@mediaone.net>
Date: Wed, 17 Mar 1999 20:00:10 -0600
Links: << >>  << T >>  << A >>
Thanks to all who responded. My problem turned out to be leaving the
MODE pin floating and counting on the weak pull-up to keep it high.

I tied a 10K pullup to VCC and all my problems disappeared.

Thanks again,
Jeff
Article: 15302
Subject: Re: Xilinx Spartan configuration troubles
From: Hobson Frater <hobson@xilinx.com>
Date: Wed, 17 Mar 1999 18:38:18 -0800
Links: << >>  << T >>  << A >>
Something else you might like to try is using the FPGA Configuration
Problem Solver on our website.  Simply go to http://support.xilinx.com
and click on 'FPGA Configuration' to step through a series of questions
that will help you to debug the problem.

Regards,
Hobson Frater
Xilinx Applications

Article: 15303
Subject: Re: Power Estimiation
From: Richard Guerin <guerin2@home.com>
Date: Thu, 18 Mar 1999 02:47:50 GMT
Links: << >>  << T >>  << A >>
bob elkind wrote:
> It won't be perfect, its results won't be guaranteed, but it would
> still be a *big* help.  And my guess is that the data required to "code"
> this is already lying around in the engineering dept.
> 
> Does anyone agree that this would help ?  Does anyone agree that this
> is worth doing ?   Does anyone have any better solutions, or improvements ?

Virtually anything would be an improvement over the cowboy techniques
<demonstrating a shooting from my hips gesture> that designers are
forced to employ. 

The problem only worsens as enabling technology trends continue that
allow higher levels of on-chip integration and complexity
(System-On-A-Chip seems to be a hot buzz word these days). Wonder which
FPGA synthesis vendor will be the 1st to offer power driven synthesis
...which FPGA vendor will take the lead roll in supporting an integrated
solution ?
Article: 15304
Subject: Xilinx routing problem: removing "reset" increases cycle time.
From: Zhen Luo <zhenluo@ee.princeton.edu>
Date: Thu, 18 Mar 1999 00:47:13 -0500
Links: << >>  << T >>  << A >>
I have a design that used a global reset signal on XC4000e. Later on I
removed this signal since I decided to utilize the initial "0" state of
all FFs. However, I could never synthesize my design at the clock rate
it used to be. Anyone has the same exprience here? How could I get
around this problem?

-- Zhen


Article: 15305
Subject: SRL16 simulation models
From: simon_bacon@my-dejanews.com
Date: Thu, 18 Mar 1999 09:21:23 GMT
Links: << >>  << T >>  << A >>
Hoping to minimise the number of hours wasted on this...

If you are using the Virtex SRL16 component in a VHDL
design, be aware that the older unisim simulation
models are inaccurate.  In particular, the unisim
library distributed with the ActiveVHDL evaluation CD
in the Foundation 1.5 release contains an inaccurate
model of SRL16.

The more recent unisim releases are OK; the comments at
the head of the file list the update history.

--
Simon

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 15306
Subject: Reconfigurable computing thesis on the web
From: zik@zikzak.net (Zik Saleeba)
Date: 18 Mar 1999 20:43:14 +1100
Links: << >>  << T >>  << A >>
I've put together an online version of my recent thesis on
reconfigurable computing for people to view on the web or download as
postscript.

The idea behind the thesis was to create a new kind of computer
architecture based around reconfigurable logic which was effective
not only for the rarified set of problems current FPGA systems are
applicable to - but could also be applied to the same sorts of
problems as conventional general-purpose processors.

Enjoy!

http://www.cs.monash.edu.au/~zik/thesis.html

---------------------------------------------------------------------
Abstract

In the fast-paced field of computing new technologies appear, are
developed and then become outdated all within a few years. The
underlying architectural precepts on the other hand remain relatively
constant. Modern CPUs use the same sequential execution model which
has been with us since Von Neumann. The latest processors use
performance features such as caching, deep pipelining and register
scoreboarding which are really only minor adaptations of techniques
which have been used for twenty years.

Reconfigurable logic arrays give us the opportunity to embrace an
entirely new approach to computing. The technology is still young so
there is a great deal to be done before this new medium reaches the
maturity of conventional processors. Current reconfigurable logic
arrays are limited to specialised custom computing tasks and are not
suitable for the wide variety of tasks which general purpose
computers tackle.

This thesis demonstrates that reconfigurable processors _do_ have the
potential to entirely replace conventional processors. The
Switchblade system described is a complete standalone general-purpose
computer based entirely around a reconfigurable logic array. It lacks
only hardware implementation and appropriate software to make it a
realisable system.

A significant aspect of this thesis is that it points the way to a
major paradigm shift in the way computations can be performed.
Instead of devising algorithms to run on and exploit a given computer
architecture, an architecture is defined dynamically to perform the
computation. While much work is still required the conceptual
framework presented here paves the way for exciting future
developments.
---------------------------------------------------------------------

Zik Saleeba
Article: 15307
Subject: Re: Clock multiplier
From: Ed McCauley <emccauley@bltinc.com>
Date: Thu, 18 Mar 1999 08:22:06 -0500
Links: << >>  << T >>  << A >>
Sven:

Just a quick thought that might help...

Do you actually need to multiply OR do you simple want a Frequency 100x
your original?  

To the point:  
1. Build a DPLL that generates your HF clock (Fout)
2. Divide Fout by 100 and compare fout/100 with Fin using that as the
feedback to the DPLL

There are several timing constraints (dare I use that work outside of
Xilinx-land) that need to be considered.


-- 
Ed McCauley
Bottom Line Technologies Inc.
http://www.bltinc.com
Specializing Exclusively in Xilinx Design, Development and Training
Voice: (500) 447-FPGA, (908) 996-0817
FAX:   (908) 996-0787



Sven Svensson wrote:
> 
> Does anyone have a suggestion on how to make a clock multiplier
> according to specs below:
> 
> Fin: 10 Hz - 2000 Hz
> Fout: Fin*100
> 
> I would like to use a FPGA but other ideas are also appreciated.
> 
> Sven
Article: 15308
Subject: Re: Possible problem with die shrink of xc4010
From: Ed McCauley <emccauley@bltinc.com>
Date: Thu, 18 Mar 1999 08:31:34 -0500
Links: << >>  << T >>  << A >>
Gilles:

1. I second Ray's idea.  I'd take the OSC4 symbol and take its F15
output to the pin through an OBUF.  If you see ~15Hz, the pin is fine.
2. MORE likely, you have a circuit that is failing timing
3. MOST likely, you have a circuit that has one or more unmanaged
asynchronous events going on.

-- 
Ed McCauley
Bottom Line Technologies Inc.
http://www.bltinc.com
Specializing Exclusively in Xilinx Design, Development and Training
Voice: (500) 447-FPGA, (908) 996-0817
FAX:   (908) 996-0787


wgilles@my-dejanews.com wrote:
> 
> we are experiencing a problem with xilinx XC4010E FPGAs. So far the problem
> manifests itself as a stuck pin (Pin 126 of PQ208 package) to VCC. Two
> XC4010E fpgas with different date codes (FPGA #1 = PQ208CKM9809 A105288A 4I,
> FPGA #2 = PQ208CKJ9701 A105288A 4I) are programmed with the same image file.
> FPGA #2 works properly but FPGA #1 with 9809 Date code has the stuck pin
> problem. In the current design, Pin 126 is used as an external RAM data pin
> which constantly being used.
> 
> Per our xilinx rep, FPGA #2 has a smaller die than #1.  Presently, we are not
> sure whether if it is a timing problem with we are having with the latest
> die. Since the fpga design was farmed out to an outside firm and they are
> currently unavailable to aid us, we can't take a look at the timing
> simulation to see whether we are border line or not, or, bring out test pins
> to monitor the logics that affect pin 126.
Article: 15309
Subject: Re: Reconfigurable computing thesis on the web
From: Stephen Maudsley <Stephen.Maudsley@esgem.com>
Date: Thu, 18 Mar 1999 13:32:16 +0000
Links: << >>  << T >>  << A >>
Zik Saleeba wrote:

> I've put together an online version of my recent thesis on
> reconfigurable computing for people to view on the web or download as
> postscript.
>
> The idea behind the thesis was to create a new kind of computer
> architecture based around reconfigurable logic which was effective
> not only for the rarified set of problems current FPGA systems are
> applicable to - but could also be applied to the same sorts of
> problems as conventional general-purpose processors.
>
> Enjoy!
>
> http://www.cs.monash.edu.au/~zik/thesis.html
>
> ---------------------------------------------------------------------
> Abstract
>
> In the fast-paced field of computing new technologies appear, are
> developed and then become outdated all within a few years. The
> underlying architectural precepts on the other hand remain relatively
> constant. Modern CPUs use the same sequential execution model which
> has been with us since Von Neumann. The latest processors use
> performance features such as caching, deep pipelining and register
> scoreboarding which are really only minor adaptations of techniques
> which have been used for twenty years.
>
> Reconfigurable logic arrays give us the opportunity to embrace an
> entirely new approach to computing. The technology is still young so
> there is a great deal to be done before this new medium reaches the
> maturity of conventional processors. Current reconfigurable logic
> arrays are limited to specialised custom computing tasks and are not
> suitable for the wide variety of tasks which general purpose
> computers tackle.
>
> This thesis demonstrates that reconfigurable processors _do_ have the
> potential to entirely replace conventional processors. The
> Switchblade system described is a complete standalone general-purpose
> computer based entirely around a reconfigurable logic array. It lacks
> only hardware implementation and appropriate software to make it a
> realisable system.
>
> A significant aspect of this thesis is that it points the way to a
> major paradigm shift in the way computations can be performed.
> Instead of devising algorithms to run on and exploit a given computer
> architecture, an architecture is defined dynamically to perform the
> computation. While much work is still required the conceptual
> framework presented here paves the way for exciting future
> developments.
> ---------------------------------------------------------------------

There's a company in Oxford, UK doing this. I saw a demo of their product
a couple of years ago. The development environment is called Handel C. I
can route out an address if anyone's interested.
--
Stephen Maudsley mailto:Stephen.Maudsley@esgem.com
Esgem Limited: electronic product design http://www.esgem.com
Tel: +44-1453-521626 Mobile: +44-370-810991
Personal pages: http://www.esgem.com/people/Stephen.Maudsley




Article: 15310
Subject: Re: Xilinx Spartan configuration troubles
From: "Austin Franklin" <austin@dark9room.com>
Date: 18 Mar 1999 13:52:53 GMT
Links: << >>  << T >>  << A >>
Hi Peter,

The problem appeared to have been the MODE pin was floating.  Once a 10k
pullup was used, the part was able to be configured.  According to the spec
the MODE pin is supposed to have a weak pullup on it.  It also says in the
spec, specifically, that the MODE pins can be left unconnected.

Is the spec 'optimistic' saying it can be left unconnected?  Have other
people had problems leaving this pin unconnected?  Just curious what your
take is on this, since the solution appears to go completely contrary to
what the spec says one could do.

Austin

Article: 15311
Subject: Re: Clock multiplier
From: Sven Svensson <sveng@ce.chalmers.se>
Date: Thu, 18 Mar 1999 15:05:19 +0100
Links: << >>  << T >>  << A >>
Jitter is a problem in the actual application but I got some nice ideas from
the newsgroup sci.electronics.design based on a PLL solution.
Anyway, thanks for your interest.

Sven

Eli Keren wrote:

> Hi !
>
> What about jitter ? if you not mined from jitter them i think i can help
> you.
>
> Sven Svensson wrote:
>
> > Does anyone have a suggestion on how to make a clock multiplier
> > according to specs below:
> >
> > Fin: 10 Hz - 2000 Hz
> > Fout: Fin*100
> >
> > I would like to use a FPGA but other ideas are also appreciated.
> >
> > Sven



Article: 15312
Subject: Re: Clock multiplier
From: Sven Svensson <sveng@ce.chalmers.se>
Date: Thu, 18 Mar 1999 15:06:10 +0100
Links: << >>  << T >>  << A >>
Jitter is a problem in the actual application but I got some nice ideas from
the newsgroup sci.electronics.design based on a PLL solution.
Anyway, thanks for your interest.

Sven

Eli Keren wrote:

> Hi !
>
> What about jitter ? if you not mined from jitter them i think i can help
> you.
>
> Sven Svensson wrote:
>
> > Does anyone have a suggestion on how to make a clock multiplier
> > according to specs below:
> >
> > Fin: 10 Hz - 2000 Hz
> > Fout: Fin*100
> >
> > I would like to use a FPGA but other ideas are also appreciated.
> >
> > Sven



Article: 15313
Subject: Re: Xilinx Spartan configuration troubles
From: Ray Andraka <randraka@ids.net>
Date: Thu, 18 Mar 1999 09:10:07 -0500
Links: << >>  << T >>  << A >>
I don't like leaving signals like this to pull themselves up with a weak
internal pull-up.  It works fine in theory, but in practice there are too often
times when the weak pullup is not sufficient to overcome emi picked up on the
floating pin.  This is especially true if there is a PWB route to the pin.  If
there is a reason you need to let the pin go undriven, then at least put an
external pull-up on it to bolster the weak internal pullup.  Just good
engineering practice, nothing more.

Austin Franklin wrote:

> Hi Peter,
>
> The problem appeared to have been the MODE pin was floating.  Once a 10k
> pullup was used, the part was able to be configured.  According to the spec
> the MODE pin is supposed to have a weak pullup on it.  It also says in the
> spec, specifically, that the MODE pins can be left unconnected.
>
> Is the spec 'optimistic' saying it can be left unconnected?  Have other
> people had problems leaving this pin unconnected?  Just curious what your
> take is on this, since the solution appears to go completely contrary to
> what the spec says one could do.
>
> Austin



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 15314
Subject: Re: Xilinx Spartan configuration troubles
From: cyliax@cs.indiana.edu (Ingo Cyliax)
Date: 18 Mar 1999 14:32:33 GMT
Links: << >>  << T >>  << A >>
In article <01be7146$8ffcc770$207079c0@drt1>,
Austin Franklin <austin@dark9room.com> wrote:
>Hi Peter,
>
>The problem appeared to have been the MODE pin was floating.  Once a 10k
>pullup was used, the part was able to be configured.  According to the spec
>the MODE pin is supposed to have a weak pullup on it.  It also says in the
>spec, specifically, that the MODE pins can be left unconnected.
>
>Is the spec 'optimistic' saying it can be left unconnected?  Have other
>people had problems leaving this pin unconnected?  Just curious what your
>take is on this, since the solution appears to go completely contrary to
>what the spec says one could do.

I have relied on the internal pullups in the xc3000's and 4000's in
the past with OK success. However, I usually try to design in a 4.7K
or 10K pullup, whenever I can. Just to be on the safe side.

See ya, -ingo
-- 
/* Ingo Cyliax, cyliax@derivation.com, Tel/Fax: 812-333-4854/4852 */
Article: 15315
Subject: Re: How can I improve an adder?
From: "emanuel stiebler" <emu@ecubics.com>
Date: 18 Mar 1999 14:36:59 GMT
Links: << >>  << T >>  << A >>
Hi,

Brian Drummond <brian@shapes.demon.co.uk> wrote in article
<36f57d3a.179649091@news.demon.co.uk>...
> On Tue, 16 Mar 1999 01:08:18 GMT, tcoonan@mindspring.com (Thomas A.
> Coonan) wrote:
> 
> >Sounds like a school problem to me!
> >Go look for carry-lookahead adders in XILINX app notes on their WWW.
> >>I am currently trying to figure out how to improve an adder.  An n-bit
> >>adder can be constructed by cascading n full adders in series, with the
> >>carry into stage i, Ci, coming from the output of stage i-1. 
> 
> Yup, looks like homework.
> 
> But here's a goldmine.
> 
> http://www.iis.ee.ethz.ch/~zimmi/comp_arith_notes.ps.gz

Doesn't work. You sure this adress is right ?

cheers,
emanuel
Article: 15316
Subject: Re: Xilinx Spartan configuration troubles
From: "Austin Franklin" <austin@dark8room.com>
Date: 18 Mar 1999 15:08:09 GMT
Links: << >>  << T >>  << A >>
Ray,

I never leave these pins without a pullup or pulldown either.  I don't know
that I would call that 'good' engineering practice, more cautious
engineering practice.  Xilinx specifically says in the spec that you CAN
leave these pins unconnected.  How much of the spec are you going to
question, if this is the case?

Is the spec 'wrong' about this?  I don't know how they came up with their
claim that it can be left unconnected, and would like to hear the
'official' version...

Austin


Ray Andraka <randraka@ids.net> wrote in article
<36F1093F.4B0725FF@ids.net>...
> I don't like leaving signals like this to pull themselves up with a weak
> internal pull-up.  It works fine in theory, but in practice there are too
often
> times when the weak pullup is not sufficient to overcome emi picked up on
the
> floating pin.  This is especially true if there is a PWB route to the
pin.  If
> there is a reason you need to let the pin go undriven, then at least put
an
> external pull-up on it to bolster the weak internal pullup.  Just good
> engineering practice, nothing more.
> 
> Austin Franklin wrote:
> 
> > Hi Peter,
> >
> > The problem appeared to have been the MODE pin was floating.  Once a
10k
> > pullup was used, the part was able to be configured.  According to the
spec
> > the MODE pin is supposed to have a weak pullup on it.  It also says in
the
> > spec, specifically, that the MODE pins can be left unconnected.
> >
> > Is the spec 'optimistic' saying it can be left unconnected?  Have other
> > people had problems leaving this pin unconnected?  Just curious what
your
> > take is on this, since the solution appears to go completely contrary
to
> > what the spec says one could do.
> >
> > Austin

Article: 15317
Subject: Re: Reconfigurable computing thesis on the web
From: Sylvain Giroudon <giroudon@NOSPAM-montrouge.tt.slb.com>
Date: Thu, 18 Mar 1999 17:09:13 +0100
Links: << >>  << T >>  << A >>
I red http://www.starbridgesystem.com/Pages/about.html recently.
Is this thesis in the same domain/goal as what the guys
from StarBridge are doing?

Stephen Maudsley wrote:
> 
> Zik Saleeba wrote:
> 
> > I've put together an online version of my recent thesis on
> > reconfigurable computing for people to view on the web or download as
> > postscript.
> >
> > The idea behind the thesis was to create a new kind of computer
> > architecture based around reconfigurable logic which was effective
> > not only for the rarified set of problems current FPGA systems are
> > applicable to - but could also be applied to the same sorts of
> > problems as conventional general-purpose processors.
> >
> > Enjoy!
> >
> > http://www.cs.monash.edu.au/~zik/thesis.html
> >
> > ---------------------------------------------------------------------
> > Abstract
> >
> > In the fast-paced field of computing new technologies appear, are
> > developed and then become outdated all within a few years. The
> > underlying architectural precepts on the other hand remain relatively
> > constant. Modern CPUs use the same sequential execution model which
> > has been with us since Von Neumann. The latest processors use
> > performance features such as caching, deep pipelining and register
> > scoreboarding which are really only minor adaptations of techniques
> > which have been used for twenty years.
> >
> > Reconfigurable logic arrays give us the opportunity to embrace an
> > entirely new approach to computing. The technology is still young so
> > there is a great deal to be done before this new medium reaches the
> > maturity of conventional processors. Current reconfigurable logic
> > arrays are limited to specialised custom computing tasks and are not
> > suitable for the wide variety of tasks which general purpose
> > computers tackle.
> >
> > This thesis demonstrates that reconfigurable processors _do_ have the
> > potential to entirely replace conventional processors. The
> > Switchblade system described is a complete standalone general-purpose
> > computer based entirely around a reconfigurable logic array. It lacks
> > only hardware implementation and appropriate software to make it a
> > realisable system.
> >
> > A significant aspect of this thesis is that it points the way to a
> > major paradigm shift in the way computations can be performed.
> > Instead of devising algorithms to run on and exploit a given computer
> > architecture, an architecture is defined dynamically to perform the
> > computation. While much work is still required the conceptual
> > framework presented here paves the way for exciting future
> > developments.
> > ---------------------------------------------------------------------
> 
> There's a company in Oxford, UK doing this. I saw a demo of their product
> a couple of years ago. The development environment is called Handel C. I
> can route out an address if anyone's interested.
> --
> Stephen Maudsley mailto:Stephen.Maudsley@esgem.com
> Esgem Limited: electronic product design http://www.esgem.com
> Tel: +44-1453-521626 Mobile: +44-370-810991
> Personal pages: http://www.esgem.com/people/Stephen.Maudsley

-- 
Sylvain GIROUDON - mailto:giroudon@montrouge.tt.slb.com
SCHLUMBERGER Systems, R&D Telecom
50, avenue Jean Jaures
F-92542 MONTROUGE
FRANCE
Article: 15318
Subject: Re: Reconfigurable computing thesis on the web
From: Sylvain Giroudon <giroudon@NOSPAM-montrouge.tt.slb.com>
Date: Thu, 18 Mar 1999 17:13:22 +0100
Links: << >>  << T >>  << A >>
Sylvain Giroudon wrote:
> 
> I red http://www.starbridgesystem.com/Pages/about.html recently.
> Is this thesis in the same domain/goal as what the guys
> from StarBridge are doing?
> 

Sorry, I mean http://www.starbridgesystems.com/Pages/about.html

--
Sylvain GIROUDON - mailto:giroudon@montrouge.tt.slb.com
SCHLUMBERGER Systems, R&D Telecom
50, avenue Jean Jaures
F-92542 MONTROUGE
FRANCE
Article: 15319
Subject: Re: Allowed logic functions in Virtex LE
From: arast@inficom.com (Alex Rast)
Date: Thu, 18 Mar 1999 20:10:40 GMT
Links: << >>  << T >>  << A >>
In article <7cpko5$ve$1@feynman.xsj.xilinx.com>, mcgett@feynman.xsj.xilinx.com (Ed McGettigan) wrote:
>In article <36f015d9@news.nwlink.com>, Alex Rast <arast@inficom.com> wrote:
>>I've been looking through the details of a Virtex slice (1/2 of a CLB) using 
>>the editblock functionality of EPIC. I've run across a state that I want to 
>>verify cannot exist. At least as far as I can tell, provided you're not using 
>>the BY input, it's impossible to have Y=1, XB<>YB. That is to say, the 
>>following logic expression holds:
>>
>>Y*(XB@YB) = 0
>>
>
>This is nonsensical question since Y, XB and YB are all outputs.  
>
>It is highly irregular to think of outputs as a "state" of a slice,
..

Many apologies if the terminology I used offends. I didn't mean it as a 
precise, rigidly-defined term with an accepted, standard meaning but rather as 
simply a word to convey a concept. How might you phrase the same question 
incorporating more acceptable terminology?

>
>But since you asked, the above "equation" is not true.  It is possible to 
>get the following output values at the same time from the same slice,
>Y=1, YB=0, XB=1 which would give you a 1 in the above "equation". And you
>can do this without using the BY input.  

Yes, I actually noticed that I posed the question based on an earlier series 
of notes. I noted the same condition you outlined. However, I do still find 
one output combination that *does* seem to be impossible, namely YB=1, Y=1, 
XB=0. Does this look correct?

Thanks, BTW, for quickly pointing out the (rather glaring) error. Part of the 
reason I posted was for a quick sanity check on my thinking. I'd gotten so 
wound up in trying to think of creative ways of generating certain output 
combinations that I knew my head wasn't completely clear. I wanted to bounce 
my train of thought off an external observer to verify.

>Ed McGettigan

Alex Rast
arast@inficom.com
Article: 15320
Subject: Re: How can I improve an adder?
From: "Otto Bruggeman" <obruggie@worldonline.nl>
Date: Thu, 18 Mar 1999 21:28:08 +0100
Links: << >>  << T >>  << A >>

Lisa Nangel wrote in message <36EDAAE6.88558059@sju.edu>...
>I am currently trying to figure out how to improve an adder.  An n-bit
>adder can be constructed by cascading n full adders in series, with the
>carry into stage i, Ci, coming from the output of stage i-1.  The carry
>into stage 0, C0, is 0.  If each stage takes T nsec to produce its sum
>and carry, the carry into stage i will not be valid until iT nsec after
>the start of the addition.  For large n the time required for the carry
>to ripple through to the high-order stage may be unacceotably long.  I
>want to design an adder that works faster.  I believe that it has
>something to do with Ci being able to be expressed in terms of the
>operand bits Ai-1 and Bi-1 as wekk as the carry Ci-1.  Using this
>relationship it is possible to express Ci as a function of the inputs to
>stages 0 to i-1, so all the carries can be generated simultaneously.
>Can anyone help to improve the adder?

Lisa,

I have a pdf about Look ahead carry generators. If you want i can mail it to
you.
You can increase it up to as many bits as possible. The texts are in dutch
but you should
be able to read the formulas and understand them. There are a lot of
schematics in here, so that shouldn't be a problem. It's 800 kB in size.

Otto.


Article: 15321
Subject: Re: How can I improve an adder?
From: Lasse Langwadt Christensen <fuz@kom.auc.dk>
Date: Thu, 18 Mar 1999 20:37:49 GMT
Links: << >>  << T >>  << A >>
emanuel stiebler wrote:
> 
> Hi,
> 
> Brian Drummond <brian@shapes.demon.co.uk> wrote in article
> <36f57d3a.179649091@news.demon.co.uk>...
> > On Tue, 16 Mar 1999 01:08:18 GMT, tcoonan@mindspring.com (Thomas A.
> > Coonan) wrote:
> >
> > >Sounds like a school problem to me!
> > >Go look for carry-lookahead adders in XILINX app notes on their WWW.
> > >>I am currently trying to figure out how to improve an adder.  An n-bit
> > >>adder can be constructed by cascading n full adders in series, with the
> > >>carry into stage i, Ci, coming from the output of stage i-1.
> >
> > Yup, looks like homework.
> >
> > But here's a goldmine.
> >
> > http://www.iis.ee.ethz.ch/~zimmi/comp_arith_notes.ps.gz
> 
> Doesn't work. You sure this adress is right ?
> 
> cheers,
> emanuel

I you take the "front door" http://www.iis.ee.ethz.ch/~zimmi/ 
and look around you sse the correct url is: 

http://www.iis.ee.ethz.ch/~zimmi/publications/comp_arith_notes.ps.gz

 
--L2C                 
--___--_-_-_-____--_-_--__---_-_--__---_-_-_-__--_----
Lasse Langwadt Christensen, MSEE (to be in 1999) 
Aalborg University, Department of communication tech.    
Applied Signal Processing and Implementation (ASPI)      
http://www.kom.auc.dk/~fuz , mailto:langwadt@ieee.org
Article: 15322
Subject: Re: Reconfigurable computing thesis on the web
From: zik@zikzak.net (Zik Saleeba)
Date: 19 Mar 1999 08:57:10 +1100
Links: << >>  << T >>  << A >>
Stephen Maudsley <Stephen.Maudsley@esgem.com> writes:

>There's a company in Oxford, UK doing this. I saw a demo of their product
>a couple of years ago. The development environment is called Handel C. I
>can route out an address if anyone's interested.

As far as I'm aware all of the existing attempts at this are just
using conventional off-the-shelf FPGAs. My hardware architecture is
specifically designed to provide support for a full general-purpose
virtual-logic computing environment based around reconfigurable logic
elements. It's rather a big step from FPGAs :)

Zik
Article: 15323
Subject: Re: Want to learn about FPGA.
From: "Luis de Funes" <fuzzy8888@hotmail.com>
Date: Thu, 18 Mar 1999 23:03:55 +0100
Links: << >>  << T >>  << A >>
Damiano, look here http://www.optimagic.com/lowcost.html

Ciao

Luigi

>NO-SPAM damiano wrote:
>
>> Hi all,
>>
>> I just ended my studies to become an electronic engineer and I'd like
>> to start a few projects.
>> This is intended for learning purposes.
>> I heard that FPGA can be managed with a PC and a few hunred dollars,
>> is it true?
>> What can I do using FPGA at the moment?
>>
>> Damiano Rullo
>> Trezzano S/N
>> Milan, Italy
>> http://members.it.tripod.de/Damianoux/index.html
>> mailto: dmn@cheerful.com
>> mailto: damiano@mclink.it



Article: 15324
Subject: Re: Xilinx Spartan configuration troubles
From: Ray Andraka <randraka@ids.net>
Date: Thu, 18 Mar 1999 17:10:35 -0500
Links: << >>  << T >>  << A >>
You can leave them unconnected, but my point is that those inputs are a fairly
high impedance so it doesn't take much stray signal to tickle them.  In cases
where you have an undriven PWB route to the mode pins, you can quickly get
enough induced signal to cause the inputs to see transitions.  If you are
leaving those pins unconnected, then don't hang a wire on them and you should
be OK as long as you're not sitting a few feet from a high power transmitter.

Austin Franklin wrote:

> Ray,
>
> I never leave these pins without a pullup or pulldown either.  I don't know
> that I would call that 'good' engineering practice, more cautious
> engineering practice.  Xilinx specifically says in the spec that you CAN
> leave these pins unconnected.  How much of the spec are you going to
> question, if this is the case?
>
> Is the spec 'wrong' about this?  I don't know how they came up with their
> claim that it can be left unconnected, and would like to hear the
> 'official' version...

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search