Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi, I am looking for a self study book above the basic introductory level of digital logic design. Looking into what text books are used for senior level courses at Universities I found the two books: "Computer Organization and Design" by David A. Patterson, John L. Hennessy "Structured Computer Organization" by Andrew S. Tanenbaum http://www.amazon.com/Computer-Organization-Design-Interface-Architecture/dp/1558606041/sr=8-3/qid=1169645535/ref=pd_bbs_sr_3/103-6992646-3335035?ie=UTF8&s=books http://www.amazon.com/Structured-Computer-Organization-Andrew-Tanenbaum/dp/0131485210/sr=8-3/qid=1169645623/ref=sr_1_3/103-6992646-3335035?ie=UTF8&s=books I was reading the comments on amazon.com and it sounds like the Patterson/Hennessy book is THE book to read for Computer architecture, but has a lot of editorial flaws. On the other hand, one comment about the Tannenbaum book sounds like it is better written to suite as an introductory than the Patterson/Hennessy one. Unfortunately there is only a brief table of content available for the Tannenbaum book to see more in depth what is covered in it. What I am looking for is an easy to read book, with plenty of exercises to get me some hands on experience in the design of digital logic. I would appreciate any recommendation about which book is better for self study. Thanks for your help. Cheers, GuenterArticle: 114801
"MM" <mbmsv@yahoo.com> wrote in message
news:51oh3gF1l9k1mU1@mid.individual.net...
> 1. It seems that Xilinx uses sysgen internally to develop their new cores.
Well... that's not really true. Sure, there are certain pieces of DSP IP
that are produced using System Generator, mostly as part of application
notes / reference designs. But the majority of cores (i.e. generic,
parameterizable, optimized, documented, extensively verified IP blocks) are
delivered through coregen.
We aim to make IP available in the most convenient form possible. Obviously
not everyone has or wants the System Generator tool, and therefore we
continue to provide IP for users who have chosen a standard HDL design flow.
In any case, a block designed in Sysgen can be exported and incorporated
into a larger design done in HDL, and a block design in HDL can similarly be
incorporated into a Sysgen design.
Your other two points are valid though (hope I don't get into any trouble
for saying that! :))
Cheers,
-Ben-
Article: 114802On Jan 24, 1:12 am, "Symon" <symon_bre...@hotmail.com> wrote: > Google Subversion. And if you use Windows, Google Tortoise. > HTH, Syms. > p.s. This chap recommends it on his blog.http://www.cambriandesign.com/ I nice pair with subversion is trac: http://trac.edgewall.org/ It provides a web view interface to the subversion repository with a ticket system and wiki. The trac page itself is using trac, so you can get from it a feeling what you get. Using the "Timeline" for example will show you what commits has been done to the repository or tickets beeing created or finished. "Browse Source" e.g. allows to browse the repository via the web interface. Cheers, GuenterArticle: 114803
jbnote, Sorry, but we do not discuss how our parts work. If you are curious, you may go to http://www.uspto.gov and search for patents on interconnect for FPGAs. As well, the view in FPGA Editor is a fiction: merely a convenience for the user to visualize the internal workings. FPGA Editor is a software representation - there is no hardware construction details that you should assume are there (they are not). The "pip" or programmable interconnect point, in fact, does not exist in reality. AustinArticle: 114804
Hi,
So, my problem :
I have a netlist of a module. I can't change it, it comes from a big
manufacturer and they have no interest whatsoever in really helping us
especially since we're not really paying customer but more "academic
researcher" ...
This takes a stream of continous data, and they have to be continuous,
1 each clock (there are pauses but very far apart) and they don't have
"enable" on their registers. Now, the rest of my chain only can process
2 data in 3 cycles ...
So an idea would be to "block" the rising edge 1 cycle every 3 cycle,
maybe using a bufgmux ? Also, I'm considering using the "divide clock
by 1.5" circuit by Peter Alfe, and use some sort of clock domain
crossing technique to cross my 2 data back and forth.
Any suggestion on this ?
FYI: I'm working in a virtex4 FPGA.
Thanks for any insight ...
Sylvain
Article: 114805"Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com> wrote in message news:1169652537.347421.148260@h3g2000cwc.googlegroups.com... > > This takes a stream of continous data, and they have to be continuous, > 1 each clock (there are pauses but very far apart) and they don't have > "enable" on their registers. Now, the rest of my chain only can process > 2 data in 3 cycles ... > Hi Sylvain, If the netlist is in EDIF format, I believe Synplify PRO will 'fix' gated clocks for you. This might solve your problem. HTH, Syms. http://syndicated.synplicity.com/Q405/tips.htmlArticle: 114806
Okay, here are the first steps to hopefully solve the problem. Thanks to the Xilinx Webcase Specialists 1. Download the zip-file ftp://ftp.xilinx.com/pub/utilities/fpga/install_cable.zip 2. Overwrite inf file. 3. ran batch file (according to readme.pdf) 4. Immediatley new device manager changed from "unknow device" to "Xilinx" 5. Followed three times "New Hardware found" (manually triggerd, because no wizard appeared). 6. "Programming cables cables > Xilinx Platform Cable USB" in device manger 7. Led on cable box changed to green. Everything seems to be set up properly now. But impact and ChipScopePro still cant find the cable. But maybe the new issues are cause by the fact that I work remote on my server. ChipscopePro -----------snip---------------------------------------- INFO: Connecting to cable (Usb Port - USB22). INFO: Invalid OS minor version = 2. INFO: Cable connection failed. -----------snap------------------------------------ impact ---------snip------------------------------------------- Checking cable driver. Driver windrvr6.sys version = 7.0.0.0.Cable connection failed. Connecting to cable (Usb Port - USB21). Invalid OS minor version = 2. Cable connection failed. ------snap------------------------------------------ Bye HelmutArticle: 114807
Thanks for talking to us Ben! >> 1. It seems that Xilinx uses sysgen internally to develop their new >> cores. > > Well... that's not really true. Sure, there are certain pieces of DSP IP > that are produced using System Generator, mostly as part of application > notes / reference designs. But the majority of cores (i.e. generic, > parameterizable, optimized, documented, extensively verified IP blocks) > are delivered through coregen. This is good to hear. Can I ask you then to move the DUC into coregen. It would be also very nice if one could choose complex input for the DDC and complex output for the DUC, as well as multichannel optimization. > In any case, a block designed in Sysgen can be exported and incorporated > into a larger design done in HDL, Yes, but one needs to have Sysgen for that... Thanks, /MikhailArticle: 114808
Those aren't digital logic books, those are computer architecture books. For my first course in logic design I used "Fundamentals of Logic Design" by Roth. For a mix of logic design and HDL, "Advanced Digital Design with the Verilog HDL" by Ciletti is quite good, but more advanced. I personally wanted to read "Digital Design: Principles and Practices" by Wakerly, which got good reviews but may be on the advanced side of things. ---Matthew Hicks > Hi, > > I am looking for a self study book above the basic introductory level > of digital logic design. Looking into what text books are used for > senior level courses at Universities I found the two books: > > "Computer Organization and Design" by David A. Patterson, John L. > Hennessy > "Structured Computer Organization" by Andrew S. Tanenbaum > http://www.amazon.com/Computer-Organization-Design-Interface-Architect > ure/dp/1558606041/sr=8-3/qid=1169645535/ref=pd_bbs_sr_3/103-6992646-33 > 35035?ie=UTF8&s=books > > http://www.amazon.com/Structured-Computer-Organization-Andrew-Tanenbau > m/dp/0131485210/sr=8-3/qid=1169645623/ref=sr_1_3/103-6992646-3335035?i > e=UTF8&s=books > > I was reading the comments on amazon.com and it sounds like the > Patterson/Hennessy book is THE book to read for Computer architecture, > but has a lot of editorial flaws. On the other hand, one comment about > the Tannenbaum book sounds like it is better written to suite as an > introductory than the Patterson/Hennessy one. Unfortunately there is > only a brief table of content available for the Tannenbaum book to see > more in depth what is covered in it. > > What I am looking for is an easy to read book, with plenty of > exercises to get me some hands on experience in the design of digital > logic. > > I would appreciate any recommendation about which book is better for > self study. > > Thanks for your help. > > Cheers, > > Guenter >Article: 114809
"MM" <mbmsv@yahoo.com> writes: > Since nobody wants to answer... I don't have any practical experience with > sysgen, but here is what I know: > I wrote of my experience a while ago: http://groups.google.co.uk/group/comp.lang.vhdl/browse_thread/thread/9413e46f42c3ec64/3b3204ff45804367?lnk=st&q=martin.j.thompson%40trw.com+sysgen&rnum=3&hl=en#3b3204ff45804367 I guess there's more blocks in there now, and the integration with AccellDSP might be of benefit, but we didn;t feel much benefit from it on the project we were doing. <snip> > 3. Sysgen + Simulink cost a lot of money. > Sysgen isn't *that* expensive if you are already Matlab/Simulink inclined. -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 114810
I have previous experience with microchip pics, do I need a 0.1uF bypass cap for the +/- pins?Article: 114811
imity wrote: > I have previous experience with microchip pics, do I need a > 0.1uF bypass cap for the +/- pins? > > Every chip, everywhere should have bypass caps on all power pins. Period. If the manufacturer says not to do it, then you should comply, but reluctantly (re: Microchip Vpp line, which is driven by the programmer and Must Have Fast Edges). If it has more than one power pin, it should have more than one cap. The rule of thumb is to have one cap per power pin. Extras never hurt. If the chip designers were paying attention you'll find power and ground pins in pairs; you should lay out your board so you have short runs to the caps. If the chip designers were _really_ paying attention you'll find a section of the data sheet that specifies how the bypass caps should be laid out. Follow it. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/ "Applied Control Theory for Embedded Systems" came out in April. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 114812
Wow, that's really interesting, thanks. On Jan 24, 4:59 pm, "Symon" <symon_bre...@hotmail.com> wrote: > "Sylvain Munaut <Some...@SomeDomain.com>" <246...@gmail.com> wrote in > messagenews:1169652537.347421.148260@h3g2000cwc.googlegroups.com... > > > This takes a stream of continous data, and they have to be continuous, > > 1 each clock (there are pauses but very far apart) and they don't have > > "enable" on their registers. Now, the rest of my chain only can process > > 2 data in 3 cycles ...Hi Sylvain, > If the netlist is in EDIF format, I believe Synplify PRO will 'fix' gated > clocks for you. This might solve your problem. > HTH, Syms.http://syndicated.synplicity.com/Q405/tips.htmlArticle: 114813
"MM" <mbmsv@yahoo.com> wrote in message
news:51perqF1lit5kU1@mid.individual.net...
> Thanks for talking to us Ben!
You are welcome, although I am probably not the most useful person to talk
to about this particular subject :-)
>> But the majority of cores (i.e. generic, parameterizable, optimized,
>> documented, extensively verified IP blocks) are delivered through
>> coregen.
> This is good to hear. Can I ask you then to move the DUC into coregen. It
> would be also very nice if one could choose complex input for the DDC and
> complex output for the DUC, as well as multichannel optimization.
I should certainly like these up/down converter blocks available outside of
the SysGen environment too, although I certainly don't have much say in the
matter I'm afraid. I'm happy to pass requests on to the right people. If
there is a certain critical mass of people who want a particular piece of IP
in a particular format, then obviously we'll do our best to provide that.
>> In any case, a block designed in Sysgen can be exported and incorporated
>> into a larger design done in HDL,
> Yes, but one needs to have Sysgen for that...
Well, mostly true I suppose. Although if you buy the IP from Xilinx I'm sure
you would be able to get netlists that would work without System
Generator...
Cheers,
-Ben-
Article: 114814doug, This thread is not being ignored. I will comment when I have something useful to add to it. Trashing software is not uncommon. Especially when that software has become quite common (over 300,000 "seats" in use, not including Xilinx, Xilinx FAEs). I have a rule, which I call the "rule of tens." Sell ten of something, find all the bugs, fix them, and then sell some more. At or about the shipment of the 100th item, a bug is found, that is so bad, that you hear "how stupid could you be!" You fix that bug, and then go on. Again, at the 1000th ship date, another "totally fatal" bug happens, and again is heard "how..." I have seen this personally up to shipment of the 100,000th item (once upon a time). I have no doubts that there are bugs (I use the software, too). I also report my bugs, and I see the lists of "correction requests" which get found, and fixed. Generally speaking, we are also dependent upon others (Microsoft, Red Hat, Sun), so a "memory leak" may be some weird combination of an operating system, our code, and perhaps even Java. Add to that Dell, HP, and so on, with different 'compatible hardware' and it gets pretty tough. I offer no excuses: software quality is of the utmost importance. Please continue the thread, AustinArticle: 114815
"Sean Durkin" <news_jan07@durkin.de> wrote in message news:51oelhF1kmsn8U1@mid.individual.net... > I think the main problem is that Xilinx releases new ISE versions in a > predefined schedule Text clipped. > This approach results in the software department always being busy > integrating new features so they can make the fixed deadline for the new > software release Actually, for the 9.1i release, feature freeze was in June 2006 and the release to manufacturing was in December. We spend about 6 months fixing bugs and improving quality. > > Sometimes you get the idea that a new ISE is not just a new software > version, but an entirely new product. Maybe it was just quicker to start > from scratch than to fix what was already there. And then you get > effects like bugs that were fixed in 7.1 re-appearing in 8.1 and things > like that... Yes, 7.1i had a new database and 8.1i had a new ProjNav GUI. The database was created in 1990 and needed to be rewritten and so did the GUI. > > We had a Xilinx FAE here in late November, introducing us to Virtex-5, > and when the topic of bugs in ISE came up, he actually said that we > needn't bother sending in bug reports now, since the entire software > department at Xilinx was now scrambling to make the deadline for the 9.1 > release and nothing would really happen until after that anyway. And bug > reports for ISE8.2 were useless anyway, since all the work is going into > 9.1 now... While it's true that the software team was working on 9.1i, bug reports for 8.2i would only be useless if the bug was fixed in 9.1i. Even getting duplicate bug reports is useful because it raises the priority of fixing that bug. > > What is it with that regular release cycle? It's not as simple as saying we will release when its ready because of other dependencies. We need to make sure all of our other software products (ChipScope, PlanAhead, System Generator, EDK, etc.), all of our IP, and 3rd party tools all work together. Defining a release date and sticking to that date is the best way to accomplish this. So instead, we define a feature freeze date. If a feature can't be done by that date, it gets pushed to the next release. > > Partial reconfiguration is another example. I've been fiddling around > with this since ISE4, gave up with ISE7, since I always ran into some > "FATAL_ERROR"-thingies that "will be fixed in the next service pack" or > "will be fixed in the next ISE release", but never were. Now with > software radio being a high-volume-application, they seem to have fixed > it, but only in specially patched ISE8-versions you have to get through > your FAE. I agree with all of this. To be honest, no customers told us they were using partial reconfig in ISE 4 - 7, so we did not make it a priority. Now it is, and we have a lot of customers using it. One final note. We do take quality and these posts seriously. In 8.1 and 8.2, we allowed features into the release after feature freeze and quality suffered. That has resulted in a quality initiative that I expect will have a dramatic effect over the next year or two. Don't be shy about reporting bugs to us and don't complain about bugs not being fixed if you don't report them. Steve Lass One of those Marketing guys.Article: 114816
Doug, If you have a case number, I can track it down and try to get you an answer. Steve "doug" <doug@doug> wrote in message news:12rf4t0tknpph59@corp.supernews.com... > jbnote wrote: >>>Memory leaks come from sloppy programmers. Not fixing memory leaks >>>comes from lazy or incompetent programmers. >> >> >> Even incompetent programmers can manage this. The use of valgrind >> [http://www.valgrind.org] will pinpoint memory leaks right to the line >> where the allocation was made. It runs on unmodified software. This >> would be, oh, one hour work maximum if you have the source. >> >> JB >> > So, Austin and the other Xilinx people that monitor the board-- > Why is Xilinx not willing to take the hour to fix a show stopper > problem that has existed for at least a year in at least NINE > versions of ISE? > > There have been 7 sevice packs issued which still have this > problem. This means it is a management decision to not fix > things. The fact that the service pack and the release came > at the same time was a very bad sign. > > On the other hand, could I get a job as a xilinx programmer, > or better yet, as a manager. I have always had bosses who > exptected me to do things correctly. This would be a nice > change. > >Article: 114817
Martin, Thanks, that was what i was looking for. I know about the employer issues, as there are many things i cannot disclose here as well. But we can certainly build on what you provided. Again, thanks!! I'm going to take this weekend and compile all this info and put it on my site, including some scripts. If all goes well, www.hackthebox.org/xilinx will have excerps and links from this theard and a few others. Right now my site is down (harddrive blewup) and i have had only a few hours to spend reloading the system. Umm, I think my php scripts are still broken so if you get there and see errors, please try again next week. Hopfully my raid system will prevent future single harddrive issues. Thanks all for the input!!!!!! I'm going to continue to bang my head on my desk untill i get the scripting thing down. At least at home i have a Quad Xeon with 2GB of memory running linux to run tests on. I will be checking back thoughout the next few days (or as longs as this thread lives). --Brian On Jan 24, 12:15 pm, doug <doug@doug> wrote: > jbnote wrote: > >>Memory leaks come from sloppy programmers. Not fixing memory leaks > >>comes from lazy or incompetent programmers. > > > Even incompetent programmers can manage this. The use of valgrind > > [http://www.valgrind.org] will pinpoint memory leaks right to the line > > where the allocation was made. It runs on unmodified software. This > > would be, oh, one hour work maximum if you have the source. > > > JBSo, Austin and the other Xilinx people that monitor the board-- > Why is Xilinx not willing to take the hour to fix a show stopper > problem that has existed for at least a year in at least NINE > versions of ISE? > > There have been 7 sevice packs issued which still have this > problem. This means it is a management decision to not fix > things. The fact that the service pack and the release came > at the same time was a very bad sign. > > On the other hand, could I get a job as a xilinx programmer, > or better yet, as a manager. I have always had bosses who > exptected me to do things correctly. This would be a nice > change.Article: 114818
"bgshea" <bgshea@gmail.com> writes: > I'm looking for POSITIVE feedback on Xilinx ISE. I wrote: > As compared to what? > Xilinx ISE is the best development software for Xilinx FPGAs that > I've ever used. Martin Thompson <martin.j.thompson@trw.com> writes: > If by ISE we mean the GUI (as I think we do) then I disagree... > > The best development environment I have ever used for Xilinx devices > is Emacs (with vhdl-mode) and a command-line build script :-) I do my editing in Emacs, but I despise vhdl-mode. I normally use the GUI for everything but editing. EricArticle: 114819
jbnote wrote: >>Memory leaks come from sloppy programmers. Not fixing memory leaks >>comes from lazy or incompetent programmers. > > > Even incompetent programmers can manage this. The use of valgrind > [http://www.valgrind.org] will pinpoint memory leaks right to the line > where the allocation was made. It runs on unmodified software. This > would be, oh, one hour work maximum if you have the source. > > JB > So, Austin and the other Xilinx people that monitor the board-- Why is Xilinx not willing to take the hour to fix a show stopper problem that has existed for at least a year in at least NINE versions of ISE? There have been 7 sevice packs issued which still have this problem. This means it is a management decision to not fix things. The fact that the service pack and the release came at the same time was a very bad sign. On the other hand, could I get a job as a xilinx programmer, or better yet, as a manager. I have always had bosses who exptected me to do things correctly. This would be a nice change.Article: 114820
I am doing some embedded video processing, where I store an incoming frame of video, then based on some calculations in another part of the system, I warp that buffered frame of video. Now when the frame goes into the buffer (an off-FPGA SDRAM chip), it is simply written in one pixel at a time in row major ordering. The problem with this is that I will not be accessing it in this way. I may want to do some arbitrary image rotation. This means the first pixel I want to access is not the first one I put in the buffer, It might actually be the last one in the buffer. If I am doing full page reads, or even burst reads, I will get a bunch of pixels that I will not need to determine the output pixel value. If i just do single reads, this waists a bunch of clock cycles setting up the SDRAM, telling it which row to activate and which column to read from. After the read is done, you then have to issue the precharge command to close the row. There is a high degree of inefficiency to this. It takes 5, maybe 10 clock cycles just to retrieve one pixel value. Does anyone know a good way to organize a frame buffer to be more friendly (and more optimal) to nonsequential access (like the kind we might need if we wanted to warp the input image via some linear/nonlinear transformation)?Article: 114821
Hi, I am trying to do my own vga driver for ML403 board. I have done the same vga driver for other boards, so I only have to change the FPGA pins labels. I was looking for the pins in ML403 board in the schematics provided by xilinx and when I tried to map my design I got: ERROR:MapLib:30 - LOC constraint M24 on PIN_M24 is invalid: No such site on the ... ERROR:MapLib:30 - LOC constraint L23 on PIN_L23 is invalid: No such site on the ... I understand that this pins labels are invalid in the FPGA of ML403 board, and when I look for the pins in the Virtex IV datasheet I see that this both pins are not connected in the xc4vfx12ff668-10 FPGA. So I think that the information provided by is wrong, anybody know how can I get the right pins? The BLUEpins, GREENpins, REDpins, VSYNCpin, HSYNCpin and CLOCKpin are right the wrong are: BLANKpin "M24" SYNCpin "L23" Thanks in advance Gerardo SosaArticle: 114822
pbFJKD@ludd.invalid wrote: >Ben Jackson <ben@ben.com> wrote: > > >>On 2007-01-23, stephen.craven@gmail.com <stephen.craven@gmail.com> wrote: >> >> >>>Does anyone know if it is possible to permanently harm a Xilinx FPGA >>>internally through a bad (accidental or malicious) bitstream? >>> >>> > > > >>One totally unobvious one is: >> >> > > > >>http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=22471 >> >> > > > >>Running without an MGT hooked up for 400 hours might cause it to permanently >>fail! >> >> > >What's MGT? > > > Multi-Gigabit Transceiver? http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=20816 JonArticle: 114823
I am using a virtex 4. I have an clock input, and another input for bitstream. What is the best way to align the rising edge of a bit to the rising edge of a clock? It needs very quick. Currently I am using IDELAY to shift the data until I notice no bit errors, but it is taking up to 500ms.Article: 114824
On 2007-01-24, <imity> <> wrote: > I have previous experience with microchip pics, do I need a > 0.1uF bypass cap for the +/- pins? If you don't, I doubt you will even be able to program it. The charge pump for the flash programming will fail. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z