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Hi, everyone. I want to use bank 4 and bank 5 of Xilinx spartan device XC3S1500-4fg676 for LVDS_25 interface. I have four questions about this. 1) I wired positive polarity signals to xxP pins and negative polarity signals to xxN pins. And do some split termination on bank 4 and 5. Is this enough to using LVDS? 2) If I want to use LVDS_25 (not LVDS_25_DCI), is there no need to concern about DCI split termination on bank 4 and bank 5? 3) If the answer of question 2 is negative, then how can I choose the impedance-matching resistor on DCI split termination? I will connect some kind of cameras which uses LVDS interface. 4) I wonder this last question seems stupid. Why we need DCI and what is the different between LVDS_25 and LVDS_25_DCI? Please give some guides. Thanks a lot.Article: 90326
Hi, all. I'm newbie in circuits, and I have a silly question. Suppose that one FPGA device has about 100 Vcc pins (including VCCINT, VCCO, VCCAUX) and 80 GND pins. Then how many decoupling capacistors are needed for this IC? How can I decide that quantity? And can I have any reference design about Xilinx FPGA and its configuration PROM? I already read datasheet and user guide about that but it is rather difficult for me. So I cannot sure my design is right or wrong. If there is any reference, let me know that please. Thank you for interested with my post.Article: 90327
This, and more: http://www.xilinx.com/products/design_resources/power_central/ Austin river064 wrote: > Hi, all. > > I'm newbie in circuits, > and I have a silly question. > > Suppose that one FPGA device has about 100 Vcc pins > (including VCCINT, VCCO, VCCAUX) and 80 GND pins. > Then how many decoupling capacistors are needed > for this IC? How can I decide that quantity? > > And can I have any reference design about > Xilinx FPGA and its configuration PROM? > I already read datasheet and user guide about that > but it is rather difficult for me. > So I cannot sure my design is right or wrong. > > If there is any reference, let me know that please. > Thank you for interested with my post. >Article: 90328
If my memory isn't faulty have a look at Xilinx application note XAPP623 for a full treatment of this subject. Otherwise the Xpower tool usually gives some recommendations about sizes and numbers of. Usually it is very difficult to achieve the reccomended numbers even if you use capacitor arrays like we do in our products. Genarally a pyramid of values/size is recommended. John Adair Enterpoint Ltd. - Home of Raggedstone1. The Cheap Spartan3 Development Board. http://www.enterpoint.co.uk "river064" <river064@gmail.com> wrote in message news:1128967594.460257.42820@f14g2000cwb.googlegroups.com... > Hi, all. > > I'm newbie in circuits, > and I have a silly question. > > Suppose that one FPGA device has about 100 Vcc pins > (including VCCINT, VCCO, VCCAUX) and 80 GND pins. > Then how many decoupling capacistors are needed > for this IC? How can I decide that quantity? > > And can I have any reference design about > Xilinx FPGA and its configuration PROM? > I already read datasheet and user guide about that > but it is rather difficult for me. > So I cannot sure my design is right or wrong. > > If there is any reference, let me know that please. > Thank you for interested with my post. >Article: 90329
Hello All: Jsut an update on my efforts on using the Xilinx IPIF for a PLB master. Per another user's recommendation (thanks Alan Nishioka), I looked at the PLB spec from IBM and wrote my own interface. After several days of messing with the Xilinx IPIF fucntions, I could not get the master functionality to work correctly. I did, however, get my own to work pretty much on the first try. I wrote a simple peripheral that updated the contents of DDR memory every second with an increasing value (address zero got a 0; address 1 got a 1, etc.) Moral of the story: Read the PLB datasheet and you will be able to make whatever you want very quickly. It took me a total of 8 hours of reading through the datasheet and coding up my own state machine. If anyone wants to see my code (in Verilog), let me know. Thanks for all the help. -EliArticle: 90330
Hello, I'm looking for some example on how to use the USER1,2 functions in a spartan 3 (examples on virtex2/4 or others are welcomed). I know how to instanciate the component but that's about it. I searched xilinx site but didn't found any real example ... If anyone of you has a simple stuff using that at hand, that would be nice ! Regards, SylvainArticle: 90331
Eli Hughes wrote: > Hello All: > > Jsut an update on my efforts on using the Xilinx IPIF for a PLB master. > > Per another user's recommendation (thanks Alan Nishioka), I looked at > the PLB spec from IBM and wrote my own interface. > > After several days of messing with the Xilinx IPIF fucntions, I could > not get the master functionality to work correctly. > > I did, however, get my own to work pretty much on the first try. > > I wrote a simple peripheral that updated the contents of DDR memory > every second with an increasing value (address zero got a 0; address 1 > got a 1, etc.) > > > Moral of the story: Read the PLB datasheet and you will be able to make > whatever you want very quickly. It took me a total of 8 hours of > reading through the datasheet and coding up my own state machine. > > If anyone wants to see my code (in Verilog), let me know. Yes, I'd like to. To get my real email, just do a 'endian swap' on my email ;) I was just about to start using the IPIF for PLB master but if I can interface to the PLB myself and save some slices (the IPIF is 1000 slices with DMA!) thanks, SylvainArticle: 90332
I'm not exactly sure what the original poster was asking, but I use an SRL16(xilinx) initialised to X"FFFF", configured as 16 bit shift reg, and a '0' at the D input. Once Done goes high, GWE, GSR, etc are released(order of these dependent on bitgen options), the shift reg shifts in the '0' and after 16 clock cycles it appears at the SRL16 Q output. The Q output drives the reset I code into my design(active high). This insures my design reset is removed synchronous to my clock and the path is covered by my clock period timing constraint. (beware that the GSR net is high fanout and can have significant delay/skew depending on your clock frequency. I never found any timing specs for the GSR net in the Sparatan 3 FPGA datahseet...but there are plenty of posts about it. There is also a good tech exclusive(ken chapman) on the xilinx site talking about the use of resets in your FPGA design.) Regards AndrewArticle: 90333
Hi, I'm developing in verilog (Xilinx web pack with Modelsim XE). I came to the point I have to use some external c software for generating some signals. It's not mine though but I have the source that is using VPI. The problem is that this external code is using internal static variables for storing data between calls (y[n] = f(x,t,y[n-1])) from verilog and while using only one instance like this always @(posedge clk) out = $gen(parameters) it works fine. But now I need to use two or more instances at the same time like this: always @(posedge clk) out1 = $gen(parameters) out2 = $gen(parameters) . . outn = $gen(parameters) Because of internal static variables used in gen this is not working any more. I tried to save data like in workarea example (chapter 6) (http://www.sutherland.com/pli_book_examples.html) but it doesn't work: every time gen function is called different handler is passed to the function and diferent workarea is created on the stack. How can I get module handle that called my C function so I can save data between calls from verilog? Thanks, SlawcArticle: 90334
I new idea?
What do you experts think of the following entity I wrote? It’s purpose is
to eliminate metastability of the q signal.
The d signal is synchronous to a 1.8 MHz clock and the q will be synchronous
to a new 24 MHz clock. That means that at worst the entity will sample “one”
meta stable bit-value surrounded by many non meta stable bits.
For example (sampled values)
d: 00000X111111X00000X111111X00000 (X = meta stable bit-level)
From the initial state it need to interpret two neighbor samples as ones,
only then it gives a one on the q output. Then after that to get a zero on
the q output it must interpret two neighbor samples as zeros, then it gives
a zero on the q output.
And if you don’t think it will work please explain why. :-)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sync_to_new_clock is
Port ( new_clk : in std_logic;
d : in std_logic;
q : out std_logic);
end sync_to_new_clock;
architecture beh of sync_to_new_clock is
signal state : std_logic := '0';
begin
process(new_clk)
begin
if rising_edge(new_clk) then
case state is
when '0' => if d = '1' then -- a "real" 1 or a "fake-mata-stable"
'1'
state <= '1';
else
q <= '0';
end if;
when '1' => if d = '1' then
q <= '1';
else
state <= '0';
end if;
when others => null;
end case;
end if;
end process;
end beh;
Article: 90335
Dear Google Group Members,
Does anyone know how to instantiate a Xilinx Chipscope Pro VIO Core? I
understand that one must use component declarations in VHDL for the VIO
core, and therefore also for the ICON and ILA modules
The following is a component declaration for the ICON core when using
the Xilinx Chipscope Pro Core Generator and the radio button "Enable
Unused Boundary Scan Ports (Only if necessary)" is not selected.
---------------------------------------------------------------
component icon
port
(
control0 : out std_logic_vector(35 downto 0)
);
end component;
--------------------------------------------------------------
My question is how does Xilinx ChipScope 6.3.03i communicate with the
core? There are not inputs to the core, only an output
std_logic_vector bus.
When generating the ICON core, if the radio button is selected, "Enable
Unused Boundary Scan Ports (Only if necessary)" in the ICON Parameters
box the following component declaration is generated
-------------------------------------------------------------------
component icon
port
(
tdo_in : in std_logic;
capture_out : out std_logic;
tdi_out : out std_logic;
reset_out : out std_logic;
shift_out : out std_logic;
update_out : out std_logic;
sel_out : out std_logic;
drck_out : out std_logic;
control0 : out std_logic_vector(35 downto 0)
);
end component;
---------------------------------------------------------------
Another question I have for the group is that how does the first
component declaration communicate to the PC via JTAG/Boundary Scan if
there are no input signals? Which component declaration should I
choose?
Thank you responders in advance for answers to the above questions.
Article: 90336Bill - What if d is not a 1 or a 0, then what does your logic do? Remember, when a signal goes metastable, it may have an indeterminate value, ie, it may hover in the transition region somewhere between a 0 and a 1. Also - since you're using the d signal as input to multiple flops, because of routing and gate delays some flip-flops might see the d signal after it transitions, others might miss the transition. I think you're fighting a losing battle here. Synchronize the signal! John ProvidenzaArticle: 90337
Yes it comes with a linux and solaris cd too <aholtzma@gmail.com> wrote in message news:1128618734.597166.265290@g43g2000cwa.googlegroups.com... > > Newman wrote: >> aholt...@gmail.com wrote: >> > The Xilinx website isn't too clear with respect to the evaluation EDK >> > included with the Spartan-3 starter kit. Does anyone know if it is time >> > limited or feature limited? Can I run the reference microblaze designs >> > with it? Also, does anyone know if the starter kit will ship with >> > ISE/EDK 8.1i when it itself ships? Thanks! >> > >> > cheers, >> > aaron >> >> Aaron, >> IIRC, the Spartan 3 Eval kit shipped with a 60 day eval EDK 6_3 back >> in Feb 2005. It also came with a 60 day ISE6_3 eval. I have no >> information what they ship now. >> >> -Newman > > Thanks. One other thing, do the discs come with the linux binaries as > well? > > cheers, > aaron >Article: 90338
OK. I will go with this instead. The signals a and b is left to settle for 2
clock cycles to minimize the meta stable risk.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sync_to_new_clock is
Port ( new_clk : in std_logic;
d : in std_logic;
q : out std_logic);
end sync_to_new_clock;
architecture beh of sync_to_new_clock is
signal a, b, t : std_logic := '0';
attribute maxdelay: string;
attribute maxdelay of a: signal is "1 ns";
attribute maxdelay of b: signal is "1 ns";
begin
process(new_clk)
begin
if rising_edge(new_clk) then
if t = '0' then
q <= a;
a <= d;
t <= '1';
else
q <= b;
b <= d;
t <= '0';
end if;
end if;
end process;
end beh;
"johnp" <johnp3+nospam@probo.com> skrev i meddelandet
news:1128979682.817345.163290@g49g2000cwa.googlegroups.com...
> Bill -
>
> What if d is not a 1 or a 0, then what does your logic do?
>
> Remember, when a signal goes metastable, it may have an
> indeterminate value, ie, it may hover in the transition region
> somewhere between a 0 and a 1.
>
> Also - since you're using the d signal as input to multiple
> flops, because of routing and gate delays some flip-flops might
> see the d signal after it transitions, others might miss the
> transition.
>
> I think you're fighting a losing battle here. Synchronize the signal!
>
> John Providenza
>
Article: 90339"johnp" <johnp3+nospam@probo.com> skrev i meddelandet news:1128979682.817345.163290@g49g2000cwa.googlegroups.com... > Bill - > > What if d is not a 1 or a 0, then what does your logic do? > Remember, when a signal goes metastable, it may have an > indeterminate value, ie, it may hover in the transition region > somewhere between a 0 and a 1. The idea was that the state machine wolud jump to the other state or stay at the present state. > I think you're fighting a losing battle here. Synchronize the signal! :-( I know, but it's an interesting topic :-)Article: 90340
"Bill" wrote: >I new idea? Not new. >For example (sampled values) > > > >d: 00000X111111X00000X111111X00000 (X = meta stable bit-level) State: 000000X111111X00000X111111X0000 Q: 0000000X111111X00000X111111X000 >From the initial state it need to interpret two neighbor samples as ones, >only then it gives a one on the q output. Then after that to get a zero on >the q output it must interpret two neighbor samples as zeros, then it gives >a zero on the q output. But if the state is not one or zero, then with a zero input it might output a zero, and it might output a one. And with a one input it might output a zero, and it might output a one. > when others => null; While this case doesn't exist for binary logic, it does exist if "state" is not at '1' or '0', or metastable. The problem is that null isn't a physically realistic choice. The circuit is going to do something. -- Phil Hays to reply solve: phil_hays at not(coldmail) dot com If not cold then hotArticle: 90341
Haven't we beaten this to death? Just keep it simple, double-synchronize the asynchronous input in two cascaded flip-flops, and keep the delay between the two flip-flops to a minimum. At 24 MHz you will have more than 30 ns slack, and the MTBF will be more than 10e180 years. Call it an eternity. What more do you want ? Peter AlfkeArticle: 90342
happydude32905@gmail.com wrote:
> Dear Google Group Members,
>
> Does anyone know how to instantiate a Xilinx Chipscope Pro VIO Core? I
> understand that one must use component declarations in VHDL for the VIO
> core, and therefore also for the ICON and ILA modules
>
> The following is a component declaration for the ICON core when using
> the Xilinx Chipscope Pro Core Generator and the radio button "Enable
> Unused Boundary Scan Ports (Only if necessary)" is not selected.
>
> ---------------------------------------------------------------
> component icon
> port
> (
> control0 : out std_logic_vector(35 downto 0)
> );
> end component;
> --------------------------------------------------------------
>
> My question is how does Xilinx ChipScope 6.3.03i communicate with the
> core? There are not inputs to the core, only an output
> std_logic_vector bus.
>
>
> When generating the ICON core, if the radio button is selected, "Enable
> Unused Boundary Scan Ports (Only if necessary)" in the ICON Parameters
> box the following component declaration is generated
>
> -------------------------------------------------------------------
> component icon
> port
> (
> tdo_in : in std_logic;
> capture_out : out std_logic;
> tdi_out : out std_logic;
> reset_out : out std_logic;
> shift_out : out std_logic;
> update_out : out std_logic;
> sel_out : out std_logic;
> drck_out : out std_logic;
> control0 : out std_logic_vector(35 downto 0)
> );
> end component;
> ---------------------------------------------------------------
>
>
> Another question I have for the group is that how does the first
> component declaration communicate to the PC via JTAG/Boundary Scan if
> there are no input signals? Which component declaration should I
> choose?
>
> Thank you responders in advance for answers to the above questions.
>
In order to a VIO core to your design you must also have an ICON core
in your design. Connect the bidirectional control bus from the ICON
core to the control bus of the VIO core to provide communication and
then connect the user side inputs and outputs to wherever you need
them in the design.
Here's a Verilog Example snippet with 3 VIO cores:
wire [35:0] icon_control0;
wire [35:0] icon_control1;
wire [35:0] icon_control2;
wire [31:0] sync0_in;
wire [31:0] sync0_out;
wire [179:0] sync1_in;
wire [31:0] sync1_out;
wire [31:0] sync2_in;
wire [219:0] sync2_out;
//
// ChipScope Integrated Controller Core (3 ports)
//
icon_3 i_icon
(
.control0 (icon_control0),
.control1 (icon_control1),
.control2 (icon_control2)
);
//
// ChipScope VIO Core for MGT Adaptive IO controls
//
vio_32_32 i_vio_0
(
.control( icon_control0),
.clk( usrclk_g[0]),
.sync_in( sync0_in),
.sync_out( sync0_out)
);
//
// ChipScope VIO Core for Addressable BERT controls
//
vio_180_32 i_vio_1
(
.control( icon_control1),
.clk( usrclk_g[1]),
.sync_in( sync1_in),
.sync_out( sync1_out)
);
//
// ChipScope VIO Core for Addressable CLB & IOB Noise controls
//
vio_32_220 i_vio_2
(
.control( icon_control2),
.clk( usrclk_g[2]),
.sync_in( sync2_in),
.sync_out( sync2_out)
);
Both ICON questions are linked together, so I'm going to answer them as one.
The ICON (Integrated CONtroller) core includes a BSCAN primitive as part
of its netlist. The BSCAN primitive can be accessed by the JTAG chain
using special instructions for a USER1 and USER2 internal scan chains.
Selecting the "Enable Unused Boundary Scan Ports" allows you to bring out
the other port on the BSCAN primitive so that it can be used by your own
custom scan chain if you need it.
Ed
Article: 90343Bill wrote: > What do you experts think of the following entity I wrote? It's > purpose is to eliminate metastability of the q signal. ... > And if you don't think it will work please explain why. :-) Because the example you give is in VHDL, not in electronic circuitry. Metastability is a problem of real logic hardware, not VHDL. Any circuitry implementing actual gates and flip-flops will behave differently from your VHDL, given that physical components have an analog behavior with a finite gain and load capacitance that is not completely described in a digital VHDL model. The problem is the wire capacitance on the "q" output. Any solution has to drive that capacitance to a legal voltage clearly representing either a "1" or a "0" using finite gain circuitry. The solution is simple: put a positive gain feedback amplifier in the path and wait for it to resolve... and the fastest and simplest to characterize feedback device almost always turns out to be the output stage of a flip-flop/register chosen by your technology provider. Use it; minimize the load by driving only a single nearby following flop-flop; and wait the prescribed number of pS/nS/uS/fortnights sufficient for a resolution with a probability matching your choosen reliability level. Done. IMHO. YMMV. -- rhn A.T nicholson d.O.t C-o-MArticle: 90344
I have seen the exact same problem on our Virtex-4 FX20 ES1 boards. It
has consumed a lot of debugging time. Xilinx has not acknowledged a
problem.
I have also replicated the problem on FX12 ES1 dev boards with the most
basic project possible booting out of BRAM.
You've pretty much gone through all the steps including chilling the
chip to subzero temps with a can of inverted dusting spray (which
briefly solves the problem until it warms back up to room temp). I've
also tried changing power sequencing and using insanely long external
power on resets without luck.
I see a similar thing on the PLB bus except the garbage address that
occurs after the first correct jump is either 0x00100800 or 0x00000800.
Chris wrote:
> Hello,
>
> I am looking for some help with a particularily nasty problem I have
> run into,
>
> Out of our 10 prototype Virtex-4-FX20 (CES2 stepping) boards, roughly
> half are exhibiting an issue with the PPC405 starting up out of reset.
> After powerup, the bit file is loaded, done goes high, current load
> kicks in, but the PPC never boots. Other logic on the chip is running.
>
> When the device boots properly, there are no issues booting from BRAM,
> loading DDR-DRAM from flash, or executing from DRAM. Everthing is
> working good.
>
> Using chipscope, I can see the data from address 0xfffffffc being
> returned on the PPC405 PLB-I-Master side of the PLB arbiter correctly.
> However, the second address put out is garbage (0x100600), resulting in
> a bus error. The boot code is held in a BRAM off of the PLB. During a
> successful boot, the second address is 0xffffc000 which is correct.
> The reset sequence and first PLB bus cycle look identical in both the
> failing/non-failing cases.
>
> Observations:
> * Freeze spray (now known around here as 'FPGA programming spray') will
> without exception make this problem go away. (suggests a timing /
> power issue??)
> * Warm resets (through the EDK reset controller) have no effect. The
> only way to make this problem go away is to reload the device.
> * Reloading the device does not always work. Some boards will always
> boot fine on the second try, while others will only boot once cooled.
> * The emulator (tried both XMD and Greenhills probe) cannot talk to the
> processor when it is in this state.
> * Clocks, DCM locks, reset signals, debug/jtag signals, all look
> normal.
> * The PPC is in an unrecoverable state which is a little disturbing
> regardless of how it got there.
>
> What else have I tried (none of these have made a difference):
> * clocking the PPC405 slower. Same clock as the PLB.
> * JTAG loading -vs- selectmap loading
> * Boot from the OCM bus instead of the PLB.
> * Removed all other logic from the design except the PPC and an OCM
> BRAM
> * Looked closely at the power supplies / grounding.
> * I have already successfully played 'Stump the Xilinx FAE/factory'.
> * Spent hours in Timing Analyzer looking at any unconstrained nets.
> * Looked closely at errata
>
> What angles still left to explore
> * I am 95% convinced this is either the result of an external
> condition, or a chip defect.
> * So, I am working up a power-supply change to delay VCCO from VCCINT.
> I don't believe that is it, but I am running out of things to try.
>
> ...................
>
> Has anyone ever seen an issue like this (V4, or 2VPro)? I have done
> many FPGA designs over the years (although this is our first PPC-based
> design) and have rarely been this stumped.....
>
> Any and all advice is welcome. Email me or post here.
>
> Thanks,
> Chris
> '<*{{{><
Article: 90345Apologies for posting in an FPGA group, but I couldn't think of a more appropriate one. I hear ASIC designers talk about "full custom" designs. When I was at university our VLSI course painted colored polyons using Apollo workstations. I figure when you're laying down layers by hand, that's pretty custom. These days though, it's all about RTL and constraints - all in text files (maybe aided by tools) and so when engineers talk about "full custom" I wonder what it actually means. So I'd like a three minute synopsis on what a "full custom" work flow entails today. What are the engineers specifying and how are they specifying it? Thanks, Paul. (Feel free to use more than three minutes if necessary).Article: 90346
Chris wrote: > Hello, > > I am looking for some help with a particularily nasty problem I have > run into, > > Out of our 10 prototype Virtex-4-FX20 (CES2 stepping) boards, roughly > half are exhibiting an issue with the PPC405 starting up out of reset. > After powerup, the bit file is loaded, done goes high, current load > kicks in, but the PPC never boots. Other logic on the chip is running. > <snip> > * The PPC is in an unrecoverable state which is a little disturbing > regardless of how it got there. That's not as rare as users might hope. Quite a few devices have Reset lines that are better called 'ResetRequest', and where a hard power cycle is needed to recover from such states..... > What angles still left to explore > * I am 95% convinced this is either the result of an external > condition, or a chip defect. If freeze _always_ fixes, then that is a chip margin issue, (tho that may be aggravated by external conditions) Can you measure the chip temp (sense diode?), and get an appx temperature threshold ? ( if you warm the 'good' ones, do they then fail too ?) Is this 'being pushed', in the die temp sense ? Nudge of Vcc should also be similar to temp changes. Have you tried different date codes ? > * So, I am working up a power-supply change to delay VCCO from VCCINT. > I don't believe that is it, but I am running out of things to try. -jgArticle: 90347
I'm still mulling over replacing my aging system. Looks like a lot of
the newer workstation class processors are 64 bit processors, either P4
or AMD 64. I've seen several notes stating that you should check to see
if your applications will run on 64 bit systems before buying one. Not
sure if this is going to be a problem. I want to buy as much performance
as I can, but can't afford to not have the non-CAE stuff work
I need to run, at a minimum:
Xilinx, Altera, Actel FPGA tools,
Synplify, Modelsim, Aldec
Matlab w/ simulink
MS office, Quickbooks
Acronis (disk imaging back up)
virus protection (don't care who's)
adobe acrobat
Am I going to have problems using one of the 64 bit workstations for
this?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 90348Its late, but a quick reply follows. ASIC design (excluding FPGA designs) can be grouped into two categories: standard cell and full custom. Standard cell designs use a cell library of logic gates of different sizes. The cells in this library are designed to be stacked together nicely in rows so that the power and ground connections match. For each logic gate (inv, nor, nand, etc.) several different sizes, or drive strengths are present. Usually these are named with the strength as a postscript representing the size of the transistors in the cell as compared to the minimum size. For example, an INV_4 is an inverter whose transistors are sized four times that of a minimum sized inverter. Software tools from such vendors as Cadence and Synopsys synthesis RTL to these standard logic cells, place these cells in rows and route them together, driven by constraints entered by the designer. In full custom design, the designer sizes the transistors in each gate individually for maximum performance. This can entail 'pushing polygons' as you did in school under the guidance of circuit simulators and sizing tools, such as AMPS and Spice. Unlike standard cell design, where transistor widths are quantized, a designer can tailor each transistor's size to its specific load, reducing its input capacitance. Also, the designer can route wires and buses by hand for minimum delay and cross talk. In general full custom design takes much longer and respins are equally challenging. However, for designs where performance is paramount, such as a Pentium's ALU, full custom is what's used. (Disclaimer: I used to be an ASIC designer where we did some semi-custom design, but I never taped-out any full custom designs.)Article: 90349
I have noted that the problem seems to vary with temperature but not completely depend on it. It does not seem to be possible to eliminate occurrences of the problem on our worst samples no matter how much they are blasted with cold spray. Likewise on our best boards were the problem rarely (or seemingly never occurs) under normal operating conditions, it will usually show at higher temps. We did not connect the temp diodes on our boards but we attached one to the metal casing of the FPGA package during tests to get some rough idea of temperature. Some of our boards seem to have a temp threshold where the problem starts occurring above a certain temp. It's not a binary work/not work situation. Even at the high temps the board will still work from time to time, it just fails more frequently. As indicated by our 'best' and 'worst' boards, there is no magic temperature number that exists across different chips, it seems to vary quite widely. We have at least two date codes for FX20s. I've seen the problem on both. As I mentioned on my reply to Chris I've also seen the problem on an FX12 development board which I presume is a different die altogether. I have tried bumping up Vcc a little. No notable change in the problem.
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