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Messages from 116975

Article: 116975
Subject: Re: FPGA with 5V and PLCC package
From: cs_posting@hotmail.com
Date: 21 Mar 2007 08:51:37 -0700
Links: << >>  << T >>  << A >>
On Mar 21, 5:22 am, Herbert Kleebauer <k...@unibwm.de> wrote:
> cs_post...@hotmail.com wrote:
> > On Mar 20, 11:23 am, Herbert Kleebauer <k...@unibwm.de> wrote:
> > > The last
> > > version of XILINX ISE software which supports XC3000 FPGA's
> > > isn't an alternative (and I'm not sure whether it will
> > > run on W2k/XP) because the system must be extremely easy to
> > > use so the students are able to design and implement a simple
> > > CPU in about 10 hours (including the time to learn how to use
> > > the schematic entry and simulation tool).
>
> > As a suggestion, drop the schematic entry approach and introduce a
> > hardware design language such as Verilog, or VHDL, or some academic
> > invention that can be translated - these are much more powerful and
> > extensible to real world applications.  They are also much more
> > portable.
>
> As I explained in the other reply, that isn't an alternative.


As I explained in the other reply... yes in fact it is an alternative.


Article: 116976
Subject: Re: FPGA with 5V and PLCC package
From: cs_posting@hotmail.com
Date: 21 Mar 2007 08:54:56 -0700
Links: << >>  << T >>  << A >>
On Mar 21, 5:24 am, Herbert Kleebauer <k...@unibwm.de> wrote:

> Atmel only offers a place and route tool. Therefore I asked if
> somebody can suggest a simple to use design software (with
> a schematic entry) for the Atmel FPGA's.

Use your own front end outputting low-level HDL to the atmel or any
other implementation-specific tool

> That's like a city map which doesn't use graphics but only
> textual description of the street position and connections.
> You will never get a feeling for the layout of the city
> whereas a fast glance on the graphical city map shows you
> all. Sure, if you use one of the modern navigation systems
> you don't need any overview of the city, you are told
> when to turn left or right. This may be is the best way
> if you only want to go from position A to position B,
> but if have to understand how the city is organized, then
> this is completely inappropriate.

Two words: block diagram

Don't make them build a city brick by brick.  Building a piece of a
wall in the lab out of bricks is a great idea - but if you want to
talk about cities, you then zoom out to a larger unit size.


Article: 116977
Subject: Re: Data width in Block ram
From: "Daniel S." <digitalmastrmind_no_spam@hotmail.com>
Date: Wed, 21 Mar 2007 11:58:14 -0400
Links: << >>  << T >>  << A >>
ZHI wrote:
> I have to generate a block ram in xilinx. The data width is not fixed
> and it will be changed according to the requirement of project. I have
> noticed that the data width in the block ram has been designed to be
> the 2's exponential size. Sometimes the data width I needed was not
> exactly the 2's exponential size. Is there a way to make the data
> size  not the 2's exponential size exactly? Like 18bit width.

Available widths are 1,2,4,8,9,16,18,32 and 36bits - 9, 18 and 36bits 
widths are achieved by using parity bits.

To achieve high speeds and and area efficiency, BRAMs are built as SRAMs 
and come with similar row-column organization that places some restrictions 
on how freely bits can be accessed. If you use 8, 16 or 32 bits, you waste 
the parity bits. If you use 9, 18 or 36bits, you can use every bit within 
the BRAM. For any other width not listed in the first paragraph, you will 
be wasting bits up to the next widest width.

Article: 116978
Subject: Re: gated clock
From: patrick.melet@dmradiocom.fr
Date: 21 Mar 2007 09:00:27 -0700
Links: << >>  << T >>  << A >>
no there are synchronous


Article: 116979
Subject: Re: Off topic: what is the purpoe of XST?
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 21 Mar 2007 09:06:36 -0700
Links: << >>  << T >>  << A >>
Thomas,

It is up to you.  After you read the FAQ sheet, and the quote:

"Xilinx uses XST as a proving ground for many of the innovative
optimization ideas that Xilinx engineers have for improving HDL design
flows for Xilinx devices. These improvements are then shared with Xilinx
third party synthesis partners to ensure that anyone targeting Xilinx
FPGAs as their solution can benefit from the best optimization the
industry has to offer."

Then make a decision. Is XST going to provide you with the value you
seek?  As you well know, sometimes one tool will provide a very
different result from another tool.  Synthesis is a complex and changing
business, and recognition of elements, and targeting them to the most
area efficient and speedy solution, is something that is non-trivial to do.

Some customers may be prototyping with FPGAs, and will not actually use
them in production.  For them, XST is (probably) completely capable of
meeting their needs.  Others will be trying to get the fastest possible
logic, and pack the most into the smallest device, and they may end up
trying several different tools (XST included) before they find the one
that provides the best result.

Finally, there are those that go with a single vendor (Symplicity, for
example), and are comfortable with the tools, and have developed a great
deal of expertise in their use, and really do not want to try anything
else as it would dilute their efforts.

If one read the FAQ, I doubt they would be complaining that "XYZ did not
synthesize correctly in XST" as right there in the FAQ it states that it
is not a 100% complete tool (recognizing all possible elements and
constructs).

Austin

Article: 116980
Subject: Re: gated clock
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 21 Mar 2007 16:07:12 -0000
Links: << >>  << T >>  << A >>

<patrick.melet@dmradiocom.fr> wrote in message 
news:1174492827.370037.66360@n59g2000hsh.googlegroups.com...
> no there are synchronous
>

if reset then
  reset_stuff_happens_here;
elsif rising_edge(fast_clock) then
  if clock_mode = 0 then  --which clock to use?
    clock_en <= clock_enable_1;  --clock 1?
  else
    clock_en <= clock_enable_2;  --clock 2?
  end if;

  if clock_en then   --run state machine at required rate
    state <= next_state;
  end if;

end if; 



Article: 116981
Subject: Re: Xilinx ISE support for dual/quad core CPUs?
From: "Daniel S." <digitalmastrmind_no_spam@hotmail.com>
Date: Wed, 21 Mar 2007 12:27:44 -0400
Links: << >>  << T >>  << A >>
Michael Sch÷berl wrote:
>> I'm going to work on a Virtex 4 FX100 soon so I'll
>> need all the horsepower I can get for the P&R runs...
> 
> I've been working on a Virtex4 LX100 design early this
> year and the main problem was memory usage. I upgraded
> my Windows XP Box to 4 GBytes (and patched to allow
> 3 GBytes/process) and even that was not enough!
> 
> Above something like 55% Lut/FF usage par 8.2 failed
> ("out of memory") after 2 hours or more.
> 
> I wonder how it should be possible to work with
> even larger FPGAs!?

Synplify on a 16GB x86_64 *nix box can probably handle the 4XL330. If you 
look at the "Why ISE sucks" thread, ISE is a research tool not intended for 
serious designs... that's pretty much what the XST page on Xilinx's own 
site says.

Trying to build all the bitfiles for the board below using ISE tools alone 
would probably be a one-way ticket to the asylum...

http://www.dinigroup.com/product/data/DN8000k10/images/dn8000k10_blockd.PNG

Article: 116982
Subject: Re: gated clock
From: patrick.melet@dmradiocom.fr
Date: 21 Mar 2007 09:45:54 -0700
Links: << >>  << T >>  << A >>
in fact I want to send the CLK clock to all the design not just a FSM
So CLK_1 goes to filter one, filter two, etc
and then it's CLK_2 that goes to filter one, filter two (filters with
others coefficients in respect to the new clock CLK_2)




Article: 116983
Subject: Re: how to shift mutiple bytes in an array in one clock cycle?
From: "John_H" <newsgroup@johnhandwork.com>
Date: Wed, 21 Mar 2007 09:57:29 -0700
Links: << >>  << T >>  << A >>
How about abstracting the address instead?  Each time you have to shift, the 
addresses 0-4 swap back and forth with 5-9.
Better yet, use two arrays and swap which you read or write depending on the 
"shift" status.

"CMOS" <manusha@millenniumit.com> wrote in message 
news:1174492085.641940.122080@y66g2000hsf.googlegroups.com...
>i have a byte array of size 10 and i need to shift values in the
> array
> to left by 5 positions in 5 clocks.
> here is the code im using.
>
> reg [7:0] data[0:9];
>
> // data shifting process
> reg ps_shift_start;
> reg ps_done;
>
> reg [1:0] ps_state;
> parameter ps_s0 = 2'b00;
> parameter ps_s1 = 2'b01;
>
> reg [12:0] ps_shift;
> integer ps_index;
>
> always @ (posedge clk) begin
>        if(reset == 1) begin
>                ps_done <= 0;
>                ps_state <= ps_s0;
>        end
>        else begin
>                case(ps_state)
>                ps_s0: begin
>                        if(ps_shift_start == 1) begin
>                                ps_done <= 0;
>                                ps_shift <= 0;
>                                ps_state <= ps_s1;
>                        end
>                end
>                //
>                ps_s1: begin
>                        if(ps_shift < 5) begin
>                                for(ps_index = 0; ps_index < 10;
> ps_index = ps_index + 1) begin
>                                        data[ps_index] <=
> data[ps_index + 1];
>                                end
>                        end
>                        else begin
>                                ps_done <= 0;
>                                ps_state <= ps_s0;
>                        end
>                end
>                endcase
>        end
> end
>
> the problem is XST syntherziser infferes lot of flip-flops for the
> signal 'data'. is't is possible to use
> distributed RAM for signal 'data'. if posssible, how do i do that?
>
> thank you
> 



Article: 116984
Subject: Re: Manual LUT - AND function mapping problem
From: "John_H" <newsgroup@johnhandwork.com>
Date: Wed, 21 Mar 2007 10:00:11 -0700
Links: << >>  << T >>  << A >>
For this level of control, I instantiate something that I can use as a 
template and use the getattr to attain the full string including the 
LUT-to-D connection, changing only what I know needs to be changed from my 
code-instantiated template.  I haven't found documentation on all the ins 
and outs of changing an attribute across the many architectures and 
architecture elements.


"Pasacco" <pasacco@gmail.com> wrote in message 
news:1174492134.326507.255980@e1g2000hsg.googlegroups.com...
> Dear all
>
> I am trying to manually map "2-bit AND" function into single slice,
> with no luck -:
>
> I type the commands below in the FPGA editor.
>
> Problem is that,
>
> "F" port of slice is NOT connected to "D" pin of LUT.
>
> I wonder if following is correct.
>
> F:\#LUT:D=A1\*A2\
>
> If someone has experience, let us know how I should modify the
> command.
> Any document or pointer will be also grateful.
>
> I am using ISE 8.2.03 and Virtex-4. Thank you in advance.
>
>
>
> --------------------------------------------------------------------------------------------------------------------------
> select site "SLICE_X0Y2"
> add
> setattr comp $COMP_0  Name s0
> unselect -all
>
> select site "SLICE_X2Y2"
> add
> setattr comp $COMP_1  Name s1
> unselect -all
>
> select comp "s1"
> setattr comp s1 F A1*A2
> setattr comp s1 G A1*A2
>
> setattr comp s1 Config COUTUSED:\#OFF\ YUSED:0\ XUSED:0\ F5USED:\#OFF\
> YBMUX:\#OFF\ YINIT:\#OFF\
> F:\#LUT:D=A1\*A2\ REVUSED:\#OFF\ SYNC_ATTR:\#OFF \ SRFFMUX:\#OFF\
> FFY_SR_ATTR:\#OFF\ FFX:\#OFF\ FFY:\#OFF\ FFX_SR_ATTR:\#OFF\ G_ATTR:
> \#OFF\ DIG_MUX:\#OFF\ CY0G:\#OFF\ FXUSED:\#OFF\ DIF_MUX:\#OFF\ F_ATTR:
> \#OFF\ CY0F:\#OFF\ DIGUSED:\#OFF\ SHIFTOUTUSED:\#OFF\ BYOUTUSED:\#OFF\
> FFX_INIT_ATTR:\#OFF\ FFY_INIT_ATTR:\#OFF\
> ....
> --------------------------------------------------------------------------------------------------------------------------
> 



Article: 116985
Subject: Re: gated clock
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 21 Mar 2007 17:10:23 -0000
Links: << >>  << T >>  << A >>
<patrick.melet@dmradiocom.fr> wrote in message 
news:1174495554.397494.307580@e65g2000hsc.googlegroups.com...
> in fact I want to send the CLK clock to all the design not just a FSM
> So CLK_1 goes to filter one, filter two, etc
> and then it's CLK_2 that goes to filter one, filter two (filters with
> others coefficients in respect to the new clock CLK_2)
>
I think you want to send a single fast clock to filter one, filter two. If 
necessary, make it with a PLL or DCM. Then use a clock enable for the 
filters. Adjust the clock enable according to your required rates. 



Article: 116986
Subject: Re: Xilinx ISE support for dual/quad core CPUs?
From: "Patrick Dubois" <prdubois@gmail.com>
Date: 21 Mar 2007 10:20:46 -0700
Links: << >>  << T >>  << A >>
On Mar 21, 12:28 am, "Daniel S."
<digitalmastrmind_no_s...@hotmail.com> wrote:

> If you are a little lucky, you might be able to find an overclocking tool
> that will enable you to tweak your computer's clock generator. My current
> computer has a P4P800-VM board whose BIOS lacks bus speed adjustments but I
> downloaded a clock generator control program for my board's IC and I was
> able to overclock my P4-3.0 up to 3.5GHz - I overclocked only for burn-in
> and stability testing for about a week, I am back to stock speed for
> power/noise-saving.
>
> I got the clockgen control utility for my board's chip there:http://www.cpuid.com/clockgen.php

Nice, thanks for the tip.



Article: 116987
Subject: Looking for resources on timing analysis
From: "FPGAEngineer@gmail.com" <FPGAEngineer@gmail.com>
Date: 21 Mar 2007 10:58:19 -0700
Links: << >>  << T >>  << A >>
I have been doing FPGA design work for a few years now and must admit
that timing analysis scares me because it is something I didn't learn
in school.  We use Xilinx FPGA's at the company where I currently
work, and I am somewhat familiar with the ISE Timing Analyzer tool.
However, I am looking to learn how to do timing analysis manually
before using the tool, because I feel it is becoming more and more
important as bus speeds are increasing, not to mention it's a good
skill to add to a resume.  Can anyone suggest any resources, whether
they be online or perhaps a good book?  I'm looking to have an
understanding of the various parameters one must take into account
when analyzing timing budgets for both system and source synchronous
interfaces, including board-level effects.  Any information would
greatly be appreciated.


Article: 116988
Subject: Re: Looking for resources on timing analysis
From: "Eric Crabill" <eric.crabill@xilinx.com>
Date: Wed, 21 Mar 2007 11:35:13 -0700
Links: << >>  << T >>  << A >>
Hi,

Go here:  http://www.engr.sjsu.edu/crabill/  and check Lecture Module 3. 
This is only an introduction for synchronous digital circuits with a single 
clock.  It only gets more complicated from there...

Eric

<FPGAEngineer@gmail.com> wrote in message 
news:1174499899.034327.269380@d57g2000hsg.googlegroups.com...
>I have been doing FPGA design work for a few years now and must admit
> that timing analysis scares me because it is something I didn't learn
> in school.  We use Xilinx FPGA's at the company where I currently
> work, and I am somewhat familiar with the ISE Timing Analyzer tool.
> However, I am looking to learn how to do timing analysis manually
> before using the tool, because I feel it is becoming more and more
> important as bus speeds are increasing, not to mention it's a good
> skill to add to a resume.  Can anyone suggest any resources, whether
> they be online or perhaps a good book?  I'm looking to have an
> understanding of the various parameters one must take into account
> when analyzing timing budgets for both system and source synchronous
> interfaces, including board-level effects.  Any information would
> greatly be appreciated.
> 



Article: 116989
Subject: Re: Why is Xilinx's WebPACK so inferior?
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 21 Mar 2007 11:49:00 -0700
Links: << >>  << T >>  << A >>
MM,

We restrict webcases from being filed by students: (the only stated
restriction)

http://www.xilinx.com/support/clearexpress/websupport.htm

http://www.xilinx.com/univ/studentsupport.htm

That said, the professors who use our components are allowed to file
cases (they are instructed on how by the XUP program), and individuals
who wish to file a webcase do have to register in a way that at least
causes us to believe that they are a real or potential customer.

Austin

Article: 116990
Subject: Re: Why is Xilinx's WebPACK so inferior?
From: Taylor Hutt <thutt151@comcast.net>
Date: 21 Mar 2007 11:50:11 -0700
Links: << >>  << T >>  << A >>
"MM" <mbmsv@yahoo.com> writes:

> > You can't file reports to the company until you register.
> 
> I believe only paying customers can create webcases...

That's the impression I got too, and I believe it's just plain silly.
First of all, I paid for my demo board, so in a sense, I'm a paying
customer, albiet a tiny, tiny, tiny one.

But, when a tool breaks, it breaks equally for paying and non-paying
customers, so it behooves the company to listen to all issues found
about a product, as the resolution of those issues, no matter if they
come from a paying customer or a freeloader,  will make the tools all
that much better.  And, here's the big secret, when the tools are
better, the "paying customers" might be willing to pay even more money
for better tools!

thutt

Article: 116991
Subject: Re: FPGA with 5V and PLCC package
From: "Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch>
Date: Wed, 21 Mar 2007 19:53:58 +0100
Links: << >>  << T >>  << A >>
"Symon" <symon_brewer@hotmail.com> wrote in message 
news:4601501d_1@x-privat.org...
> "Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch> 
> wrote in message news:etrgnt$gov$1@cernne03.cern.ch...
>>
>> I _wish_ i'd been introduced to VHDL in level one at university.  All 
>> digital logic design ties together, and in my opinion all the different 
>> aspects can and should be taught as interrelated topics. (contrary to 
>> some practices)
>>
> Hi Benjamin,
> OTOH, I'm glad that I know what the VHDL is compiled into. I think 
> Herbert's intention in this class is to show his students what the logic 
> is made up from, and schematics of gates and FFs do achieve this.
> As you say, I'd expect the course to then go on to show how the same thing 
> can be implemented in 5 minutes with 10 lines of Verilog (or 50 lines of 
> VHDL! :-)) but I do see where he's coming from.
> Cheers, Syms.
>
Hey Syms,

I agree with what you say... In some cases these subjects are so closely 
linked that I begin to question why they should be separate at all.

Especially CPLD design.  I always suggest designing the circuit mentally 
(i.e. Get the designer to question how the circuit could be made if all 
he/she had was a pile of 74LSxxx) and writing the VHDL to match, and I refer 
an awful lot to Burn Rate - 7400 series understanding is fundemental to 9500 
series design!

Ben 



Article: 116992
Subject: Re: Off topic: what is the purpoe of XST?
From: "Daniel S." <digitalmastrmind_no_spam@hotmail.com>
Date: Wed, 21 Mar 2007 15:12:42 -0400
Links: << >>  << T >>  << A >>
Thomas Entner wrote:
>> In other words, XST is a test vehicle where we are intentionally 
>> experimenting, in order to improve.
> 
> Hi Austin,
> 
> is this your personal meaning, or official Xilinx? Do the
> Xilinx-software-team see their work in this context? Does this mean, that
> XST and/or ISE should not be used for serious work?

That is pretty much what it means and what is written on the XST page from 
Xilinx's own site, in "marketese" as Austin said. Look elsewhere in this 
thread to find Austin's link to the relevant Xilinx page.

Go check job postings on monster, workopolis and others. Look for some 
high-profile FPGA applications and see how many mention Xilinx FPGAs as the 
target and Synplify as required/asset... nearly 100%. It becomes pretty 
obvious that very few serious rely on XST.

Article: 116993
Subject: Re: Why is Xilinx's WebPACK so inferior?
From: nico@puntnl.niks (Nico Coesel)
Date: Wed, 21 Mar 2007 19:13:21 GMT
Links: << >>  << T >>  << A >>
Taylor Hutt <thutt151@comcast.net> wrote:

>
>I've been using the Xilinx Webpack 8.2i since sometime in November,
>and I've become so irritated with their software that I'm about ready
>to just become a rabid Xilinx basher.

The reason I'm still using 7.x is that the schematics editor in 8.x
and higher uses aliasing which -litteraly- makes me cry because I
can't focus on aliased lines (and yes, I have an excellent monitor).
Why do they want to fix things that aren't broken?

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

Article: 116994
Subject: Re: FPGA with 5V and PLCC package
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Thu, 22 Mar 2007 07:22:51 +1200
Links: << >>  << T >>  << A >>
Herbert Kleebauer wrote:
> Jim Granville wrote:
> 
>>Herbert Kleebauer wrote:
> 
> 
>>>Here a description of the students project:
>>>ftp://137.193.64.130/pub/mproz/mproz_e.pdf
>>
>>This is such a simple CPU, that I quickly tried it targeting the
>>ATF1508 - which _is_ 5V and _is_ PLCC84, so you can keep all your design
>>notes, and just re-map the pins on the PCB layout you have.
> 
> 
> Thanks for the mail. But this example clearly shows the difference
> between a textual and a graphical representation of circuit.
> 
> 
> 
>>/* ~~~~~~~~~~~~~~~ ALU, pre-adder ~~~~~~~~~~~~~~~~~ */
>>/* ALU: IF (s7=0) THEN out=in1 ADD in2 , F=carry
>>    ELSE out=in1 NOR in2 , F=zero
>>*/
>>ALU = s7 & !(XGate # YGate)
>>     # !s7 & (XGate $ YGate);      /* Dummy, until adder done */
> 
> 
> How should the student get a feeling how many gates are necessary 
> to implement this two lines?

By reading the Fitter report, pasted below.
Each node eqn is there, and there is also a summary.
These reports are a vital part of the design understanding.

As an exercise, I'd ask the student to write something more than
one way, and to sumbit the FIT report file portions, that show the
trade offs of either way.

Just like I'd expect a Microcontroller student to be able to inspect the 
MAP file from an linker, to tell me the exact size of any function, be 
it assembler, C, library or whatever.

A student should also be aware that there is not a 1:1 correlation 
between gates and Schematic - the tools WILL shuffle things about
(sometimes quite a lot), as they pack it into the silicon.


> It's the same as programming in a
> HLL. No question, it is much more effective to us a HLL than
> using an assembler. But any HLL programmer should have done
> assembly programming so he has a feeling what a HLL code
> snippet has for consequences for the CPU and so he not always
> selects the code which is most easily written but the code which
> most easily can be calculated by the CPU.

-jg

[This will wrap in the news system]

MCell Pin# Oe   PinDrive  DCERP  FBDrive  DCERP  Foldback  CascadeOut 
   TotPT SO
MC1   0         --               PC14     Dge--  --        -- 
   2     f-
MC2   0         --               PC13     Dge--  --        -- 
   2     f-
MC3   12   on   ALU0      C----  PC7      Dge--  NA        -- 
   5     f-
MC4   0         --               PC12     Dge--  --        -- 
   2     f-
MC5   11   on   ALU1      C----  PC5      Dge--  NA        -- 
   5     f-
MC6   10   --   Din1      INPUT  PC3      Dge--  --        -- 
   2     f-
MC7   0         --               PC11     Dge--  --        -- 
   2     f-
MC8   9    --   Din3      INPUT  PC4      Dge--  --        -- 
   2     f-
MC9   0         --               PC9      Dge--  --        -- 
   2     f-
MC10  0         --               PC10     Dge--  --        -- 
   2     f-
MC11  8    --   Din2      INPUT  PC2      Dge--  --        -- 
   2     f-
MC12  0         --               PC8      Dge--  --        -- 
   2     f-
MC13  6    --   Din4      INPUT  PC1      Dge--  YGate1    -- 
   3     f-
MC14  5    --   Din6      INPUT  PC0      Dge--  YGate0    -- 
   3     f-
MC15  0         --               PC6      Dge--  XGate1    -- 
   3     f-
MC16  4    on   F         Dge--  --              XGate0    -- 
   4     f-
MC17  22   --   Din5      INPUT  XReg5    Dge--  --        -- 
   2     f-
MC18  0         --               XReg15   Dge--  --        -- 
   2     f-
MC19  21   --   Din7      INPUT  XReg6    Dge--  --        -- 
   2     f-
MC20  0         --               XReg13   Dge--  --        -- 
   2     f-
MC21  20   --   Din9      INPUT  XReg4    Dge--  --        -- 
   2     f-
MC22  0         --               XReg11   Dge--  --        -- 
   2     f-
MC23  0         --               XReg12   Dge--  --        -- 
   2     f-
MC24  18   --   Din8      INPUT  XReg2    Dge--  --        -- 
   2     f-
MC25  17   --   Din10     INPUT  XReg3    Dge--  --        -- 
   2     f-
MC26  0         --               XReg10   Dge--  --        -- 
   2     f-
MC27  16   --   Din12     INPUT  XReg1    Dge--  --        -- 
   2     f-
MC28  0         --               XReg8    Dge--  --        -- 
   2     f-
MC29  15   --   Din11     INPUT  PC15     Dge--  --        -- 
   2     f-
MC30  0         --               XReg9    Dge--  --        -- 
   2     f-
MC31  0         --               XReg7    Dge--  --        -- 
   2     f-
MC32  14   --   TDI       INPUT  XReg0    Dge--  --        -- 
   2     f-
MC33  0         --               YReg13   Dge--  --        -- 
   2     f-
MC34  0         --               YReg14   Dge--  --        -- 
   2     f-
MC35  31   --   Din13     INPUT  YReg6    Dge--  --        -- 
   2     f-
MC36  0         --               YReg12   Dge--  --        -- 
   2     f-
MC37  30   --   Din15     INPUT  YReg4    Dge--  --        -- 
   2     f-
MC38  29   --   s2        INPUT  YReg5    Dge--  --        -- 
   2     f-
MC39  0         --               YReg10   Dge--  --        -- 
   2     f-
MC40  28   --   s8        INPUT  YReg3    Dge--  --        -- 
   2     f-
MC41  0         --               YReg11   Dge--  --        -- 
   2     f-
MC42  0         --               YReg9    Dge--  --        -- 
   2     f-
MC43  27   --   Din14     INPUT  YReg1    Dge--  --        -- 
   2     f-
MC44  0         --               YReg7    Dge--  --        -- 
   2     f-
MC45  25        --               YReg2    Dge--  --        -- 
   2     f-
MC46  24        --               YReg0    Dge--  --        -- 
   2     f-
MC47  0         --               YReg8    Dge--  --        -- 
   2     f-
MC48  23   --   TMS       INPUT  XReg14   Dge--  --        -- 
   2     f-
MC49  41   on   ALU8      C----  --              --        -- 
   3     f-
MC50  0         --               --              --        -- 
   0     f-
MC51  40   on   ALU7      C----  --              YGate8    -- 
   4     f-
MC52  0         --               --              YGate7    -- 
   1     f-
MC53  39   on   ALU6      C----  --              YGate6    -- 
   4     f-
MC54  0         --               --              YGate4    -- 
   1     f-
MC55  0         --               --              YGate3    -- 
   1     f-
MC56  37   on   ALU5      C----  --              YGate5    -- 
   4     f-
MC57  36   on   ALU4      C----  --              YGate2    -- 
   4     f-
MC58  0         --               --              XGate8    -- 
   1     f-
MC59  35   on   ALU3      C----  --              XGate7    -- 
   4     f-
MC60  0         --               --              XGate6    -- 
   1     f-
MC61  34   on   ALU2      C----  --              XGate5    -- 
   4     f-
MC62  0         --               --              XGate4    -- 
   1     f-
MC63  0         --               --              XGate3    -- 
   1     f-
MC64  33        --               YReg15   Dge--  XGate2    -- 
   3     f-
MC65  44   on   Adr0      C----  --              --        -- 
   2     f-
MC66  0         --               --              --        -- 
   0     f-
MC67  45   on   ALU15     C----  --              YGate14   -- 
   4     f-
MC68  0         --               --              YGate13   -- 
   1     f-
MC69  46   on   ALU14     C----  --              YGate15   -- 
   4     f-
MC70  0         --               --              YGate11   -- 
   1     f-
MC71  0         --               --              YGate10   -- 
   1     f-
MC72  48   on   ALU13     C----  --              YGate12   -- 
   4     f-
MC73  49   on   ALU12     C----  --              YGate9    -- 
   4     f-
MC74  0         --               --              XGate15   -- 
   1     f-
MC75  50   on   ALU11     C----  --              XGate14   -- 
   4     f-
MC76  0         --               --              XGate13   -- 
   1     f-
MC77  51   on   ALU10     C----  --              XGate12   -- 
   4     f-
MC78  0         --               --              XGate11   -- 
   1     f-
MC79  0         --               --              XGate10   -- 
   1     f-
MC80  52   on   ALU9      C----  --              XGate9    -- 
   4     f-
MC81  0         --               --              --        -- 
   0     f-
MC82  0         --               --              --        -- 
   0     f-
MC83  54   on   Adr7      C----  --              --        -- 
   2     f-
MC84  0         --               --              --        -- 
   0     f-
MC85  55   on   Adr6      C----  --              --        -- 
   2     f-
MC86  56   on   Adr5      C----  --              --        -- 
   2     f-
MC87  0         --               --              --        -- 
   0     f-
MC88  57   on   Adr4      C----  --              --        -- 
   2     f-
MC89  0         --               --              --        -- 
   0     f-
MC90  0         --               --              --        -- 
   0     f-
MC91  58   on   Adr3      C----  --              --        -- 
   2     f-
MC92  0         --               --              --        -- 
   0     f-
MC93  60   on   Adr2      C----  --              --        -- 
   2     f-
MC94  61   on   Adr1      C----  --              --        -- 
   2     f-
MC95  0         --               --              --        -- 
   0     f-
MC96  62   --   TCK       INPUT  --              --        -- 
   0     f-
MC97  63   on   Adr14     C----  --              --        -- 
   2     f-
MC98  0         --               --              --        -- 
   0     f-
MC99  64   on   Adr13     C----  --              --        -- 
   2     f-
MC100 0         --               --              --        -- 
   0     f-
MC101 65   on   Adr12     C----  --              --        -- 
   2     f-
MC102 0         --               --              --        -- 
   0     f-
MC103 0         --               --              --        -- 
   0     f-
MC104 67   on   Adr11     C----  --              --        -- 
   2     f-
MC105 68   on   Adr10     C----  --              --        -- 
   2     f-
MC106 0         --               --              --        -- 
   0     f-
MC107 69   on   Adr9      C----  --              --        -- 
   2     f-
MC108 0         --               --              --        -- 
   0     f-
MC109 70   on   Adr8      C----  --              --        -- 
   2     f-
MC110 0         --               --              --        -- 
   0     f-
MC111 0         --               --              --        -- 
   0     f-
MC112 71   --   TDO       C----  --              --        -- 
   0     f-
MC113 0         --               --              --        -- 
   0     f-
MC114 0         --               --              --        -- 
   0     f-
MC115 73   --   s4        INPUT  --              --        -- 
   0     f-
MC116 0         --               --              --        -- 
   0     f-
MC117 74   --   s7        INPUT  --              --        -- 
   0     f-
MC118 75   --   s5        INPUT  --              --        -- 
   0     f-
MC119 0         --               --              --        -- 
   0     f-
MC120 76   --   s6        INPUT  --              --        -- 
   0     f-
MC121 0         --               --              --        -- 
   0     f-
MC122 0         --               --              --        -- 
   0     f-
MC123 77   --   s3        INPUT  --              --        -- 
   0     f-
MC124 0         --               --              --        -- 
   0     f-
MC125 79   --   Din0      INPUT  --              --        -- 
   0     f-
MC126 80   --   s1        INPUT  --              --        -- 
   0     f-
MC127 0         --               --              --        -- 
   0     f-
MC128 81   on   Adr15     C----  --              --        -- 
   2     f-
MC0   2         --               --              --        -- 
   0     f-
MC0   1         --               --              --        -- 
   0     f-
MC0   84        --               --              --        -- 
   0     f-
MC0   83        CLK       INPUT  --              --        -- 
   0     f-

Logic Array Block			Macro Cells	I/O Pins	Foldbacks	TotalPT	FanIN		Cascades
A: MC1	- MC16		18/16(112%)	8/16(50%)	4/16(25%)	43/80(53%)	24/40(60%)	0
B: MC17	- MC32		16/16(100%)	8/16(50%)	0/16(0%)	32/80(40%)	18/40(45%)	0
C: MC33	- MC48		16/16(100%)	6/16(37%)	0/16(0%)	32/80(40%)	17/40(42%)	0
D: MC49	- MC64		8/16(50%)	7/16(43%)	14/16(87%)	37/80(46%)	19/40(47%)	0
E: MC65	- MC80		8/16(50%)	8/16(50%)	14/16(87%)	37/80(46%)	20/40(50%)	0
F: MC81	- MC96		7/16(43%)	8/16(50%)	0/16(0%)	14/80(17%)	15/40(37%)	0
G: MC97	- MC112		8/16(50%)	8/16(50%)	0/16(0%)	14/80(17%)	15/40(37%)	0
H: MC113- MC128		1/16(6%)	8/16(50%)	0/16(0%)	2/80(2%)	3/40(7%)	0

Total dedicated input used:	1/4 	(25%)
Total I/O pins used		61/64 	(95%)
Total Macro cells used 		82/128 	(64%)
Total Flip-Flop used 		49/128 	(38%)
Total Foldback logic used 	32/128 	(25%)
Total Nodes+FB/MCells 		114/128 	(89%)
Total cascade used 		0
Total input pins 			28
Total output pins 		34
Total Pts 				211




Article: 116995
Subject: Re: Why is Xilinx's WebPACK so inferior?
From: "MM" <mbmsv@yahoo.com>
Date: Wed, 21 Mar 2007 14:23:06 -0500
Links: << >>  << T >>  << A >>
> You can't file reports to the company until you register.

I believe only paying customers can create webcases...

Having said that I would like to join the chorus of the ones being irritated 
by the ISE tools (mostly map and par in my case). I've been working on a big 
V4FX60 design and it's been a nightmare. FATAL errors left and right. You 
fit a design, then take a big portion of logic OUT of it and it can't fit it 
anymore. You finally get something with reasonable timing after prolonged 
fight with the tools, then add one flip-flop or change one net and it breaks 
everything no matter which guide modes you use. I had to cancel my vacation 
as I couldn't deliver a working design to a deadline :( It is most 
frustrating to feel that you have no control over what's going to be 
generated next time you do a minor change.


/Mikhail 



Article: 116996
Subject: Re: Austin the Altera Mole
From: "Derek Simmons" <dereks314@gmail.com>
Date: 21 Mar 2007 12:53:29 -0700
Links: << >>  << T >>  << A >>

They're too busy trying to get QuartusII V7.0 out the door. My
complaint is they just released V6.0 six months ago. What new and
major changes could justify a new version already?

On Mar 21, 3:19 am, rickystickyr...@hotmail.com wrote:
> Is he?
>
> First Austin admits Cyclone 3 is lower power than S3E or V5.
>
> Then he tells us to stop using XST for real designs.
>
> All in one day.
>
> Please, someone from Altera send him a fruit basket.
>
> Ricky Sticky.



Article: 116997
Subject: Re: Why is Xilinx's WebPACK so inferior?
From: "John_H" <newsgroup@johnhandwork.com>
Date: Wed, 21 Mar 2007 12:54:59 -0700
Links: << >>  << T >>  << A >>
If a tool is broken, it's good to know from any source.  But how many 
webcases from "freeloaders" - students or otherwise - are truely tool errors 
and not a user issue?  (I don't consider students as freeloaders but 
acknowledge that the professor should be better informed as a first resort 
for problem resolution).  It takes time and effort - real cost to Xilinx - 
to go through every webcase that isn't a case at all but instead an issue of 
understanding the tool or language capabilities.

Why should I expect even an hour's worth of a Customer Application 
Engineer's time if the only person benefitting from the time is me?  Not 
some company I work for now or in the future, not Xilinx, but only myself.

If I have a problem with a fireplace insert I bought, I can call up customer 
service to enquire about getting the fireplace insert replaced.  I can't 
expect extensive help on figuring out how to properly burn wet newspapers. 
If I already know how to burn wet newspapers or can get the proper 
information elsewhere, more power to me.  If burning wet newspapers means 
selling hundreds more fireplace inserts, it could be appropriate for the 
manufacturer to spend some time and resources (money) helping me out.  Just 
because I bought the product doesn't mean I deserve development support.


"Taylor Hutt" <thutt151@comcast.net> wrote in message 
news:m3veguph24.fsf@localhost.localdomain...
> "MM" <mbmsv@yahoo.com> writes:
>
>> > You can't file reports to the company until you register.
>>
>> I believe only paying customers can create webcases...
>
> That's the impression I got too, and I believe it's just plain silly.
> First of all, I paid for my demo board, so in a sense, I'm a paying
> customer, albiet a tiny, tiny, tiny one.
>
> But, when a tool breaks, it breaks equally for paying and non-paying
> customers, so it behooves the company to listen to all issues found
> about a product, as the resolution of those issues, no matter if they
> come from a paying customer or a freeloader,  will make the tools all
> that much better.  And, here's the big secret, when the tools are
> better, the "paying customers" might be willing to pay even more money
> for better tools!
>
> thutt 



Article: 116998
Subject: Re: prog_b held low?
From: mtsukanov@gmail.com
Date: 21 Mar 2007 12:55:16 -0700
Links: << >>  << T >>  << A >>
well, I went ahead and took the V4 out of the JTAG chain, and the new
chain consisting of just the CPLD and the PROM was recognized by
Impact. Apparently the CPLD  bit stream had a glitch/corruption in it,
that pulled the V4's prog_b line low. Once I erased the contents of
the CPLD, the V4 came out of reset.


Article: 116999
Subject: Re: Off topic: what is the purpoe of XST?
From: Tim <tim@nooospam.roockyloogic.com>
Date: Wed, 21 Mar 2007 19:58:57 +0000
Links: << >>  << T >>  << A >>
Daniel S. wrote:

> Go check job postings on monster, workopolis and others. Look for some 
> high-profile FPGA applications and see how many mention Xilinx FPGAs as 
> the target and Synplify as required/asset... nearly 100%. It becomes 
> pretty obvious that very few serious rely on XST.

I do. It's good. But I try to run my stuff through Synplify as well. The 
code should compile cleanly in XST, ModelSim, and Synplify, just like 
C++ should compile cleanly in vc, bcc, and gcc.

And if it's a wacky bug I go to Synplify first - it's better at showing 
me where I have tried to be clever ;-)





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