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On 4=D4=C219=C8=D5, =CF=C2=CE=E71=CA=B147=B7=D6, Peter Alfke <a...@sbcgloba= l=2Enet> wrote: > Ribbon cable: > Ideally you would like to use a coaxial cable for each signal, so that > there would be a controlled and defined impedance,and no crosstalk > between the signals. > A ribbon cable is an approximation of that, if you use the even- > numbered wires for the various signals, and all the odd-numbered wires > together as common ground. The shielding is not perfect, but usually > acceptable, and you keep the characteristic impedance fairly high (I > assumed 100 Ohm, but it might be 70 Ohm). > The asumption is that the output driver has a lower impedance than > that. CMOS outputs ar often as low as 10 Ohm. > You can measure the output impedance by loading the output with > various resistors to ground (try 100, 47, and 22 Ohms or something > like it). > Never thinkof the cable as a lumped capacitance. It is a transmission > line with distributed C and L plus some series resistance causing > losses , but I don't believe the losses will bother you much. 1 m > should be easy. If you had said 10 or 50 m, it would be another > matter... > Peter Alfke > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D > On Apr 18, 9:28 pm, "X.Y." <Xieyu1...@gmail.com> wrote: > > > > > Thanks for your reply. Thank you! > > To Symon and Peter Alfke, using ribbon cable is really a good ideal. > > It's simple and cheap. However, our CMOS image sensor (OV9655) is from > > OmniVision and is originally used on a mobile phone. It is very small > > not only on volume but also on power (90mW). Are you sure the > > attenuation is not a problem? And besides, I knew a little about the > > method of source terminators from the book "High Speed Digital Design" > > of Johnson & Graham. However, I do not understand the means of "Make > > every other conductor ground" and "in the gnd-sig-gnd mode" as Symon > > suggested. Sorry for my ignorance, could you tell me more about it? > > > To Tim and dalai lamah, thank you and I will try these chips later.- = =D2=FE=B2=D8=B1=BB=D2=FD=D3=C3=CE=C4=D7=D6 - > > - =CF=D4=CA=BE=D2=FD=D3=C3=B5=C4=CE=C4=D7=D6 - OK, I understand your means. Thank you very much! I will try it! Thank you!Article: 118176
Hi everybody, I'm using a Cyclone II EP2C20 which has 52 M4K memory blocks with each 4096+512bits. I want to use the whole memory, but I can't use the additional 512bits of the M4K blocks. if I make "a lpm_ram_dp" or "altsyncram" with 16384 8bit words the usage is: 20 lut + 32 M4K + 4 reg if I make "a lpm_ram_dp" or "altsyncram" with 16384 9bit words the usage is: 22 lut + 36 M4K + 4 reg the 9th bit (parity) is not in the additional 512bits of the M4K blocks but in 4 more M4K blocks!!!??? How can I use this additional 512bits of the M4K blocks??? Is there an other megafunction which uses this bits??? Thanks for any help, ManfredArticle: 118177
The "problem" is that Quartus by default uses the M4Ks in the 4k x 1 mode for such large memories (better performance). In the MegaWizard you can limit the maximum words per M4K to 512, Quartus will then use the 512x9 mode (this will need more LUTs for output-multiplexing and has less performance). Regards, Thomas www.entner-electronics.com "Manfred Balik" <manfred.balik@tuwien.ac.at> schrieb im Newsbeitrag news:46272a43$0$10578$3b214f66@tunews.univie.ac.at... > Hi everybody, > > I'm using a Cyclone II EP2C20 which has 52 M4K memory blocks with each > 4096+512bits. > I want to use the whole memory, but I can't use the additional 512bits of > the M4K blocks. > if I make "a lpm_ram_dp" or "altsyncram" with 16384 8bit words the usage > is: 20 lut + 32 M4K + 4 reg > if I make "a lpm_ram_dp" or "altsyncram" with 16384 9bit words the usage > is: 22 lut + 36 M4K + 4 reg > the 9th bit (parity) is not in the additional 512bits of the M4K blocks > but in 4 more M4K blocks!!!??? > How can I use this additional 512bits of the M4K blocks??? > Is there an other megafunction which uses this bits??? > > Thanks for any help, > Manfred >Article: 118178
Hi, Just wondering whether somebody could let me know the different between IOB and DIFFM/DIFFS for Xilinx FPGA. The following pin assignment constraints were specified in .ucf for Xilinx XC2V8000 FPGA. NET RAM1_SnWBYTE(0) LOC=AM27; NET RAM1_SnWBYTE(1) LOC=AM26; NET RAM1_SnWBYTE(2) LOC=AP27; NET RAM1_SnWBYTE(3) LOC=AP26; But I got the following error complaining about constaints for RAM0_SnWBYTE[1] and RAM0_SnWBYTE[2] Couldn't pass the place and route process, resolved that DIFFM RAM0_SnWBYTE[1] is restricted such that it may not be placed in a IOB. Couldn't pass the place and route process, resolved that DIFFM RAM0_SnWBYTE[2] is restricted such that it may not be placed in a IOB. Any idea why this happened? Cheers, -WilliamArticle: 118179
My suggestion is you design for the worst case..... if u duplicate the rams u will automatically get multiport reads.... you can create any multiples of frequencies from the DCM....Article: 118180
"X.Y." <Xieyu1219@gmail.com> wrote in message news:1176963245.037547.197000@b58g2000hsg.googlegroups.com... > OK, I understand your means. Thank you very much! I will try it! > Thank you! Dear XY, No worries. Here are some links to show Peter and I are not making this up! Shows loss vs. length:- http://www.csee.umbc.edu/~plusquel/650/slides/ribbon_cables.pdf Shows impedance:- http://www.daburn.com/1888.html Let us know how you get on! Cheers, SymsArticle: 118181
Thanks, I've tested it and that solves my problem :-))) "Thomas Entner" <aon.912710880@aon.at> schrieb im Newsbeitrag news:46272c28$0$2298$91cee783@newsreader01.highway.telekom.at... > The "problem" is that Quartus by default uses the M4Ks in the 4k x 1 mode > for such large memories (better performance). In the MegaWizard you can > limit the maximum words per M4K to 512, Quartus will then use the 512x9 > mode (this will need more LUTs for output-multiplexing and has less > performance). > > Regards, > > Thomas > > www.entner-electronics.com > > "Manfred Balik" <manfred.balik@tuwien.ac.at> schrieb im Newsbeitrag > news:46272a43$0$10578$3b214f66@tunews.univie.ac.at... >> Hi everybody, >> >> I'm using a Cyclone II EP2C20 which has 52 M4K memory blocks with each >> 4096+512bits. >> I want to use the whole memory, but I can't use the additional 512bits of >> the M4K blocks. >> if I make "a lpm_ram_dp" or "altsyncram" with 16384 8bit words the usage >> is: 20 lut + 32 M4K + 4 reg >> if I make "a lpm_ram_dp" or "altsyncram" with 16384 9bit words the usage >> is: 22 lut + 36 M4K + 4 reg >> the 9th bit (parity) is not in the additional 512bits of the M4K blocks >> but in 4 more M4K blocks!!!??? >> How can I use this additional 512bits of the M4K blocks??? >> Is there an other megafunction which uses this bits??? >> >> Thanks for any help, >> Manfred >> > >Article: 118182
Hi Mans The latest version of Tyd-IP Code Generator will create VHDL code for polyphase filter structures...not free though, but perhaps we can do something to help you. Regards Robert mans (myname_here) wrote: > Hello, > Where can I find the VHDL ( or verilog) source code for polyphase filter? > Is there any free implementation around? > > RegardsArticle: 118183
whyraja@gmail.com writes: > hi, > i want to impliment a 64 bit floating point matrix > multplication of matrix size 256*256, in verilog. Asking this on a VHDL newsgroup may not be the best idea... try comp.arch.fpga (given that you are thinking of using Xilinx devices) - I'll cross post this there... > kindly suggest me is > it possible to impliment in xillinx. > Yes. There are many more questions to be answered now... For example.. How fast do you want to do it? Are you going to use internal or external memory to store your matrices? (Are there devices with 12MBit of internal BRAM...?) My compilation's finished now, so I'm back off to the lab now... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 118184
<stenasc@yahoo.com> wrote in message
news:1176975694.600581.40110@b75g2000hsg.googlegroups.com...
> Hi Mans
>
> The latest version of Tyd-IP Code Generator will create VHDL code for
> polyphase filter structures...not free though, but perhaps we can do
> something to help you.
>
> Regards
> Robert
>
> mans (myname_here) wrote:
>> Hello,
>> Where can I find the VHDL ( or verilog) source code for polyphase
>> filter?
>> Is there any free implementation around?
>>
>> Regards
>
Thanks.
What is Tyd_IP? Where can I find more information about it?
Regards
Article: 118185On Apr 12, 4:08 pm, elshou...@gmail.com wrote: > Tracing timing violations in the post-p&r generated netlist can be > cumbersome with all signal merging/renaming and inserted buffer. I was > wondering if there is a way that I can back annotate the post place > and route delays back to the RTL code? even approximate delays can > reveal some design errors I would think. > > Thank you. It would be great wouldn't it? The main problem seems to be that there are at least two, and sometimes three or more tools in the chain between RTL and placed & routed gates. Tracing the heritage of gates back to RTL requires that all of those tools cooperate in providing the necessary information in a uniform manner. Often there is no direct heritage, given re-timing and pipelining optimizations. Also, the RTL may have "hidden" some of the gates in expressions or variables that cannot be directly annotated with delays without major re-writing of the code. I have found that if I do a good job simulating the RTL, and verifying the constraints used for STA, the set of problems encountered during full timing simulation is very limited. AndyArticle: 118186
On Apr 18, 11:40 am, Thomas Heller <thel...@python.net> wrote: > Finally I gotsimulationof logicores in webpack 9.1.03i to work with the ISE simulator. > However, these messages appear in the transcript window: > > Running Fuse ... > WARNING:HDLParsers:3583 - File "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" which file "C:/Xilinx91i/theller/mydesign/divider.vhd" depends on is modified, but has not been compiled. You may need to compile "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" first. > Compiling vhdl file "C:/Xilinx91i/theller/mydesign/detector.vhd" in Library work. > Entity <detector> compiled. > Entity <detector> (Architecture <behavioral>) compiled. > WARNING:HDLParsers:3583 - File "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" which file "C:/Xilinx91i/theller/mydesign/divider.vhd" depends on is modified, but has not been compiled. You may need to compile "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" first. > WARNING:HDLParsers:3583 - File "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" which file "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" depends on is modified, but has not been compiled. You may need to compile "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" first. > WARNING:HDLParsers:3583 - File "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" which file "C:/Xilinx91i/theller/mydesign/detector.vhd" depends on is modified, but has not been compiled. You may need to compile "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" first. > WARNING:HDLParsers:3583 - File "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" which file "C:/Xilinx91i/theller/mydesign/detector.vhd" depends on is modified, but has not been compiled. You may need to compile "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" first. > Compiling vhdl file "C:/Xilinx91i/theller/mydesign/detector_tbw.vhw" in Library work. > Entity <detector_tbw> compiled. > Entity <detector_tbw> (Architecture <testbench_arch>) compiled. > Parsing "detector_tbw_beh.prj": 1.84 > Codegen work/detector: 0.00 > Codegen work/detector/Behavioral: 0.41 > Codegen work/detector_tbw: 0.00 > Codegen work/detector_tbw/testbench_arch: 0.34 > Building detector_tbw_isim_beh.exe > Running ISimsimulationengine ... > This is a Lite version of ISE Simulator. > Simulator is doing circuit initialization process. > Finished circuit initialization process. > > Apparently this file "K:/IP2_J.2/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/div_gen_v1_0.vhd" isn't present on my system, it is probably a filename inXilinxsource code. How can I recompile this file??? > > Other files like these > "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" > "C:/Xilinx91i/vhdl/src/ieee/std_logic_unsigned.vhd" > "C:/Xilinx91i/vhdl/src/ieee/std_logic_arith.vhd" > *are* present on my system, but *I* did not change them. > > How can it be that they need to be compiled? How would I compile them? > Do I have a broken installation? > Or should I not be bothered at all by these messages? > > Thanks for any help, > Thomas Hi Thomas, Can you try to do a clean up project files and ensure that you have both: - Latest Service Pack - Latest IP Update The order in which you install should be the order in which it was released. If you use webupdate, then this will take care of this for you. Sounds like it is trying to look an older compiler version somewhere and that is why you are getting the error. Thanks DuthArticle: 118187
On Apr 18, 5:35 am, "mans" <(myname_here)_123...@yahoo.com> wrote: > Hello, > I am trying to simulate a VHDL code (usingISE9) and I am getting the > following error: > > ERROR:Simulator:235 - Package XXX_pkg has not been compiled properly. Please > recompile package XXX_pkg. > > How can I compile a package? > > Regards Hi, You should not need to recompile any pre-compiled libraries with ISE Simulator. This should only happen if some work library is out of sync with the latest compiler. Can you try a clean up project files and try again? Also ensure that the SP installations all went smoothly as that is when the pre-compiled libraries get installed. Thanks DuthArticle: 118188
www.tyder.com mans (myname_here) wrote: > <stenasc@yahoo.com> wrote in message > news:1176975694.600581.40110@b75g2000hsg.googlegroups.com... > > Hi Mans > > > > The latest version of Tyd-IP Code Generator will create VHDL code for > > polyphase filter structures...not free though, but perhaps we can do > > something to help you. > > > > Regards > > Robert > > > > mans (myname_here) wrote: > >> Hello, > >> Where can I find the VHDL ( or verilog) source code for polyphase > >> filter? > >> Is there any free implementation around? > >> > >> Regards > > > > Thanks. > What is Tyd_IP? Where can I find more information about it? > > RegardsArticle: 118189
Can anyone explain to me what the difference is between MPM7064LC84 and EPM7064LC84? Thanks, DerekArticle: 118190
On Apr 19, 8:23 am, "mans" <(myname_here)_123...@yahoo.com> wrote: > <sten...@yahoo.com> wrote in message > > news:1176975694.600581.40110@b75g2000hsg.googlegroups.com... > > > > > Hi Mans > > > The latest version of Tyd-IP Code Generator will create VHDL code for > > polyphase filter structures...not free though, but perhaps we can do > > something to help you. > > > Regards > > Robert > > > mans (myname_here) wrote: > >> Hello, > >> Where can I find the VHDL ( or verilog) source code for polyphase > >> filter? > >> Is there any free implementation around? > > >> Regards > > Thanks. > What is Tyd_IP? Where can I find more information about it? > > Regards ...Urine sample from a rock concert? (tie-dye pee) :^) AndyArticle: 118191
Hi, I'm a beginner in the fpga world.I've been reading up some of the books listed in this group in other posts, and doing basic designs (like contollers, ALUs etc). Although the books and my school lab have helped me get started with fpga design, I'm far, far away from being _good_ at it. Any suggestions on which direction I should be going in? IMHO, the only way to get there would be to spend more and more time 'getting my hands dirty' so to say. Books don't help beyond a point. So I'm also looking for a good fpga board I can use over summer and more.... Some suggestions were the spartan-3 starter kit, XSK40 and the XSK95. Being a poor student, I can't afford anything else (and being a beginner I guess I may not be able to _use_ anything else :) ) Which one would you suggest I should go for? Thanks, KunalArticle: 118192
On Apr 18, 4:35 am, "mans" <(myname_here)_123...@yahoo.com> wrote: > Hello, > I am trying to simulate a VHDL code (using ISE 9) and I am getting the > following error: > > ERROR:Simulator:235 - Package XXX_pkg has not been compiled properly. Please > recompile package XXX_pkg. > > How can I compile a package? > > Regards Did you add the file containing this package to your project ? /MHSArticle: 118193
Kunal, The "Spartan 3E Starter Board" from digilentinc.com is used by quite a number of schools and universities. As such, 'google' for this shows 131 hits, with complete courses with labs from University of Arizona, etc. etc. $149. http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Products&Nav2=Programmable AustinArticle: 118194
On Wed, 18 Apr 2007 21:11:50 -0700, nezhate wrote: > On Apr 18, 9:40 pm, Andy Peters <goo...@latke.net> wrote: >> On Apr 18, 4:24 am, nezhate <mazouz.nezh...@gmail.com> wrote: >> >> > Hi all, >> > I'm using Ise 9.1.03i. when I try to print a code written in Ise text >> > editor, I get this error: >> > "Print fails because the default printer has not been selected", and >> > when the design summary is opened I can see the window "steup >> > printer" and my default printer is automatically selected. How to >> > configure printer for ise text editor? thanks. >> >> Wow...somebody actually uses the ISE text editor? >> >> I thought everyone just used emacs. >> >> -a > not everyone works under Linux. > At home I have Linux and use emacs but in univ. they have windows and > use Ise text editor .... what to do? Xemacs is available for Windows, you don't have to suffer with the ISE editor even if you have to suffer with Windows. Xemacs is available stand alone or as part of Cygwin.Article: 118195
On Apr 19, 12:14 pm, Kunal <kunal.yadwad...@gmail.com> wrote: > Some suggestions were the spartan-3 starter kit, XSK40 and the XSK95. > Being a poor student, I can't afford anything else (and being a > beginner I guess I may not be able to _use_ anything else :) ) The Spartan-3 kit is pretty good, complete out of the box, and you'll find some projects for it around the net. I would spend the extra $20 to get an XC3S400 chip on it though (get it from Digilent rather than Xilinx). I see they are also offerings the XC3S1000, though you could get that chip cheaper on the nexys board. The nexys board is interesting if you want to play with USB for high-bandwidth things, and it has better digital I/O's. But it lacks the serial, keyboard, and VGA ports of the S3kit. Also, if you go that route you may want to buy one of their great-deal power supplies and parallel port programmer cables so you aren't completely dependent on the USB for power and programming. Which brings up the point: if your development computer doesn't have a parallel port, get they nexys rather than the s3kit.Article: 118196
> I am trying to simulate a VHDL code (using ISE 9) and I am getting the >following error: >ERROR:Simulator:235 - Package XXX_pkg has not been compiled properly. Please >recompile package XXX_pkg. Happens to me all the time with ISE8.2 Just clean out the project files, rebuild, and go get some more coffee. ISE seems to have trouble maintaining dependency information. -- mac the naïfArticle: 118197
On Apr 19, 12:44 pm, Austin Lesea <aus...@xilinx.com> wrote: > Kunal, > > The "Spartan 3E Starter Board" from digilentinc.com is used by quite a > number of schools and universities. > > As such, 'google' for this shows 131 hits, with complete courses with > labs from University of Arizona, etc. etc. > > $149. > > http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Pro... > > Austin Unless someone really needs an S3E chip, I might stay away from that board, as part of its schematics (around the USB chip) are withheld, limiting your options for programming and communicating with it to what is officially supported or laboriously reverse engineered.Article: 118198
On Apr 19, 1:48 pm, cs_post...@hotmail.com wrote: > On Apr 19, 12:44 pm, Austin Lesea <aus...@xilinx.com> wrote: > > > Kunal, > > > The "Spartan 3E Starter Board" from digilentinc.com is used by quite a > > number of schools and universities. > > > As such, 'google' for this shows 131 hits, with complete courses with > > labs from University of Arizona, etc. etc. > > > $149. > > >http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Pro... > > > Austin > > Unless someone really needs an S3E chip, I might stay away from that > board, as part of its schematics (around the USB chip) are withheld, > limiting your options for programming and communicating with it to > what is officially supported or laboriously reverse engineered. In fairness, I should add the substantial memories and display to the "unless one needs" consideration. All of these boards have tradeoffs of goodies vs. issuesArticle: 118199
On 19 Apr 2007 11:48:07 -0700, cs_posting@hotmail.com wrote: >On Apr 19, 12:44 pm, Austin Lesea <aus...@xilinx.com> wrote: >> Kunal, >> >> The "Spartan 3E Starter Board" from digilentinc.com is used by quite a >> number of schools and universities. >> >> As such, 'google' for this shows 131 hits, with complete courses with >> labs from University of Arizona, etc. etc. >> >> $149. >> >> http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Pro... >> >> Austin > > >Unless someone really needs an S3E chip, I might stay away from that >board, as part of its schematics (around the USB chip) are withheld, >limiting your options for programming and communicating with it to >what is officially supported or laboriously reverse engineered. How totally pathetic - who could possibly gain anything by hiding part of a devboard....
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