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cs_posting@hotmail.com wrote: : On Apr 9, 12:54 pm, "johnp" <johnp3+nos...@probo.com> wrote: : > We've used the FX2 on multiple projects with FPGAs. : > : > The FX2 delivers a stream of data bytes to the host, from the : > hosts perspective, it hasn't a clue if the external FX2 bus is : > 8 or 16 bits. As long as the transfer lengths are an even : > number of bytes and your FPGA code properly converts your : > internal 16/32/48 bit data into a byte stream, you should : > have no problems. : In general I'd agree - but my fear is that if synchronization was lost : for any reason, there'd be no way to get it back. And maybe not even : any way to know, other than the data not making any sense. Are you using the Digilent firmware on the device or your own? I've not used their firmware so I can't comment on that. If you are using your own firmware then there are a couple of options open: 1. Explicitly use one of the CTL signals from the FX2 GPIF (internal fifo control) to act as an upper/lower byte select. This would guarantee that all words are correctly preserved. There is an example of this in the 'EZ-USB FX2 GPIF Primer' pdf from Cypress. 2. Most of the FX2 devices' Port A pins are availible as IO from the FX2 firmware and as user IO from the FPGA. You could pulse one of these occasionaly from the FX2 firmware to check/force proper alignment within the FPGA. Digilent must have connect them up for a reason so perhaps one of them would suffice for this under their firmware? cheers cds (who is glad Digilent connect up ifclk on this board, unlike their old USB2 module...)Article: 117776
On Apr 10, 6:02 pm, "Gabor" <g...@alacron.com> wrote: > On Apr 10, 4:10 am, "CMOS" <manu...@millenniumit.com> wrote: > > > is there any opensource alternatives to platformstudio and microblaze > > development? > > Do you want open source for microblaze development specifically? > Or opensource for any open source 32-bit embedded micro? > > Lattice Mico32 development might fit the bill for the second... im looking for a complete set of tools and ip cores with some good documentation. tnaksArticle: 117777
On Apr 10, 9:40 am, "CMOS" <manu...@millenniumit.com> wrote: > On Apr 10, 6:02 pm, "Gabor" <g...@alacron.com> wrote: > > > On Apr 10, 4:10 am, "CMOS" <manu...@millenniumit.com> wrote: > > > > is there any opensource alternatives to platformstudio and microblaze > > > development? > > > Do you want open source for microblaze development specifically? > > Or opensource for any open source 32-bit embedded micro? > > > Lattice Mico32 development might fit the bill for the second... > > im looking for a complete set of tools and ip cores with some good > documentation. > > tnaks You might want to check out the LEON processors. www.gaisler.com I never used them myself though. It's free if your project is open- source, if it's closed-source you must pay for the license. You could also use some free cores from opencores.org. Lots of IP blocks there built around the Wishbone bus (including a few processors). But going this route, you don't have a nice integrated GUI that EDK provides. PatrickArticle: 117778
Hi Peter, Draw a bus wire extending from the out of the counter and give it a name like counteroutput[17..0]. Draw another separate wire going into the lpm_compare and give it the name counteroutput[17..13]. They will be connected correctly by the extractor. Hope this helps, Subroto Datta Altera Corp. "PeterK" <meltyb@hotmail.com> wrote in message news:evfphk$ie$1$8302bc10@news.demon.co.uk... > Dear Altera experts, > > My very first project is a PWM in Quartus II 7.0. I've drawn up a block > diagram with a 17 bit lpm_counter going into a 5 bit lpm_compare. All I > want is the top five bits of the counter to go into the comparator. After > several days of trying I still have no idea how to split the 17 bits to > just use the top five bits. With a normal bus connection it compiles with > a Width mismatch error. > > Peter >Article: 117779
I am looking for a working model of std8980 (TI Tap master) or any other tap master model. The one from FMF (http:// www.freemodelfoundry.com/) does not seem to work correctly! -- AmalArticle: 117780
axr0284 wrote: > Hi, > I am trying to measure an input signal that will be a square wave of > a certain unknown frequency in the range 1MHz to 4 MHz using an FPGA. > I have no control over that input signal. The FPGA should be able to > track the signal as it changes. Usually there is a +-5% max shift in > frequency from time to time. There is no reference clock for this > signal. > > I am not sure a simple counter will be an effective solution in this > case. I am afraid of setup time issues since the internal FPGA clock > will not be synchronized with the external signal. Can one phase lock > two signals easily in an FPGA? I would probably need a counter > running at 400 MHz to effectively to measure a 1% change in a 4MHz > signal accurately. > > I am wondering if there is an asynchronous solution to this issue that > might be more effective. Any ideas would be highly appreciated. Thanks > a lot, > Amish You have two options: 1) oversampling: use a much faster system clock to sample, detect and count transitions to determine the pulse width 2) use your input signal as the clock for a gray-code counter, capture, decode and compare that against another counter running on the system clock The second approach is used by precision frequency meters - all they need to do is a periodic difference between counts. These often use 1MHz internal clocks and simply count to 100k/250k/500k/1M/10M between diffs (depending on selected scale and precision) and output updates. If you need tight temporal granularity, oversampling (count the number of fastclk cycles between N slowclk transitions, select N as a power-of-two for convenience: fixed-point average for free) is probably best.Article: 117781
On Apr 8, 10:22 am, Richard Pennington <r...@pennware.com> wrote: > fpgabuilder wrote: > > [snip] > > > > > > > Your goal is definitely intriguing. But there are a couple of things > > that I am not sure of - > > > 1. In a distributed environment, you do not want centralized control. > > Therefore, the only thing standard between the two devices is the > > interface. So a unified tool to describe the devices seems kind of > > skewed from the basis. > > > 2. If a goal of SMIL is to describe an interface and then generate any > > logic for it straight from C. Isn't this one of the goals of SystemC? > > > Am I missing something? > > Best regards, > > Sanjay > > Great questions. Part of my problem is explaining what I'm trying to > accomplish, I think. > > A little background. In my day job I work on a fairly complex medical > device that is made up of an operator's console and image reconstruction > system that is Linux based. This connects to the actual patient > scanner via an ethernet connection to an SBC running vxWorks. Part of > the system rotates about an axis and has its own SBC running vxWorks. > Both the stationary and rotating sides of the device talk to a variety > of other subsystems via Ethernet, CAN, and serial ports. > > The interfaces between the systems are currently described with C header > files. A lot of code is present on the two SBCs to translate the TCP/IP > messages coming from the operators console to forms compatible with the > non-Ethernet communication links. > > SMIL is an attempt to unify the definition of the communication paths > throughout the entire system. It is designed for distributed computing > but my emphasis has been on systems of the sort I just described. Pats > might come up and go down asynchronously, but generally most of the > parts need to be present for the device to function. > > I wanted to be able to do semantic checks on the interfaces. SMIL will > check that a data packet (a SMIL event) which is generated in a part of > the system is consumed in another part of the system, for example. In > general events are broadcast in SMIL: You don't have to explicitly say > where the event is being consumed. This decouples the system to a great > extent, obviously, making for what I think is a cleaner system design. > SMIL doesn't really do broadcasts, however. During system generation it > can see where events flow and generate code to send the events from the > source to the destination(s) automatically. > > As to point two, Yes, SystemC can generate code for FPGAs. SMIL's main > emphasis is the communication paths between the systems. To that end > there are facilities to detect when subsystems power up and go down, > trace events, do endian conversions, etc. that are not (I think) > directly available in SystemC. Also, SMIL is (or will be) open source. I > don't believe that's true of SystemC. > > Thanks for the questions. > > -Rich Actually SystemC is open-source and I may just be able to do everything that you are doing in SMIL with a C++ library. The interfaces would plug straight into your code that is running on individual SBCs. Synthesis maybe a problem. I'd be curious to know things that you are able to do with SMIL that you cannot do with SystemC. http://www.systemc.org/web/sitedocs/library_overview.html Best, -sanjayArticle: 117782
GaLaKtIkUs™ wrote: > Hi everybody, > In the new version (2.1) of the Virtex-4 User Guide (ug070), in the > FIFO chapter is described the synchronous clock work-around (page 161) > to solve the FIFO bug. At the end of the paragraph the following is > written: "The connections between the input registers and the FIFO16 > must be tightly constrained, as this part of the circuit effectively > runs at twice the clock rate." > Can anybody explain me which contraints are needed? placement? timing? > an example is wellcome! Because one is posedge and the other negedge, signals only have half a period to get from the FFs' outputs to the FIFOs' inputs. At 100MHz, this is not really a problem but at 200MHz and beyond, this translates to less than 2.5ns timing constraints. Unless those work-around FFs are constrained very close to the FIFOs, PAR is going to take forever to meet timings and might fail altogether.Article: 117783
On Apr 9, 4:51 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > mans wrote: > > I have an entity in VHDL that one of its ports is a record type. I am > > trying to create a test bench wave form to test the code but when ISE > > creating a test bench; it doesn't create the wave form for records. What is > > the problem and how can I solve it? > Hi, Please refrain from using anything other than std_logic or std_logic_vector in the top level. Xilinx recommends using only std_logic and std_logic_vector at the top level. Even arrays are not supported as yet. The main reason is that there is no way for the back annotation tools to write out HDL that matches your top structure. Since the waveform tool is written to work with the rest of the ISE tools, it does not support this either. The workaround if you absolutely must have it be records is to write one manually, although be aware the only simulation you can do easily would be the RTL simulation. Thanks Duth > I would write my own testbench. > The alternative is to change the port types > or talk toXilinx. > > -- Mike TreselerArticle: 117784
mynewlifever@yahoo.com.cn wrote: > I use COREGEN to generate XAUI(choose device Virtex5 110t), but I > cannot do simulation with modelsim6.1f. It is always reporting the > following error. I think maybe there is something in modelsim needed > to set. Please to help me. Thank you! > > vsim work.testbench > # Loading d:\Xilinx91i\smartmodel\nt\installed_nt/lib/pcnt.lib/ > swiftpli_mti.dll > # ** Error: (vsim-3193) Load of "d:\Xilinx91i\smartmodel\nt > \installed_nt/lib/pcnt.lib/swiftpli_mti.dll" failed: DLL > dependent library not found. > # ** Error: (vsim-PLI-3002) Failed to load PLI object file > The most likely cause is that you have not properly installed the SmartModels on your system. More information on how to do this can be found here: http://toolbox.xilinx.com/docsan/xilinx9/books/docs/sim/sim.pdf There is also something weird in the path names that might be causing a problem as it contains both forward and back slash characters. I am not sure how that may have happened, but it looks like something has mixed up DOS vs UNIX directory styles. Ed McGettigan -- Xilinx Inc.Article: 117785
On Apr 10, 4:23 am, "mynewlife...@yahoo.com.cn" <mynewlife...@yahoo.com.cn> wrote: > I use COREGEN to generate XAUI(choose device Virtex5 110t), but I > cannot dosimulationwith modelsim6.1f. It is always reporting the > following error. I think maybe there is something in modelsim needed > to set. Please to help me. Thank you! > > vsim work.testbench > # Loading d:\Xilinx91i\smartmodel\nt\installed_nt/lib/pcnt.lib/ > swiftpli_mti.dll > # ** Error: (vsim-3193) Load of "d:\Xilinx91i\smartmodel\nt > \installed_nt/lib/pcnt.lib/swiftpli_mti.dll" failed: DLL > dependent library not found. > # ** Error: (vsim-PLI-3002) Failed to load PLI object file Hi, Please follow all the instructions in Solution Record: 24800. Pay specific attention to the part about putting the LMC_HOME in the path variable. Thanks DuthArticle: 117786
I understand that the inventor of the FPGA was a Ross Freeman, who died aged 45, tragically just 5 years after he co-counded Xilinx. Does anyone have more details of him? Best regards.Article: 117787
fpgabuilder wrote: > Actually SystemC is open-source and I may just be able to do > everything that you are doing in SMIL with a C++ library. The > interfaces would plug straight into your code that is running on > individual SBCs. Synthesis maybe a problem. I'd be curious to know > things that you are able to do with SMIL that you cannot do with > SystemC. > > http://www.systemc.org/web/sitedocs/library_overview.html > > Best, > -sanjay > I think I didn't describe what I'm trying to do very well. The way I see it, SMIL would be used along with something like SystemC. I really wanted SMIL to describe interactions between systems. The functionality of the systems would be created using currently existing tools with SystemC being an example of one. SMIL is less of a language and more of a tool that allows you to describe interactions. SMIL then generates a communication library based on your description. SMIL currently uses TCP/IP as the communication medium, but eventually I'd like to support other communication paths such as CAN, serial ports, etc. What I'm really trying to do is define a way to send messages (SMIL events) between these heterogeneous systems as simply and cleanly as possible. When I talk about VHDL generation, I mean I'd like to generate VHDL glue that would all events to pass directly to FPGA hardware. For example: Let's say a system consists of a Linux box and an Altera FPGA running a NiosII and eCos (I use this example because it's sitting on my desk ;-) Today, SMIL can generate code for both the Linux box and the Nios system and these two systems can communicate with each other. Nothing fancy here, but SMIL also generates code to do event timing, tracing, etc. which helps me look at performance bottlenecks, etc. SMIL also can generate code to create threads of execution. In one example I'm working on I have 16 threads of execution and event interactions defined between them. Some are running on the Linux box and some are running on the Nios. The SMIL code for that is about 600 lines. The bulk of the "application" code would be written in C or C++. Where it gets more interesting for me is I'd like to generate enough VHDL to allow the Linux box to send events to the FPGA (probably through the Nios) and visa versa. Again, the main "application" code for the FPGA would be SystemC, VHDL, etc. and written outside of SMIL. SMIL would just describe and implement the interfaces, tracing, etc. I'm not trying to reinvent any wheels. I'm just trying to address a problem that I've seen and found interesting. -RichArticle: 117788
Hello all: I have a question regarding using SysGen to create a co-processor that's used in a microblaze design. I'm using EDK v9.1 through the base system builder wizard to create a design used on a Xilinx ML401 dev. board. I've already generated a simple pcore and connected that to the microblaze proc. in EDK. Data are being passed from MB -> pcore and pcore -> MB through shared memory (using the "from register" and "to register" in SysGen). Using the provided function calls for communicating from MB -> pcore, I do the following: findavg_sm_0_Write(FINDAVG_SM_0_D0,FINDAVG_SM_0_D0_DIN, datasamp[0]); findavg_sm_0_Write(FINDAVG_SM_0_D1,FINDAVG_SM_0_D1_DIN, datasamp[1]); findavg_sm_0_Write(FINDAVG_SM_0_D2,FINDAVG_SM_0_D2_DIN, datasamp[2]); etc. To check performance, I start timer, do function call to write shared memory, then read value from timer. So it's just: //start timer findavg_sm_0_Write(FINDAVG_SM_0_D0,FINDAVG_SM_0_D0_DIN, datasamp[0]); //read count register I'm seeing that it takes 28 clock cycles to pass a 16-byte word from MB -> pcore in this way. This seems *way* too long. To improve performance, the API documents that were generated when I created the pcore suggest to remove this line in the xparameters.h file: #define FINDAVG_SM_0_SG_ENABLE_FSL_ERROR_CHECK I did that, but it doesn't help. I didn't do anything special regarding connecting my pcore to the MB. Just added it through the Hardware -> Configure coprocessor... tool in EDK which connects the pcore to MB through an FSL. Has anyone investigated this and can share any words of wisdom? thanks, JoelArticle: 117789
Sorry...typo 16-bit word (not "16-byte word") in passing data from MB -> pcore. On Apr 10, 11:07 am, "eejw" <wilder_j...@hotmail.com> wrote: > Hello all: > > I have a question regarding using SysGen to create a co-processor > that's used in a microblaze design. I'm using EDK v9.1 through the > base system builder wizard to create a design used on a Xilinx ML401 > dev. board. > > I've already generated a simple pcore and connected that to the > microblaze proc. in EDK. Data are being passed from MB -> pcore and > pcore -> MB through shared memory (using the "from register" and "to > register" in SysGen). > > Using the provided function calls for communicating from MB -> pcore, > I do the following: > > findavg_sm_0_Write(FINDAVG_SM_0_D0,FINDAVG_SM_0_D0_DIN, datasamp[0]); > findavg_sm_0_Write(FINDAVG_SM_0_D1,FINDAVG_SM_0_D1_DIN, datasamp[1]); > findavg_sm_0_Write(FINDAVG_SM_0_D2,FINDAVG_SM_0_D2_DIN, datasamp[2]); > etc. > > To check performance, I start timer, do function call to write shared > memory, then read value from timer. > > So it's just: > > //start timer > findavg_sm_0_Write(FINDAVG_SM_0_D0,FINDAVG_SM_0_D0_DIN, datasamp[0]); > //read count register > > I'm seeing that it takes 28 clock cycles to pass a 16-byte word from > MB -> pcore in this way. This seems *way* too long. > > To improve performance, the API documents that were generated when I > created the pcore suggest to remove this line in the xparameters.h > file: > > #define FINDAVG_SM_0_SG_ENABLE_FSL_ERROR_CHECK > > I did that, but it doesn't help. > > I didn't do anything special regarding connecting my pcore to the MB. > Just added it through the Hardware -> Configure coprocessor... tool in > EDK which connects the pcore to MB through an FSL. > > Has anyone investigated this and can share any words of wisdom? > > thanks, > JoelArticle: 117790
Hello, I have put up an article on our web site that describes a RISC CPU IP Core that was created for one of our clients: http://www.summitsoftconsulting.com/Pic10IpCore.htm The RISC IP Core is instruction-compatible with the Microchip PIC10F200-series of microcontrollers. Full design documentation is available as well as full Verilog source code (including a full set of test benches). I have included you VHDL people in this post since the design is a generic Controller-Datapath design that easily can be ported to VHDL. Thanks, /John. -------------------------------------------- John Gulbrandsen, Summit Soft Consulting Professional Windows Systems Programming 26895 Aliso Creek Rd. Suite B504 Aliso Viejo, CA 92656-5301 Phone (877) 839-2543 Fax (877) 349-1818 John.Gulbrandsen (a t) SummitSoftConsulting (d o t ) com --------------------------------------------Article: 117791
> I understand that the inventor of the FPGA was a Ross Freeman, who > died > aged 45, tragically just 5 years after he co-counded Xilinx. > > Does anyone have more details of him? Have you seen this: http://www.xilinx.com/company/history.htm#begin Some time ago I was wondering about Jim Barnett because I could found no mentioning of him except that he co-founded Xilinx?!? ThomasArticle: 117792
Thanks for the help, I will try to test all the solutions to see which one fits my needs. Thanks a lot, AmishArticle: 117793
On Apr 10, 1:10 am, "CMOS" <manu...@millenniumit.com> wrote: > is there any opensource alternatives to platformstudio and microblaze > development? There is a WISHBONE Builder project at opencores.org: http://www.opencores.org/projects.cgi/web/wb_builder/overview I have not used it, so I can not compare it to EDK. There is also a collection of processors and other cores that use the WISHBONE interface: http://www.opencores.org/browse.cgi/by_category Another site you might find interesting is the gEDA site at: http://www.geda.seul.org/ This is a collection of GPL EDA tools. Regards, John McCaskill www.fastertechnology.comArticle: 117794
Yes, I saw that, (thanks). Really I wondered how he died so young. It's a sobering thought that in ~10 years I'll be as old as he was when he died, and I haven't yet done anything that I'm *really* proud of.Article: 117795
fancier, "Ross Freeman, along with Bernie Vonderschmitt and Jim Barnett, founded Xilinx in February 1984. It is Ross's invention, the FPGA, that is the foundation of our company and the basis for a multi-billion-dollar industry. Quite literally, if it were not for Ross and his vision, Xilinx would not exist. "Ross was a brilliant engineer. He was formally educated in physics with a BS from Michigan State and an MS from the University of Illinois. He began his IC design career at Teletype. He joined Zilog when it was a startup. By the time he reached his early 30's he was the Director of Engineering for the Components Division at Zilog, in charge of all engineering activities for the division. In 1986, while the VP of Engineering here at Xilinx, the San Jose Mercury News named Ross one of Silicon Valley's dozen Rising Stars (along with the likes of Sun's Bill Joy and Cypress' T. J. Rodgers). "Unlike many very bright engineers, Ross was not a prima donna. In fact, he was quite the opposite. He was unassuming and approachable. He heaped praise on others, often when he was the person deserving of the recognition. He was supremely self-confident, without being arrogant or cocky. "But more than that, Ross was a good human being. Before he started his professional career, he was a Peace Corps volunteer, teaching math and electronics in Ghana. He treated everyone fairly and with respect. He was extremely loyal. Quite simply, he cared about people. "As stated before, if it were not for Ross's vision Xilinx would not exist. But equally important, if it were not for Ross and Bernie's shared values and beliefs, Xilinx would not be the special company that it is. Please take a moment and remember Ross." From an internal website here at Xilinx. I thought it appropriate that the newsgroup understand who Ross was, what he accomplished, and what a role model he is to all engineers here at Xilinx. AustinArticle: 117796
I am trying to work through the "EDK 8.2 MicorBlaxe Tutorial in Spartin 3" When I get to the point of "Generate Programming File" to implement the design on page 26, It appears that ISE does not call XPS to generate the EDK to create the directories "hdl, implemtation, & synthesis". I get the following error message; ERROR:HDLParsers:3264 - Can't read file "E:/users/sgwillis/Engineering/xilinx/designs/ edk82_mb_spart3/project_navigator/../hdl/system.vhd": No such file or directory. I am using the ISE 8.2.03i web pack with the EDK 8.2.02i. EDK 8.2i and SP2 was installed after ISE 8.2i and SP3 on a Windows XP Pro computer with SP2 and multiple patches. Any ideas/hints would be greatly appreciated. Thanks. V/R ScottArticle: 117797
Hi everybody,
i have a missunderstanding of the flip flop behavior:
usually the output of a flip flop is assigned its input of the
previous clock period (that's true for internal signal), but i
observed that when i connect the flip flop to an external input the
output of the flip flop is assigned to the input of the same clock
period: it works like an "asynchronous flip flop", an example of the
problem is described below.
anyone of you can explain me the problem or the behavior of this flip
flop please?
thank you!!!
clk : 01010101010101010101
input : 00001111100000111111
ouput : U0000111110000011111 (expected)
output:00000111110000011111 (obtaine)
d=E9claration of the flip flop
process (Reset_n, Clk)
begin
if (reset_n=3D'0') then
Output <=3D'0';
elsif(clk'event and clk=3D'1') then
output <=3Dinput;
end if;
end process;
Article: 117798Thank you, Austin. I agree 100% with these words, even if they sound a bit corny. I came to Xilinx 19 years ago, after some dog-eat-dog years at Fairchild and AMD with its domineering president Jerry Sanders. Coming to Xilinx was a very positive experience. Ross Freeman and Bernie Vonderschmitt were two of the smartest, and simultaneously the two most decent and caring human beings I ever met. They created a company culture that attracted many of us, and kept us here at Xilinx, the best company I ever worked for. There are few subjects that I feel this unequivocally enthusiastic about, and leave the usual engineering cynicism behind. Peter Alfke On Apr 10, 11:22 am, Austin Lesea <aus...@xilinx.com> wrote: > fancier, > > "Ross Freeman, along with Bernie Vonderschmitt and Jim Barnett, founded > Xilinx in February 1984. It is Ross's invention, the FPGA, that is the > foundation of our company and the basis for a multi-billion-dollar > industry. Quite literally, if it were not for Ross and his vision, > Xilinx would not exist. > > "Ross was a brilliant engineer. He was formally educated in physics with > a BS from Michigan State and an MS from the University of Illinois. He > began his IC design career at Teletype. He joined Zilog when it was a > startup. By the time he reached his early 30's he was the Director of > Engineering for the Components Division at Zilog, in charge of all > engineering activities for the division. In 1986, while the VP of > Engineering here at Xilinx, the San Jose Mercury News named Ross one of > Silicon Valley's dozen Rising Stars (along with the likes of Sun's Bill > Joy and Cypress' T. J. Rodgers). > > "Unlike many very bright engineers, Ross was not a prima donna. In fact, > he was quite the opposite. He was unassuming and approachable. He heaped > praise on others, often when he was the person deserving of the > recognition. He was supremely self-confident, without being arrogant or > cocky. > > "But more than that, Ross was a good human being. Before he started his > professional career, he was a Peace Corps volunteer, teaching math and > electronics in Ghana. He treated everyone fairly and with respect. He > was extremely loyal. Quite simply, he cared about people. > > "As stated before, if it were not for Ross's vision Xilinx would not > exist. But equally important, if it were not for Ross and Bernie's > shared values and beliefs, Xilinx would not be the special company that > it is. Please take a moment and remember Ross." > > From an internal website here at Xilinx. > > I thought it appropriate that the newsgroup understand who Ross was, > what he accomplished, and what a role model he is to all engineers here > at Xilinx. > > AustinArticle: 117799
Hi all, I have a potential (hobby) project, where I'm looking at needing, in effect, a CPLD and a µC that can share memory. +5 V I/O tolerance is necessary (for about 52 signals coming into the board), and I would like to keep the power supply complexity to a minimum since I'm really a software guy and don't particularly trust my board layout skills. Anyway, I was looking at using an Atmel FPSLIC part, but it looks like the tools are prohibitively expensive. I was wondering if anyone knows of a similar part that would be less expensive once the tools are accounted for? The alternatives seem to be using a Cyclone or Spartan big enough to integrate the whole design including µC, but they require complex power supplies and external voltage converters, or cobble something together from multiple parts. -hpa
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