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Messages from 120350

Article: 120350
Subject: Difference between DCM and PMCD
From: Ahmed <ahmedongun@gmail.com>
Date: Tue, 05 Jun 2007 13:59:50 -0700
Links: << >>  << T >>  << A >>

Hi,

I will appreciate if someone clarify for me the difference between DCM
and PMCD. When do you need to use both together (cascaded)?

Thanks,

Ahmed


Article: 120351
Subject: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
From: Totally_Lost <air_bits@yahoo.com>
Date: Tue, 05 Jun 2007 14:14:22 -0700
Links: << >>  << T >>  << A >>
On Jun 4, 6:45 pm, Ray Andraka <r...@andraka.com> wrote:
> Totally_Lost wrote:
> > I've been looking at the various core/macro generators and they all
> > seem horribly large and slow, almost like student designs. Has anyone
> > seriously taken a good look at hand fitting multipliers and squarers
> > into Altera/Xilinx FPGA's?
>
> If you haven't already, you might look at the multiplication in FPGAs
> page on my website athttp://www.andraka.com/multipli.htm.  The partial
> product LUT multipliers are about as efficient as you are going to get
> with the FPGA LUT structure.  If you can use multiple cycles, then you
> can combine that with sequential multiplication to make the multiplier
> smaller at the expense of more clock cycles per product.

Hi Ray,

I certainly had took another cruise past that web site, as it's
certainly a useful resource. The logic depths to build a wide
64x64=>128 bit multiplier that way do get a bit excessive, of which
some pipelining does help a bit. The last time I faced this for a
smaller 20x20=>40 bit multiplier I did better with an odd carry-save
construction using the carry chain in a non-standard way, but took a
couple days in the fpga editor to pack cleanly. The 64x64 isn't
looking nearly as fun, so I was looking to see if someone has already
been down this path.


Article: 120352
Subject: Re: Lattice XP2 finally announced
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Wed, 06 Jun 2007 09:33:33 +1200
Links: << >>  << T >>  << A >>
Antti wrote:

> On 5 Jun., 16:33, austin <aus...@xilinx.com> wrote:
> 
>>Antti,
>>
>>Yes, Steve worked at Triscend.
>>
>>Triscend had reached a point where it was either close the doors, and go
>>out of business and put everyone on the street; or call up folks at
>>Xilinx and ask if their excellent staff of employees could possibly find
>>a home.
>>
>>The doors still closed.
>>
>>Since some were X-Xilinx employees, and we knew what excellent
>>designers, etc. they were, it was a simple matter to ask them to come to
>>2100 Logic Drive the next day, rather than start looking for jobs.
>>
>>We did the same with DynaChip.
>>
>>The Triscend group has distinguished themselves with valuable additions
>>to V5.
>>
>>The Dynachip group is responsible for the design excellence of Virtex II
>>and continuing.
>>
>>It is not our fault that being a FPGA vendor is incredibly difficult.
>>The history is littered with those who failed.  Big names, like Intel,
>>ATT Microelectronics, Motorola have all tried.
>>
>>And, the valley is littered with the stock of little shops that also failed.
>>
>>Austin
> 
> 
> eh ok, maybe.
> 
> still a bit pitty that ARM is not taking off in FPGAs as Triscend
> closed doors and Altera discontinued the products.

Hi Antti,
  Yes, but for a while customers did have a choice of both, and customers
drove the decision by choosing NIOS over ARM. ARM was just too costly
to do as a SoftCPU, and too restrictive in a HardCPU.

  So the FPGA optimised SoftCPUs won.

  Triscend had the same problems as the now trailing FpSLIC.
Everyone looks and say 'yeah, nice idea', but the silicon struggles to 
make actual design wins, because you have locked three variables in 
silicon, and so have a VERY SMALL market sweet spot, as well as
being VERY single-source locked.
I'd call them a Salesman's device, not an Engineer's device :)

  The recent growth in FLASH 32 bit Microcontrollers is even putting
pressure on the SoftCPU design decision.

  Some recent examples that have impressed me are

ARM9+FLASH with 'the works':
[Atmel have one too, somewhere, in 're-work']
http://www.hitex.com/str9-comstick/con-str9-comstick.html

Floating Point DSP + FLASH :
http://focus.ti.com/docs/pr/pressrelease.jhtml?prelId=sc07103

Atmel AT91CAP - picks the higher volume, mask FPGA Niche,
http://www.atmel.com/dyn/corporate/view_detail.asp?FileName=CAP9_5_21.html

AVR32 - FLASH+EtherNET+OTG.USB
http://www.atmel.com/dyn/corporate/view_detail.asp?ref=&FileName=AT32uC3AFamily_4_2.html&SEC_NAME=Product

-jg




Article: 120353
Subject: Re: Topics and Ideas for BS Project
From: ARH <haghdoost@gmail.com>
Date: Tue, 05 Jun 2007 14:49:17 -0700
Links: << >>  << T >>  << A >>
Hans,

Thank you very much for your useful explanations.

I agree with you about systemC abilities and have to know C++ didn't
change my idea about this language because I learned C++ as the first
programming language.

Also I have no problem with learning any new language in my project
and I think this would be a good chance for me, for this reason I
mention SystemC and SoC design because I think these are new area in
Hardware Design that have shiny  future.


I have seen your website , www.ht-lab.com and I want to congratulate
you for your effort. I am one of the interest person in your CPU86
project. I involved to this project several days, last week and have
three question/offer about it :

1. Did you ever think to system level description ? there are several
IP-core from Ht-lab and Opencores.org that could be together in a
system level design.

2. what is the advantages of x86 CPU IP-core vs. other CPU IP that use
ordinary in SoCs (like embedded PowerPC cores)

3. in which places in this project you need contributor (especially in
Verilog version wrote by Antti Lucas because I prefer Verilog rather
VHDL)



ARH


Article: 120354
Subject: Re: Build error for multiprocessor sytem.
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Wed, 06 Jun 2007 08:02:53 +1000
Links: << >>  << T >>  << A >>
Hi Shant,

Shant wrote:

> My basic version of design has two interconnected microblaze, FSL has
> been used for interconnection.

> There is one application on each microblaze such that frist writes to
> second then the second microblaze sends some data back to the first
> one.

Sounds reasonable.

> My problem is that while performing Build all user application, it
> builds the application present in first microblaze but throws errror
> while building the application in second microblaze.

Details of the error message would be helpful!

John

Article: 120355
Subject: Re: Virtex4 CLKX2 DCM Jitter
From: austin <austin@xilinx.com>
Date: Tue, 05 Jun 2007 15:06:02 -0700
Links: << >>  << T >>  << A >>
Answered off-line,

Lots of stuff to go over.

Xapp 623 is the start of the process of review.

If IOs are causing it, then decoupling of the IOs, and ground bounce, is 
critical.

Austin

Article: 120356
Subject: Re: Lattice XP2 finally announced
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Wed, 06 Jun 2007 10:08:16 +1200
Links: << >>  << T >>  << A >>
  besides these Microcontrollers, I see the MPU offerings are also 
bringing pressure on the 'FPGA with HardCPU' decision.

This new device from AMCC, has some impressive peripherals and MIPS/$$ 
ratios.

405EXr:
  1,000 DMIPS
  PCI Express
  Gigabit Ethernet
  USB 2.0 On-the-Go 480 Mbps
  pricing will start at $14 in 10Ku volumes

http://investor.amcc.com/releasedetail.cfm?ReleaseID=247168

-jg


Jim Granville wrote:
<snip>
>  The recent growth in FLASH 32 bit Microcontrollers is even putting
> pressure on the SoftCPU design decision.
> 
>  Some recent examples that have impressed me are
> 
> ARM9+FLASH with 'the works':
> [Atmel have one too, somewhere, in 're-work']
> http://www.hitex.com/str9-comstick/con-str9-comstick.html
> 
> Floating Point DSP + FLASH :
> http://focus.ti.com/docs/pr/pressrelease.jhtml?prelId=sc07103
> 
> Atmel AT91CAP - picks the higher volume, mask FPGA Niche,
> http://www.atmel.com/dyn/corporate/view_detail.asp?FileName=CAP9_5_21.html
> 
> AVR32 - FLASH+EtherNET+OTG.USB
> http://www.atmel.com/dyn/corporate/view_detail.asp?ref=&FileName=AT32uC3AFamily_4_2.html&SEC_NAME=Product 


Article: 120357
Subject: Re: Virtex4 CLKX2 DCM Jitter
From: "MikeJ" <mikej@fpgaarcade.nospam.com>
Date: Tue, 05 Jun 2007 23:00:49 GMT
Links: << >>  << T >>  << A >>
Thanks Austin,
/Mike

"austin" <austin@xilinx.com> wrote in message 
news:f44mo1$rae2@cnn.xilinx.com...
> Answered off-line,
>
> Lots of stuff to go over.
>
> Xapp 623 is the start of the process of review.
>
> If IOs are causing it, then decoupling of the IOs, and ground bounce, is 
> critical.
>
> Austin 



Article: 120358
Subject: Re: Virtex4 CLKX2 DCM Jitter
From: "John Retta" <jretta@rtc-inc.com>
Date: Wed, 06 Jun 2007 00:30:38 GMT
Links: << >>  << T >>  << A >>
And one technique that Xilinx recommends for lessening
effects of ground bounce is to drive unused adjacent IO
to GND on the PWB, and drive these as outputs on the
FPGA. ie tie the input to the obuf to logic 0.
Regards,
John Retta
Retta Technical Consulting Inc.
Colorado Based Xilinx Consultant

email : jretta@rtc-inc.com
web :  www.rtc-inc.com


"austin" <austin@xilinx.com> wrote in message 
news:f44mo1$rae2@cnn.xilinx.com...
> Answered off-line,
>
> Lots of stuff to go over.
>
> Xapp 623 is the start of the process of review.
>
> If IOs are causing it, then decoupling of the IOs, and ground bounce, is 
> critical.
>
> Austin 



Article: 120359
Subject: Re: Topics and Ideas for BS Project
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Tue, 05 Jun 2007 16:56:28 -0800
Links: << >>  << T >>  << A >>
ARH wrote:

> 1. I have think that all of the C based design flow ends to an HDL
> description in low level of design and C isn't a suitable language for
> designing a hardware because it's naturally sequential and limited in
> many cases like X or Z data representation. May be your intent is
> systemC ?

I agree.  To me the main advantage would be to use existing
C programs, but the usual hardware implementation of an algorithm
is very different from the software implementation.

I have been told that another reason is that it is too hard for
engineers to learn and understand both C and verilog.  This I also
don't believe, but maybe that is just me.

-- glen


Article: 120360
Subject: Re: Virtex4 CLKX2 DCM Jitter
From: Brian Davis <brimdavis@aol.com>
Date: Tue, 05 Jun 2007 19:14:30 -0700
Links: << >>  << T >>  << A >>
Mike,

 Assuming you've already checked the likely suspects,
here are some random thoughts on jitter troubleshooting.
(FWIW, many of these will break other things and are not
suggested as a fix, just a troubleshooting aid )

 A) Try to distinguish whether the DCM input clock is
   affected when the I/O switches; or, if the DCM
   itself is being affected; or, if both are

   - clock your DDR clock forwarding flop directly from
     the input clock, with no DCM: does it still get
     the jitters when the QDR I/O switching starts?

     i.e.  100 Mhz input clock -> BUFG -> DDR output

     ( IIRC, you don't need to fiddle with DIFF_OUT buffers
     for global clock forwarding in V4 due to the already
     differential global clock distribution )

   - if you have another clock input ( esp. in a quiet bank ),
     temporarily clock the QDR logic from that ( with and
     without DCM ) and see if the jitter changes

 B) DCM Duct Tape

   - LOC the DCM to the other DCM sites on the chip;
     see if that affects the jitter

     Even if it's not an optimum LOC for the DCM because of
     the GCLK pin location, and there needs to be a long clock
     route to get there, putting the DCM on the other side
     of the chip away from I/O activity may help your jitter
     ( but not meet system timing )

   - change FACTORY_JF as described in Answer Record 13756

     If decide to try CLKFX, see AR 21594 and AR 18181
     ( V2/S3 era advice, not sure how it applies to V4 )

   - change DCM DESKEW_ADJUST to SOURCE_SYNCHRONOUS to turn off
     the internal DCM feedback delay element (more V2 era advice)
     ( see pages 4-5 of XAPP259 )

Other questions:

 - Do you have any spare LVDS input/outputs elsewhere
   on the chip ? ( handy for clock troubleshooting )

 - If you run a 'hammer' test 0000 <=> FFFF instead of
   pseudorandom patterns on the QDR address/data lines,
   does the jitter get much worse and/or the DCM unlock ?
   ( also try changing the toggle rate, 1,2..N clocks )

   FWIW, my S3 Starter Kit SRAM memory test that used a
   x2 DCM would unlock on hammer patterns, even with slow
   slew I/O meeting SSO limits, unless the DCM was LOC'd
   to the other side of the chip away from the SRAM I/O.

 - Is the QDR interface bandwidth sufficient to allow for
   Asteroids vector generator emulation at 1080p resolution?

Brian


Article: 120361
Subject: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
From: Totally_Lost <air_bits@yahoo.com>
Date: Tue, 05 Jun 2007 20:16:13 -0700
Links: << >>  << T >>  << A >>
On Jun 5, 11:56 am, Thomas Womack <twom...@chiark.greenend.org.uk>
wrote:

> I agree that partial-product LUT multipliers are pretty much optimal for
> multiplying three-bit quantities.  For wide multipliers, I think the
> relevant literature is the multi-precision arithmetic stuff by people like
> Knuth; you can multiply two 64-bit numbers by using three 32x32 multipliers
> in parallel. Relevant search terms are Karatsuba and Toom-Cook.

Thanks Tom,

I'll explore optimizations around that structural model as well, and
compare with the carry-save model optimized around the extra half
adders and mux in the  carry chain hardware that worked well for the
20x20 multiplier.


Article: 120362
Subject: Weird! sysace_fwrite() cannot be found!!!???
From: Yao Sics <yao.sics@gmail.com>
Date: Wed, 06 Jun 2007 03:24:33 -0000
Links: << >>  << T >>  << A >>
Hi everyone,

I run into a weird erorr. sysace_fwrite() cannot be found.
---------------------------------------------------------------------------
undefined reference to `sysace_fwrite' collect2: ld returned 1 exit
status
make: *** [CF_demo/executable.elf] Error 1
---------------------------------------------------------------------------

Xilfatfs lib is chosen and included in the main.c, as follow. If I
comment out sysace_fwrite, no errors come up during compilation. How
come can edk only find sysace_fread but sysace_fwrite? Any input would
be appreciated!

Thanks in advance,


Yao



----------------------------------------------------------------------------------------------------------------------------------------------------------------------
#include "xparameters.h"
#include "xutil.h"
#include "xio.h"

#include <sysace_stdio.h>


int main(void)
{

	char* file1 = "input.bin";
	char* file2 = "result.bin";

	SYSACE_FILE* infile1, *infile2;

	int i, numread, numwrite;

	unsigned char Buffer[1];

	/** Open the dummy files and read a data**/
	infile1 = sysace_fopen(file1, "r");
	infile2 = sysace_fopen(file2, "w");

	for(i=0; i<49152; i++)
	{
		numread  = sysace_fread(Buffer, 1, 1, infile1);
		numwrite = sysace_fwrite(Buffer, 1, 1, infile2);
	}

	sysace_fclose(infile1);
	sysace_fclose(infile2);

	return 0;
}


Article: 120363
Subject: Re: How to Access CompactFlash by using SystemACE?
From: Yao Sics <yao.sics@gmail.com>
Date: Wed, 06 Jun 2007 03:26:56 -0000
Links: << >>  << T >>  << A >>
On Jun 5, 10:40 pm, Jon Beniston <j...@beniston.com> wrote:
> On 5 Jun, 13:59, Yao Sics <yao.s...@gmail.com> wrote:
>
>
>
>
>
> > Hi Guys,
>
> > I was trying to access CF by using API sysace_fread and
> > sysace_fwrite.
> > I checked xilfatfs library in the software platform settings and
> > #include <sysace_stdio.h>, but edk still complains.
>
> > -----------------------------------------------------------------------=
----=AD=AD=AD--------------------------------------------
> > Running DRCs for OSes, Drivers and Libraries ...
> > ERROR:MDT - issued from TCL procedure
> > "::sw_xilfatfs_v1_00_a::xilfatfs_drc" line 15
> >     xilfatfs () - Sysace HW module not present or not accessible from
> > this
> >    processor. FATfs cannot be used without this module
>
> > ERROR:MDT - Error while running DRC for processor ppc405_1...
>
> > make: *** [ppc405_0/lib/libxil.a] Error 2
> > -----------------------------------------------------------------------=
----=AD=AD=AD--------------------------------------------
>
> > Has anyone experienced this before? Any input would be appreciated!
>
> > Thanks in advance,
>
> > Yao
>
> Do you have the system ace module accessible over the bus from your
> processor?
>
> Jon- Hide quoted text -
>
> - Show quoted text -

Hi Jon,

The previous problem was solved. I was supposed to use ppc405_0, not
ppc405_1. I think thats why edk complains. A silly mistake.

But, I run into another weird erorr. sysace_fwrite() cannot be found.
---------------------------------------------------------------------------
undefined reference to `sysace_fwrite' collect2: ld returned 1 exit
status
make: *** [CF_demo/executable.elf] Error 1
---------------------------------------------------------------------------

Xilfatfs lib is chosen and included in the main.c, as follow. If I
comment out sysace_fwrite, no errors come up during compilation. How
come can edk only find sysace_fread but sysace_fwrite? Any input
would
be appreciated!


Thanks in advance,


Yao


---------------------------------------------------------------------------=
=AD------------------------------------------------------------------------=
---=AD----------------
#include "xparameters.h"
#include "xutil.h"
#include "xio.h"


#include <sysace_stdio.h>


int main(void)
{


        char* file1 =3D "input.bin";
        char* file2 =3D "result.bin";


        SYSACE_FILE* infile1, *infile2;


        int i, numread, numwrite;


        unsigned char Buffer[1];


        /** Open the dummy files and read a data**/
        infile1 =3D sysace_fopen(file1, "r");
        infile2 =3D sysace_fopen(file2, "w");


        for(i=3D0; i<49152; i++)
        {
                numread  =3D sysace_fread(Buffer, 1, 1, infile1);
                numwrite =3D sysace_fwrite(Buffer, 1, 1, infile2);
        }


        sysace_fclose(infile1);
        sysace_fclose(infile2);


        return 0;




Article: 120364
Subject: Re: Weird! sysace_fwrite() cannot be found!!!???
From: Yao Sics <yao.sics@gmail.com>
Date: Tue, 05 Jun 2007 20:50:57 -0700
Links: << >>  << T >>  << A >>
On Jun 6, 11:24 am, Yao Sics <yao.s...@gmail.com> wrote:
> Hi everyone,
>
> I run into a weird erorr. sysace_fwrite() cannot be found.
> -------------------------------------------------------------------------=
--
> undefined reference to `sysace_fwrite' collect2: ld returned 1 exit
> status
> make: *** [CF_demo/executable.elf] Error 1
> -------------------------------------------------------------------------=
--
>
> Xilfatfs lib is chosen and included in the main.c, as follow. If I
> comment out sysace_fwrite, no errors come up during compilation. How
> come can edk only find sysace_fread but sysace_fwrite? Any input would
> be appreciated!
>
> Thanks in advance,
>
> Yao
>
> -------------------------------------------------------------------------=
--=AD----------------------------------------------------------------------=
-----=AD----------------
> #include "xparameters.h"
> #include "xutil.h"
> #include "xio.h"
>
> #include <sysace_stdio.h>
>
> int main(void)
> {
>
>         char* file1 =3D "input.bin";
>         char* file2 =3D "result.bin";
>
>         SYSACE_FILE* infile1, *infile2;
>
>         int i, numread, numwrite;
>
>         unsigned char Buffer[1];
>
>         /** Open the dummy files and read a data**/
>         infile1 =3D sysace_fopen(file1, "r");
>         infile2 =3D sysace_fopen(file2, "w");
>
>         for(i=3D0; i<49152; i++)
>         {
>                 numread  =3D sysace_fread(Buffer, 1, 1, infile1);
>                 numwrite =3D sysace_fwrite(Buffer, 1, 1, infile2);
>         }
>
>         sysace_fclose(infile1);
>         sysace_fclose(infile2);
>
>         return 0;
>
>
>
> }- Hide quoted text -
>
> - Show quoted text -


The problem was solved by switching on a serect setting inside
Software Platform Setting/OS and Libraries/Configuration for
Libraries, expand it. Turn on CONFIG_WRITE.

Hope this would help someone who runs into the same problem.

Yao




Article: 120365
Subject: Re: Weird! sysace_fwrite() cannot be found!!!???
From: Siva Velusamy <siva.velusamy@xilinx.com>
Date: Tue, 05 Jun 2007 20:58:30 -0700
Links: << >>  << T >>  << A >>
Yao Sics wrote:
> Hi everyone,
> 
> I run into a weird erorr. sysace_fwrite() cannot be found.
> ---------------------------------------------------------------------------
> undefined reference to `sysace_fwrite' collect2: ld returned 1 exit
> status
> make: *** [CF_demo/executable.elf] Error 1
> ---------------------------------------------------------------------------
> 
> Xilfatfs lib is chosen and included in the main.c, as follow. If I
> comment out sysace_fwrite, no errors come up during compilation. How
> come can edk only find sysace_fread but sysace_fwrite? Any input would
> be appreciated!
> 

Make sure you have write support enabled. Check your s/w platform settings.

-Siva

Article: 120366
Subject: How to Find false path in a design
From: VIPS <thevipulsinha@gmail.com>
Date: Wed, 06 Jun 2007 04:07:14 -0000
Links: << >>  << T >>  << A >>
Hi Guys

We have been knowing the false path and its nature but i am confused
as to how to identify a false path in a design having say 100 modules.
We know that false path as defination that it is the path that is
never executed or sanitisized henceforth it is not included in the
STA . But the million dollar question is if the design is really big
the how can one it so as to name it in the synthesis. I want to know
the steps followed in the industry. I will value your comments and pls
do upload some relevant material or any case study

Thanks in advance
Vips


Article: 120367
Subject: Re: How to Find false path in a design
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Tue, 05 Jun 2007 21:25:46 -0700
Links: << >>  << T >>  << A >>
On Wed, 06 Jun 2007 04:07:14 -0000, 
VIPS <thevipulsinha@gmail.com> wrote:

>We have been knowing the false path and its nature but i am confused
>as to how to identify a false path in a design having say 100 modules.
[...]
> I want to know the steps followed in the industry.

Google for "false path" is a good start.  Here's a couple
of places you might look:

PrimeTime, probably the best-known of the many static
timing analysis tools....
http://www.synopsys.com/products/analysis/primetime_ds.html

FishTail, an interesting new tool that uses formal techniques
to identify false and multi-cycle paths....
http://www.fishtail-da.com/

Note, these are not recommendations in any way - just two
products that I happen to be aware of.  I'm sure there are 
many more.  It's not really my field.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 120368
Subject: XILINX IPCore
From: Ace <yasirmm@gmail.com>
Date: Tue, 05 Jun 2007 21:47:26 -0700
Links: << >>  << T >>  << A >>
Hello,

I recently bought a board that has a firewire port that uses PCI32 as
a communication to the TI Link layer chip. I was told that I could
easily communicate with the board by FPGA using Xilinx IPcore. I
followed the steps on "Getting Started User Guide" i.e. inserting the
device id, vendor id values and etc, getting the .ngc file and then
get the .bit file and used iMPACT. However, after several attempts, my
linux machine still could not detect the board.

Does anyone has any suggestion on this?


Cheers!


Article: 120369
Subject: Re: What's the smallest/fastest CLB/Slice/Lut based unsigned integer 64 bit by 64 bit multiplier/squarer design?
From: Totally_Lost <air_bits@yahoo.com>
Date: Tue, 05 Jun 2007 23:14:52 -0700
Links: << >>  << T >>  << A >>
On Jun 4, 6:45 pm, Ray Andraka <r...@andraka.com> wrote:
> Totally_Lost wrote:
> > I've been looking at the various core/macro generators and they all
> > seem horribly large and slow, almost like student designs. Has anyone
> > seriously taken a good look at hand fitting multipliers and squarers
> > into Altera/Xilinx FPGA's?
>
> If you haven't already, you might look at the multiplication in FPGAs
> page on my website athttp://www.andraka.com/multipli.htm.  The partial
> product LUT multipliers are about as efficient as you are going to get
> with the FPGA LUT structure.  If you can use multiple cycles, then you
> can combine that with sequential multiplication to make the multiplier
> smaller at the expense of more clock cycles per product.

Hi Ray ... Just for reference, what would you consider an optimal
number of LUTs/Slices using this approach for an 8x8=>16 and 16x16=>32
multiplier? Thanks


Article: 120370
Subject: Re: XILINX IPCore
From: John Adair <g1@enterpoint.co.uk>
Date: Tue, 05 Jun 2007 23:42:15 -0700
Links: << >>  << T >>  << A >>
A few more details like the board being used would be useful but here
is s a few things to check.

If you are using the PCI core as a Host Bridge and your end is the
main master in the system then you need to configure any PCI based
cards or chips on that PCI bus using configuration cycles.

If you are a plug in card check presence lines are implemented.

Worth checking if you are a Target that would not getting hung or
aborted cycles. Whole bunch of reasons for these. PCI implementations
in PCs are generally not very good at handling errors, like no
response, and generally hang if anything is mildly wrong.

Check your pinout is correct.

John Adair
Enterpoint Ltd.



On 6 Jun, 05:47, Ace <yasi...@gmail.com> wrote:
> Hello,
>
> I recently bought a board that has a firewire port that uses PCI32 as
> a communication to the TI Link layer chip. I was told that I could
> easily communicate with the board by FPGA using Xilinx IPcore. I
> followed the steps on "Getting Started User Guide" i.e. inserting the
> device id, vendor id values and etc, getting the .ngc file and then
> get the .bit file and used iMPACT. However, after several attempts, my
> linux machine still could not detect the board.
>
> Does anyone has any suggestion on this?
>
> Cheers!



Article: 120371
Subject: Re: Virtex4 CLKX2 DCM Jitter
From: mk <kal*@dspia.*comdelete>
Date: Wed, 06 Jun 2007 07:00:29 GMT
Links: << >>  << T >>  << A >>
On Tue, 05 Jun 2007 15:06:02 -0700, austin <austin@xilinx.com> wrote:

>Answered off-line,

Why, are we chopped liver?

Article: 120372
Subject: Re: XILINX IPCore
From: Ben Jackson <ben@ben.com>
Date: Wed, 06 Jun 2007 02:27:38 -0500
Links: << >>  << T >>  << A >>
On 2007-06-06, Ace <yasirmm@gmail.com> wrote:
> get the .bit file and used iMPACT. However, after several attempts, my
> linux machine still could not detect the board.
>
> Does anyone has any suggestion on this?

Is your board fully programmed and responsive to PCI cycles before the
PC BIOS starts looking at the PCI bus?  If it doesn't assert DEVSEL for
the first config read cycle, a modern motherboard will probably take
away its clock and never speak to it again.  Even looking later from an
OS you will not see it since it will not have a clock.

-- 
Ben Jackson AD7GD
<ben@ben.com>
http://www.ben.com/

Article: 120373
Subject: Re: How to Find false path in a design
From: hans64@ht-lab.com
Date: Wed, 06 Jun 2007 00:39:09 -0700
Links: << >>  << T >>  << A >>
On Jun 6, 5:07 am, VIPS <thevipulsi...@gmail.com> wrote:
> Hi Guys
>
> We have been knowing the false path and its nature but i am confused
> as to how to identify a false path in a design having say 100 modules.
> We know that false path as defination that it is the path that is
> never executed or sanitisized henceforth it is not included in the
> STA . But the million dollar question is if the design is really big
> the how can one it so as to name it in the synthesis. I want to know
> the steps followed in the industry. I will value your comments and pls
> do upload some relevant material or any case study
>
> Thanks in advance
> Vips

Hi Vips,

If you are not meeting timing and you have lots and lots of path
failing then save yourself some major pain and get a copy of fishtail.
I played with this software some time ago and I can tell you it is
very powerful. You just feed it your rtl and some constraints and out
come a set of SDC files for false and multi-cycle path. On top of that
if can also generate a set of assertions for you to verify the
generated constraints.

Hans
www.ht-lab.com


Article: 120374
Subject: Install two version of EDK/ISE (8.1, 8.2) in my windows xp?
From: Pablo <pbantunez@gmail.com>
Date: Wed, 06 Jun 2007 00:47:44 -0700
Links: << >>  << T >>  << A >>
Is it possible to install two diferent versions of EDK/ISE, that is,
one EDK/ISE 8.1 and another EDK/ISE 8.2. The reson is that I need the
first one for simulink, but my custom board uses the second one (for
the drivers). I suppose that the problem is the "Path Variable".

Has anyone some experience in this?.

I will post my results as soon as possible.

Regards, Pablo




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