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"Marek Kraft" <sepher_grupy@o2.pl> wrote in message news:1182330434.220400.17630@q69g2000hsb.googlegroups.com... > Hello! > > I have been playing with image processing on FPGA for some time now, > and the results seem interesting (I am working mainly on image > preprocessing and edge/corner detection algorithms). My main research > platform was the S3BOARD from Digilent/Xilinx, but I got to the point, > where RS232, or RS232 <-> USB converters do not offer sufficient speed > (imagine sending a 512x512 image to the board and then waiting for the > results, even in grayscale). Therefore, I'd like to invest some money > in a more advanced evaluation board. For now, the Virtex-4-based Video > Starter Kit seems to be the most reasonable choice for me. Is anyone > here using this kit? I am. > The opinions I have found while googling the net > (like the one here: > http://www.embeddedrelated.com/usenet/embedded/show/54852-1.php) > are however somewhat disencouraging. I'd like to know if it's hard to > develop my own applications for the daughtercard without having to use > the Matlab/Simulink software (just plain HDL). It's not too bad. It's annoying (to me) that Xilinx demos are so tied to Matlab, but they do supply a simple video pass through application (with selection of the various inputs and outputs) that runs standalone on the daughter card. It uses a PicoBlaze to bit-bang the IIC buses. It's in Verilog, but there's not much there so it's fairly easy to translate. If the 2VP7 has enough processing power (and memory) for you, you could just use it standalone. I have the complete VSK, but I'm told by Xilinx folks that one of the new V5 SXT boards works with the daughterboard. If you need more power/memory than the 2VP7 provides you could look into using a ML506 with the Video IO daughterboard. > I also tried to find > some other boards for this task (a solution that is functioning out-of- > the-box would be ideal). The price of boards by Vmetro and > Hitechglobal is an overkill for me. I considered also buying the > XUPV2P board from Digilent design a CameraLink compatible interface > for it, but I fear that V2Pro devices are a bit outdated and Xilinx > will stop supporting this product line. I'd also like to know if it is > better to use dedicated National Semiconductor chips to do the > deserialization, or try to use the IOB/multiple clocks based approach? > Thanks for any suggestions. >Article: 120926
look for picoblaze/kcpsm3 reference design On Jun 20, 10:50 am, Jay <jaycp.iit...@gmail.com> wrote: > You are right Antii, > Hands on experience can only get me exact details about spartan 3e kit > and related peripherals ... thanks for the prompt reply ...Article: 120927
do you plan to release a reference design for spartan 3A700 xilinx starter kit ? On Jun 20, 2:23 pm, "Ben Jones" <ben.jo...@xilinx.com> wrote: > "Guru" <ales.gor...@email.si> wrote in message > > news:1182332483.106686.23690@p77g2000hsh.googlegroups.com... > > > > > That is a great news. > > Is PPC supported in Xilinx ML401 reference design? > > Seems unlikely, as the ML401 has a Virtex-4 LX chip on it, which does not > have an embedded PowerPC block. That would be the FX family, available on > the ML403 board. > > Cheers, > > -Ben-Article: 120928
On Jun 20, 4:04 am, Laurent Pinchart <laurent.pinch...@skynet.be>
wrote:
> Hi Ankit,
>
> > I think it would be really great if you could tell the exact bash script
> > because i would not mind that too..My aim here is to run xilinx on linux
> > it does not matter how it is done..
>
> Ok. Here is a quick howto. I assume you have a basic knowledge of bash
> scripting. If not, there are plenty of documentation available online.
>
> 0. Directories and file names
>
> The examples below are based on the following project directory hierarchy.
>
> /bench
> /vhdl VHDL test benches
> /verilog Verilog test benches
> /rtl
> /vhdl VHDL source files
> /verilog Verilog source files
> /sim
> /rtl_sim
> /bin Simulation scripts
> /log Simulation logs
> /out Simulation results
> /run Simulation resources
> /syn
> /xst
> /bin Synthesis scripts
> /log Synthesis logs
> /out Synthesis results
> /run Synthesis resources
>
> Only VHDL and Verilog sources can be simulated this. Coregen can generate
> VHDL or Verilog simulation modules for (some) IP cores, and schematics can
> be converted to VHDL or Verilog as well.
>
> If you want to adapt the hierarchy to your needs (or even flatten everything
> out), you will have to modify the simulation script.
>
> 1. Environment variables
>
> First of all, make sure your environment variables are up-to-date. The
> Xilinx binary and shared library directories should be accessible through
> $PATH and $LD_LIBRARY_PATH. If you allowed the XilinxISEinstaller to
> modify your system configuration (in /etc) this might be done already.
>
> Check the $XILINX environment variable.
>
> $ echo $XILINX
> /opt/xilinx/ise9.1i/
>
> If the variable is not set, you can just source the configuration script
> (change the path to match yourISEinstallation directory).
>
> $ source /opt/xilinx/ise9.1i/settings.sh
>
> You will have to repeat this step for any shell instance you want to work
> with. You can alternatively add the above line to your bash startup script
> (.bashrc or .bash_profile).
>
> 2. Writing the test bench
>
> The entity under test (EUT) must be instantiated in a portless top-level
> entity that will drive the EUT inputs. I usually write tests in VHDL, but
> you might be able to convert graphical waveforms into VHDL/Verilog code. I
> haven't tested this myself.
>
> The simulation script assumes that your top-level test bench entity is named
> ${module}_tb (for instance, if the EUT entity is named counter, the
> top-level test bench entity should be named counter_tb). This can be
> overridden when running the simulation script, but it's a good idea to
> stick to a coherent naming if you have no reason to do otherwise.
>
> 3. Preparing the simulation resources
>
> Now that your development environment is ready, you will have to prepare the
> simulation resource files.
>
> The simulation script goes in sim/rtl_sim/bin. As the news server doesn't
> seem to like attachments, I included it inline. Let me know if it comes out
> badly.
>
> ---------------- sim.sh --------------------
> #!/bin/sh
>
> set -e
>
> if [ $# -lt 1 ]; then
> self=`basename "$0"`
> echo "Usage: ${self} [options] module"
> exit 1
> fi
>
> do_compile=true
> do_wave=false
> entity=
>
> while [ $# -gt 0 ]; do
> case $1 in
> -no-compile)
> do_compile=false
> ;;
> -wave)
> do_wave=true
> ;;
> -entity)
> entity=$2
> shift
> ;;
> -*)
> echo Invalid argument $1
> exit 1
> ;;
> *)
> module=$1
> ;;
> esac
>
> shift
> done
>
> if [ x${entity} == x ]; then
> entity=${module}_tb
> fi
>
> if $do_compile; then
> vhpcomp -intstyleise-work work=../out/work -prj ../run/${module}.prj
> fuse -work work=../out/work -top ${entity}
> fi
>
> ../out/work/${entity}/lin/xsimbhv_${entity} -tclbatch ../run/${module}.tcl \
> -wavefile ../out/${module}.xwv
>
> if $do_wave; then
> isimwave ../out/${module}.xwv &
> fi
> -----------------------------------------------
>
> Command-line simulation requires a project file (.prj) listing the
> VHDL/Verilog source files and a simulation script (.tcl) with the
> simulation commands.
>
> Here are a sample project file and simulation script that goes in
> sim/rtl_sim/run.
>
> ---------------- sdclk.prj --------------------
> vhdl work ../../../rtl/vhdl/sdclk.ent.vhd
> vhdl work ../../../rtl/vhdl/sdclk.beh.vhd
> vhdl work ../../../bench/vhdl/sdclk.test.vhd
> -----------------------------------------------
>
> ---------------- sdclk.tcl --------------------
> scope /sdclk_tb/
>
> ntrace select -o on -n sd_frequency
> ntrace select -o on -n sd_stop
> ntrace select -o on -n sd_enable
> ntrace select -o on -n sd_clk_in
> ntrace select -o on -n sd_clk_out
>
> ntrace start
> run all
> quit
> -----------------------------------------------
>
> The project file is pretty self-explanatory. Each line adds a source file to
> the simulation. The first keyword is the source file language, the second
> keyword the library which the source will be compiled into, and the third
> keyword is the source file path and name.
>
> The simulation script select signals that will be recorded in the output
> waveform (ntrace directive) and start the simulation. The scope directive
> can be used to navigate in the design hierarchy and select internal
> signals.
>
> More information on theISEsimulatorand the simulation script commands can
> be found at
> http://
> toolbox.xilinx.com/docsan/xilinx9/help/iseguide/mergedProjects/xsim/whnjs.htm
>
> 3. Running the simulation
>
> The simulation script usage is as follows.
>
> ------------ Sample simulation session ----------
> $ ./sim.sh
>
> Usage: sim.sh [options] module
>
> -entity Top entity name. Defaults to module_tb.
> -no-compile Don't compile the sources. Useful if you modified the
> simulation script and want to rerun the simulation without
> recompiling the sources.
> -wave Automatically launch the waveforw viewer upon completion.
>
> $ ./sim.sh -wave sdclk
>
> Compiling vhdl file "rtl/vhdl/sdclk.ent.vhd" in Library work.
> Entity <sdclk> compiled.
> Compiling vhdl file "bench/vhdl/sdclk.test.vhd" in Library work.
> Entity <sdclk_tb> compiled.
> Entity <sdclk_tb> (Architecture <bhv_sdclk_tb>) compiled.
> Compiling vhdl file "rtl/vhdl/sdclk.beh.vhd" in Library work.
> Entity <sdclk> (Architecture <str_sdclk>) compiled.
> Parsing "../run/sdclk.prj": 0.27
> Codegen work/sdclk: 0.00
> Codegen work/sdclk_tb: 0.00
> Codegen work/sdclk/str_sdclk: 0.00
> Codegen work/sdclk_tb/bhv_sdclk_tb: 0.00
> Release 9.1.03i -ISESimulatorFuse J.33
> Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
> Building ../out/work/sdclk_tb/lin/xsimbhv_sdclk_tb
> Release 9.1.03i -ISESimulatorEngine J.33
> Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
> This is a Lite version ofISESimulator.Simulatoris doing circuit initialization process.
> Finished circuit initialization process.
>
> ** Failure:Simulation successful (not a failure). No problems detected.
> User(VHDL) Code Called Simulation Stop
>
> Simulation stopped when executing process: sdclk.test.vhd:stimuli
> on line 105 in file "bench/vhdl/sdclk.test.vhd"
> -----------------------------------------------
>
> The simulation script will use ${module}_tb as the top-level entity name. If
> your top-level entity has a different name, use the -entity option.
>
> I hope this helps. I've been using theISEsimulatorwith success for some
> time now with command-line simulation. You should installISE9.1i (with
> the latest service pack) or newer, asISE8.2i has lots of simulation bugs
> that have been fixed in 9.1i (including crashes).
>
> Best regards,
>
> Laurent Pinchart
Hi Laurent,
Thanks for helping out here. Just one comment in case you did not
know. The -instyle ise switch is not needed if you are not inside
ISE :). We just use this for out internal use for formatting the
messages better to show in the ise console in case you were wondering.
Thanks
Duth
Article: 120929Marek We have a couple of things in the pipeline that may be useful to your application depending exactly on what you want to do. If you want to either post your requirements I'll respond. If you don't want the details in public send an email marked for my attn. to one of our public emails listed on our website and the team will pass it over to me to respond. John Adair Enterpoint Ltd. www.enterpoint.co.uk On 20 Jun, 10:07, Marek Kraft <sepher_gr...@o2.pl> wrote: > Hello! > > I have been playing with image processing on FPGA for some time now, > and the results seem interesting (I am working mainly on image > preprocessing and edge/corner detection algorithms). My main research > platform was the S3BOARD from Digilent/Xilinx, but I got to the point, > where RS232, or RS232 <-> USB converters do not offer sufficient speed > (imagine sending a 512x512 image to the board and then waiting for the > results, even in grayscale). Therefore, I'd like to invest some money > in a more advanced evaluation board. For now, the Virtex-4-based Video > Starter Kit seems to be the most reasonable choice for me. Is anyone > here using this kit? The opinions I have found while googling the net > (like the one here:http://www.embeddedrelated.com/usenet/embedded/show/54852-1.php) > are however somewhat disencouraging. I'd like to know if it's hard to > develop my own applications for the daughtercard without having to use > the Matlab/Simulink software (just plain HDL). I also tried to find > some other boards for this task (a solution that is functioning out-of- > the-box would be ideal). The price of boards by Vmetro and > Hitechglobal is an overkill for me. I considered also buying the > XUPV2P board from Digilent design a CameraLink compatible interface > for it, but I fear that V2Pro devices are a bit outdated and Xilinx > will stop supporting this product line. I'd also like to know if it is > better to use dedicated National Semiconductor chips to do the > deserialization, or try to use the IOB/multiple clocks based approach? > Thanks for any suggestions.Article: 120930
Uwe Have you thought of using an analogue pll multiplier chip like a ICS8442. We use this chip in some unusual situations because it can run it's VCO to a very high frequency and for that matter can supply it to FPGA as a LVDS clock. Once you have the clock can you then use phases of the clock to recover your data maybe even then using a DCM to phase shift if needed. John Adair Enterpoint Ltd. On 20 Jun, 09:53, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> wrote: > Hello, > > for some legacy instrument, I need to replace AM796X Taxichips doing a > 9B<->11B encoding/decoding. The Taxichip is long EOL, and replacement chips I > know only do 8B<->10B or 10B<-> 12B > Data encoding can easily be done with BRAMs as ROM, and also the aligned > receive data stream. For receiving, I plan to use the XAPP224 > datarecovery. However having the data recovery run at the same nominal > frequency like the transmitter, two bits can be received in one receiver > clock cycle. This will make data alignment harder. Running the receiver > clock a little bit higher, say 125 vs 125.1 MHz, the two bit receive > situation can be avoided. The Xilinx DFS can "only" multiply by 2..32 and > divide by 1..32. With a clock frequency of 20 MHz, I could run at > transmitter at 125 MHZ and and the receiver at 130 MHz, imho too far apart. > > Any idea how to generate frequencies slightly apart? > > Thanks > > -- > Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 120931
Hi Laurent..
Thanx a lot for providing the bash script..But i have
worked out of this problem i wasnt able to reply sooner because i was
trying to overcome this problem which made me land up in another..I
arranged for RHEL 4.0 and i installed Webpack 91i on it the compiler
and simulator are working out fine but it is the IMPACT which is
giving me the problem what happens is when i double click on IMPACT
after checking everything and showing it is successfully checked till
"Fit" it just hangs up and during installation the drivers script do
not get installed that is the drivers cable do not get installed
saying "kernel mismatch"..So is there a way out of this i have tried
installing windrvr6.0 but some how it doesnt seem to work out if
somebody could provide a better solution to this it would be really
great...
Regards
Ankit
Article: 120932The type of thing you are doing we have a number of clients doing similar things with our development hardware in quite a few application areas. >From DSP performance it is hard for a DSP processor to beat a well designed and implemented FPGA design. Generally you should see a massive increase in performance in FPGA DSP engine compared to the software running on a generic X86 processor. The second part of your problem is getting data to and from the DSP Processor or FPGA. We see a lot of these applications because a lot of our boards are PCI or PCI-E based and offer a high bandwidth route to the PC but you may want to consider USB2 as an alternative. It is not as performant as PCI usually. Often the USB controller itself effectively sits on a PCI bus so is limited by that if not it's own protocol handing. If you do have a high data bandwidth requirement do be careful of what PCI and PCI-E can deliver in reality. 20-50% of the bus/link speed is a reason first level guide of what can be achieved and even then there are lots of factors. John Adair Enterpoint Ltd. www.enterpoint.co.uk On 20 Jun, 06:41, "h...@hit.edu.cn" <h...@hit.edu.cn> wrote: > There is a software application which demonds huge computation. My aim > is to port the software program into hardware. So first of all, I need > to evaluate the required volumn of computation. > > The situation is that the software program will need up to 22 hours on > personal computer (P4 3.06G, 2GB RAM) to finish the computation, while > the operations mostly are float-point multiplications and additions. I > need to finish the computation by hardware in serveral minites. Is it > possible? > > Another problem is that which kind of hardware platforms is > perferable. I have checked that the production provided by > Nallatech(www.nallatech.com) seems suitable for me. I am still > wondering whether I should choose some boards with multiple DSP > processors on it? I think DSP processors are better at floating point > operations.Article: 120933
On 20 juin, 08:12, subint <subin...@gmail.com> wrote: > The controller generated by MIG tool is not efficient. There was lot > of bugs in the code i generated using 1.6 version. They are not sure > it's works in the higher frequency. That's why it's shown 165 as the > limit. But you can make changes in the code and can try to work for > higher frequency. > Regards > Subin We are thinking about using the Direct-clocking part of the MIG for DDR2 (which runs at 220 MHz) as a reference and integrate this in the MIG for DDR memory. I'm assuming that the differences between DDR and DDR2 are small enough that this could work, but maybe I'm mistaken. Hopefully with that trick we could go higher than 165 MHz (we really need 200 MHz). Does that seems like a good idea or not? PatrickArticle: 120934
Hello everybody, I am trying to make a software video processing with the VSK. For this, I want read video data from the DDR, applied the convolution algorithm and write the modified video data in the ddr. but I have some probleme to read/write in the ddr. Can anyone tell me how we can read and write data in the ddr? Thanks.Article: 120935
I'm a MIG newbie and am trying to implement the following: Memory: DDR2, 64 MB x 16 x 2 chips (64 MB x 32 result) FPGA: XC4VLX25-10FF668 The DDR2 I/O requirements can be satisfied using one 'big' bank (banks 5-10) and one 'small' bank (banks 1-4). My plan was to allocate data, control and address to bank 5 and address to bank 3. In the MIG GUI, when I select a big bank (5), all DDR2 signal groups are supported (address, data, control). However, when I select a small bank (3), only the control lines are supported. In this case, the address and data lines won't all fit in the large bank, so I get an error indicating that not enough pins are available for the address lines. When looking at bank 3, there doesn't appear to be any reason why it shouldn't be availble. Unlike banks 1,2, DCI is available on banks 3,4 for the the LX25-FF668. I haven't yet looked at the generated HDL code to see if there are come clock distribution issues with bank 3 that make it unavailable, but I wouldn't suspect this is the issue. Any ideas??? TIA UrbArticle: 120936
I am interested in finding the manufacturer of U3 on this SSD device: http://www.engadget.com/2007/02/19/the-do-it-yourself-ssd-adapter/ The device in question is on the underside of the PCB above the letters "25SD". It has a strange Logo that I do not recognize. See : http://akiba.ascii24.com/akiba/news/2006/11/16/imageview/images825461.jpg.html Regards, Richard.Article: 120937
I have made a lot of test. In this test I have first tried to write one data on all the ddr, for this I write in fifo[512]ddr0_wa numbers from 0 to 511, after I write for example "767858038" in all the fifo[512]ddr0_wd, but I have nothing.Article: 120938
If you think you meet our high standards, and you would like to work in a challenging but friendly environment in San Jose, CA or Longmont, CO, then just e-mail me your resume. Might be the best move you ever made. It was for me, 19 years ago. peter@xilinx.comArticle: 120939
On Jun 20, 2:07 am, Marek Kraft <sepher_gr...@o2.pl> wrote: > I considered also buying the > XUPV2P board from Digilent design a CameraLink compatible interface > for it, but I fear that V2Pro devices are a bit outdated and Xilinx > will stop supporting this product line. I'd also like to know if it is > better to use dedicated National Semiconductor chips to do the > deserialization, or try to use the IOB/multiple clocks based approach? Buy the National chips and be done with it. You'll be glad you did. -aArticle: 120940
Marek, Virtex II Pro is a successful, in production, product line. We rarely remove support for anything. We still offer the XC3000 family of components (not many, but still manufacture, sell, and support the ones that are still used!). Discontinuance is determined by lack of use. For example, the 4KXV series was intended to be a 'fall back' if Virtex was unsuccessful. I would not worry about discontinuance of the VII Pro. If you are designing a new board, for a commercial product, then I would encourage you to consider Virtex 5. The latest technology provides much more value for the cost than the older technologies. AustinArticle: 120941
Couldn't start to identify the part with that image. Maybe it looks good on your monitor but I don't care to adjust my monitor settings and get the loop out to try and SEE the logo on that chip in the first place. Might I suggest a better macro lens? "RR" <richardrooney@icecomms.net> wrote in message news:1182357838.983936.116440@u2g2000hsc.googlegroups.com... >I am interested in finding the manufacturer of U3 on this SSD device: > http://www.engadget.com/2007/02/19/the-do-it-yourself-ssd-adapter/ > > The device in question is on the underside of the PCB above the > letters "25SD". > It has a strange Logo that I do not recognize. > > See : > http://akiba.ascii24.com/akiba/news/2006/11/16/imageview/images825461.jpg.html > > Regards, > Richard. >Article: 120942
hitsx@hit.edu.cn wrote: > There is a software application which demonds huge computation. My aim > is to port the software program into hardware. So first of all, I need > to evaluate the required volumn of computation. > The situation is that the software program will need up to 22 hours on > personal computer (P4 3.06G, 2GB RAM) to finish the computation, while > the operations mostly are float-point multiplications and additions. I > need to finish the computation by hardware in serveral minites. Is it > possible? If you give some hints as to what type of computation you are doing you will get better answers. Floating point, especially addition, is relatively expensive in an FPGA. You might consider the possibility of using fixed point, even if it is significantly wider. Sometimes block floating point works well, where one exponent applies to many (like a whole vector of) values. (The pre/post normalization needed for floating point is expensive.) The actual implementation of the algorithm is usually very different in an FPGA. I recommend the systolic array architecture, but there are other possibilities. > Another problem is that which kind of hardware platforms is > perferable. I have checked that the production provided by > Nallatech(www.nallatech.com) seems suitable for me. I am still > wondering whether I should choose some boards with multiple DSP > processors on it? I think DSP processors are better at floating point > operations. There are some systems convenient for implementing such designs. I have seen PCMCIA cards with an FPGA, though that might not be big enough for you. How many times do you need to run this problem, and how big is your budget? You might also look at: http://www.drccomputer.com/ -- glenArticle: 120943
"Vasanth Asokan" <vasanth@xilinx.com> wrote in message news:f59jkj$lgv1@cnn.xilinx.com... > The warning comes about because you are trying to initialize this > partitioned application into _BRAM_. When the bitstream is downloaded, > your app won't work since only a part of it is present in the bitstream. > But if you are downloading everything via XMD, then you are fine. So > depending on what you are trying to do, the warning could be something > real you have to watch out for. > > You can use the linker script generator for partitioning ELf setions > between different memories. It works and no, there is no confusion between > the code segments as someone else pointed out. > > Vasanths > I altered the loader script so that only .data, heap and stack were placed in external memory. However I still got the error. Things have moved onto another board where thankfully there is sufficient block ram. Many thanks for the replies.Article: 120944
John_H wrote: > Couldn't start to identify the part with that image. Maybe it looks > good on your monitor but I don't care to adjust my monitor settings > and get the loop out to try and SEE the logo on that chip in the > first place. Might I suggest a better macro lens? > > Richard wrote > >> I am interested in finding the manufacturer of U3 on this SSD device: >> http://www.engadget.com/2007/02/19/the-do-it-yourself-ssd-adapter/ > >> The device in question is on the underside of the PCB above the >> letters "25SD". It has a strange Logo that I do not recognize. >> http://akiba.ascii24.com/akiba/news/2006/11/16/imageview/images825461... I had trouble making it out as well. Looks fuzzily-familiar to a Cypress logo. If you tell us the part number we can pin it down.Article: 120945
On Jun 20, 3:11 pm, "John_H" <newsgr...@johnhandwork.com> wrote: > Couldn't start to identify the part with that image. Maybe it looks good on I don't think the OP actually owns one, that looks like a stock/ catalog photo. And the second photo appears to be a woman's hand, which while not incompossible with the name "Richard" is at least unusual.Article: 120946
Hi, rponsard@gmail.com wrote: > do you plan to release a reference design for spartan 3A700 xilinx > starter kit ? I'm in discussion with Xilinx to get hold of some of the S3A boards, with a view to their support in PetaLinux. I'm not familiar withthe specifics of this board, but if it has a couple of meg of DRAM and some parallel flash, we can get Linux going on it. Regards, JohnArticle: 120947
RR wrote: > I am interested in finding the manufacturer of U3 on this SSD device: > http://www.engadget.com/2007/02/19/the-do-it-yourself-ssd-adapter/ Q. Why do you want to know? Looking at the PCB vs the functionality, I'm having trouble understanding why you'd need half the crap on there just to interface 4 SD cards to IDE... and looking at the asking price it would appear that the marketing division have as little clue as the engineering division... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 120948
I see Achronix and Mentor Graphics have inked a co-operation deal. Anyone know when their Async FPGA Silicon will actually ship ? -jgArticle: 120949
In article <4679d975$0$22418$5a62ac22@per-qv1-newsreader- 01.iinet.net.au>, markm@vl.com.au says... > RR wrote: > > > I am interested in finding the manufacturer of U3 on this SSD device: > > http://www.engadget.com/2007/02/19/the-do-it-yourself-ssd-adapter/ > > Q. Why do you want to know? > > Looking at the PCB vs the functionality, I'm having trouble understanding > why you'd need half the crap on there just to interface 4 SD cards to > IDE... and looking at the asking price it would appear that the marketing > division have as little clue as the engineering division... According to the manufacturer (Century Corp, Japan), it stripes the data across the multiple cards to speed up access (you must install cards in pairs). --Gene
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