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Messages from 12100

Article: 12100
Subject: WORKSHOPS '98 - VHDL for Power Users
From: "Peter J. Ashenden" <petera@cs.adelaide.edu.au>
Date: Tue, 29 Sep 1998 12:47:44 +0930
Links: << >>  << T >>  << A >>
WORKSHOPS '98 - VHDL for Power Users
                             October 26 - 28, 1998 

                      Adam's Mark Hotel, Orlando Florida

For further info and registration:
http://www.vhdl.org/viuf/conf/conf.html

Advance registrations due October 9.

INVITATION

"It is time for a change." That is the message that has come through
loud and clear from you, the user community. VHDL has come of age and
now has a mature following. Isn't it about time to give some dedicated
focus to the issues facing experienced VHDL users?

With this in mind, I cordially invite you to take advantage of a
unique opportunity - to participate in workshops and tutorials geared
to moderate and advanced VHDL users and developers. VIUF is replacing
the usual Fall Conference with a program that we hope will accomplish
two goals:

1.Provide a more extensive forum for open dialog; and 

2.Provide information on current industry trends in VHDL thinking and
  usage.

Workshops '98 will attempt to promote an active rather than passive
environment. Workshop topics were selected based upon input solicited
from the user community; and workshop attendance will be limited to
facilitate better dialog. We intend to capture the key points and
arguments from each workshop. This information will then be passed on
to relevant working groups and standards bodies within the
IEEE/DASC. Your voice will be heard by those who are actively evolving
VHDL and its companion standards.

Preceding the workshops, there will be a day dedicated to tutorials
for both novice and experienced VHDL users. For variety, the Program
Committee has also embedded a few tutorials within the workshop
schedule as well as a special session to showcase papers from the
academic community.

It is a great pleasure to announce the return of the VIUF International
Workshop on Behavioral Modeling and Simulation (BMAS). This valuable
forum will address the emerging needs associated with analog and
mixed-signal extensions to VHDL and will be co-located with Workshops
'98.

In closing, I again extend to you my personal invitation to
participate in what I believe will be an intriguing, informative
and significant dialog. Are you up to the challenge? I hope to
see you there.

Yvonne T. Ryan - Event Chair
Article: 12101
Subject: Re: Announcement: 200.000 Gates FPGA Prototyping Board
From: Rickman <spamgoeshere4@yahoo.com>
Date: Tue, 29 Sep 1998 00:59:25 -0400
Links: << >>  << T >>  << A >>
Sri Saripalle wrote:
> 
> Hello Lothar,
> 
> We offer the following services and have expertise in-house
> (a)ASIC/FPGA design, verification & implementation services.
> (b) EDA Software solutions
> (c) Cell & Library Development
> 
> We have 90 employees world-wide and 50 engineers in our US Design center
> and the rest in our engineering center in India.
> Please let me know if there are any opportunities we could address and
> bring in our expertise in this area.
> 
> Thanks
> 
> - Sri

Almost everyone reading this message is a designer who is doing the same
type of work. Why are you telling us? 

-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.
Article: 12102
Subject: Re: I2C controller references needed!
From: Andrew Cannon <a.cannon@fairlightesp.com.au>
Date: Tue, 29 Sep 1998 10:24:50 +0200
Links: << >>  << T >>  << A >>


Tim O wrote:

> >I am working on an I2C controller to be placed in an FPGA and I will
> >appreciate any valuable information.
> >
>
> If you're using Altera devices there's an I2C module on the freecore
> webpage that might do what you need.  I'll look up the url if you're
> interested.  (I haven't used this lpm myself, I've only seen it -- it
> is well documented though).
>
>                 Tim.


Could you post that url please!


...Andrew

Article: 12103
Subject: Re: Metastability
From: Andrew Cannon <a.cannon@fairlightesp.com.au>
Date: Tue, 29 Sep 1998 10:48:28 +0200
Links: << >>  << T >>  << A >>


saju@wipinfo.soft.net wrote:

> Any good reference material on "Metastability".
>
> Thanx,
>
> Saju
>
>   --------------------------------------------------------------------
>   Posted using Reference.COM                  http://WWW.Reference.COM
>   FREE Usenet and Mailing list archive, directory and clipping service
>   --------------------------------------------------------------------


A couple on the Xilinx site which also have some general discussion and
further references:

 http://www.xilinx.com/apps/xapp.htm#xapp077
 http://www.xilinx.com/apps/xapp.htm#xapp094

...Andrew


Article: 12104
Subject: Re: I2C controller references needed!
From: dstewart@REMOVE.THIS.dmicros.com (Derek Stewart)
Date: Tue, 29 Sep 1998 09:57:26 GMT
Links: << >>  << T >>  << A >>
The Freecore URL is :
http://193.215.128.3/FREECORE/

Derek

>Hello everyone!
>
>I am working on an I2C controller to be placed in an FPGA and I will
>appreciate any valuable information.
>
>Tank you!
>Ovi
>-- 
>
>************************************************************
>Ovidiu Lupas
>TimTeh Electronics Ltd.
>
>e-mail      : ovilup@hotmail.com                     
>home e-mail : ovilup@mail.dnttm.ro      phone : 40-56-121951
>work e-mail : lupas@timteh.dnttm.ro phone/fax : 40-56-198943
>************************************************************

Article: 12105
Subject: Using Xilinx TBUF?
From: Thomas Reinemann <thomas.reinemann@mb.uni-magdeburg.de>
Date: Tue, 29 Sep 1998 12:21:43 +0100
Links: << >>  << T >>  << A >>
I'm using Xilinx M1 (Syntesys FPGA Express).

I've a shift register and every output must drive some inputs. I want to

avoid a slow slew rate. Is there an explicit possibility to use Xilinx
TBUF?

Bye Tom!



Article: 12106
Subject: Where can I get comp.arch.fpga newsarticle archive?
From: vic@alpha.podol.khmelnitskiy.ua (Victor Levandovsky)
Date: Tue, 29 Sep 1998 12:31:39 GMT
Links: << >>  << T >>  << A >>

Article: 12107
Subject: Re: strange problem of 4028XL
From: Mohsin Riaz <mohsin@engr.mun.ca>
Date: Tue, 29 Sep 1998 11:45:30 -0230
Links: << >>  << T >>  << A >>
Hi friend,

I am faced with the same problem too, since i am also targeting the same 
XC4028expg299-3 device. 

I am also faced with the problem of getting the post_synthesis simulation 
to work using the time_sim.sdf amd time_sim.vhd files that are generated, 
while i am using the FLOW ENGINE in the design manager of the XILINX. I 
troed using the same test bench file which i had earlier used for 
functional simulation, but i can't get any trace/signal on the VHDL 
simulator using the VHDLDBX &. I just get a single all zero trace 
labelled TOC. Am i missing something?

I would really appreciate, if u could outline the steps that are involved 
in successfully getting through the post synthesis timing simulation.

Thanks,

Mohsin Riaz

Faculty Of Engineering,
Memorial University Of Newfoundland,
St. John's,Newfoundland,
A1B3X5,Canada.
email:mohsin@engr.mun.ca
Web:www.engr.mun.ca/~mohsin



On Mon, 28 Sep 1998, Gareth Baron wrote:

> Are you sure you are providing all the power and gnd pins correctly ?
> 
> Are you exceeding the total current specifications ?  Ie the current drawn
> by the VCC pins is less than the datasheet specifications ?  What about the
> Dynamic current consumption when you are switching a load of outputs ?
> 
> Just some thoughts for you.
> 
> 
> Leprechaun wrote in message <6ue1f8$cpd@ustsu10.ust.hk>...
> >Hi all,
> >
> >I am using Xilinx XC4028XL-1-PG299 to implement a circuit. The utilization
> >is 100 % (all 1024 CLBs are used). After I download the circuit, I use a
> >IMS Tester to test the chip.
> >I found that for some output pin assignment, my circuit works well, but
> >for another, it just gives wrong result or just no result (all outputs
> >stay zero).
> >
> >I've done post-sim using the .sdf and .vhd files generated by M1 in
> synopsys
> >and the it works well (not any glitch problems ) and the timing
> >requirement for my circuit is not tight at all.
> >
> >does anyone have the same experience? I've already spent 2 weeks time in
> >debugging this problem but don't have any idea up till now.....
> >
> >Thanks a lot.
> >
> >Rgds,
> >
> >Oliver
> >
> 
> 
> 
> 


Mohsin Riaz
Box#59,
Faculty Of Engineering,
Memorial University Of Newfoundland,
St. John's,Newfoundland,
A1B3X5,Canada.
email:mohsin@engr.mun.ca
Web:www.engr.mun.ca/~mohsin
Tel# res:(709)576-8414
     off:(709)737-8809 
     lab:(709)737-3583

Article: 12108
Subject: Simple programmable device suggestions please?
From: "Lukas Louw" <louw1@worldnet.att.net>
Date: 29 Sep 1998 14:53:31 GMT
Links: << >>  << T >>  << A >>
Hi all,

I have an application where we use a handful of standard CMOS IC's, a 4028
BCD to decimal, and 3 x 4071 quad OR gates, to generate 10 outputs from a 4
input BCD switch. Speed is not important, as it controls input selection of
a consumer audio product.

Any ideas on a simple cost effective programmable device that could replace
these parts? Something that can implement a simple 12 gate or so equivalent
lookup table? It seems that most of the devices out there today are much
more complex, therefore too pricey, for what we need.

I would like to use a programmable device of some kind, as the marketing
people drive me nuts with their requests for feature changes/additions.
Every time this happens, the gate routing has to be changed, which means
modifying the PCB layout........

Thanks,
Lukas Louw


Article: 12109
Subject: I2C : thank you
From: "ovilup" <ovilup@hotmail.com>
Date: 29 Sep 1998 15:43:48 GMT
Links: << >>  << T >>  << A >>
Hello,

Thank you very much for your help and url. 

I had looked up and it is a good starting point. My controller should be a
little more complex,
but I think I can handle it. At least this I should do, er ? :)

Ovi.
 


Article: 12110
Subject: Re: Simple programmable device suggestions please?
From: "Stephen Peddle" <smp@spam.com>
Date: Tue, 29 Sep 1998 15:47:43 GMT
Links: << >>  << T >>  << A >>
Because you have 10 outputs your circuit won't fit in a 16V8 (only 8 outs).
The next part I would consider would be a 22V10 (10 outs).

Both these parts come in multiple flavours from multiple vendors.  You can
even get some ISP parts if you want.

Lukas Louw wrote in message <6uqs9b$2io@bgtnsc03.worldnet.att.net>...
>Hi all,
>
>I have an application where we use a handful of standard CMOS IC's, a 4028
>BCD to decimal, and 3 x 4071 quad OR gates, to generate 10 outputs from a 4
>input BCD switch. Speed is not important, as it controls input selection of
>a consumer audio product.
>
>Any ideas on a simple cost effective programmable device that could replace
>these parts? Something that can implement a simple 12 gate or so equivalent
>lookup table? It seems that most of the devices out there today are much
>more complex, therefore too pricey, for what we need.
>
>I would like to use a programmable device of some kind, as the marketing
>people drive me nuts with their requests for feature changes/additions.
>Every time this happens, the gate routing has to be changed, which means
>modifying the PCB layout........
>
>Thanks,
>Lukas Louw
>
>


Article: 12111
Subject: Re: Simple programmable device suggestions please?
From: Jonathan Bromley <jsebromley@brookes.ac.uk>
Date: Tue, 29 Sep 1998 16:54:38 +0100
Links: << >>  << T >>  << A >>
Lukas Louw wrote:
> I have an application where we use a handful of standard CMOS IC's, a 4028
> BCD to decimal, and 3 x 4071 quad OR gates, to generate 10 outputs from a 4
> input BCD switch. Speed is not important, as it controls input selection of
> a consumer audio product.
> Any ideas on a simple cost effective programmable device that could replace
> these parts? Something that can implement a simple 12 gate or so equivalent
> lookup table? It seems that most of the devices out there today are much
> more complex, therefore too pricey, for what we need.
> I would like to use a programmable device of some kind, as the marketing
> people drive me nuts with their requests for feature changes/additions.
> Every time this happens, the gate routing has to be changed, which means
> modifying the PCB layout........

Go for it!
To  get 10 outputs the cheapest you can do is pretty certainly one of
the
22V10 family - 10 outputs, more inputs than you need.  Far more speed
than
you require, but of course that's no problem.  If you're making
consumer kit then your volumes are probably high enough to get a good
deal
on the part.  True product-life cost of the 22V10s should be a stack
cheaper than all the PCB real-estate, PCB design respins, assembly
hassle
and inflexibility that you have right now.  Plenty of free software
around
(PALASM from AMD,  demo versions of CUPL from Logical Devices, etc, etc)
for something as simple as this.  And what's more you get enough logic
to implement extra stuff like latches if you need them.

In-system-programmable parts (Lattice) probably too expensive to suit
your
application, so you will need a programmer - but don't buy anything
expensive
because in a high volume application you should get your distributor to 
program the parts for you - tell 'em how many thousands of pieces you
need,
and they'll crawl all over you offering programming services.

You won't look back.

Jonathan Bromley
--
Article: 12112
Subject: Re: strange problem of 4028XL
From: fliptron@netcom.com (Philip Freidin)
Date: Tue, 29 Sep 1998 17:44:54 GMT
Links: << >>  << T >>  << A >>
Sounds like it might be poor power supply characteristics.

	Are all the power and grounds connected
	Are the outputs in slow slew mode (default)
	Are you following the data book rules about number of switching
		outputs per power/ground pair
	How far away are the decoupling capacitors?
	Is the chip in a wirewrap socket? if so how long are the power
		and ground wires, where are the decoupling capacitors.

Philip.


In article <6ue1f8$cpd@ustsu10.ust.hk> cpegfa@uxmail.ust.hk (Leprechaun) writes:
>Hi all,
>
>I am using Xilinx XC4028XL-1-PG299 to implement a circuit. The utilization
>is 100 % (all 1024 CLBs are used). After I download the circuit, I use a 
>IMS Tester to test the chip. 
>I found that for some output pin assignment, my circuit works well, but
>for another, it just gives wrong result or just no result (all outputs 
>stay zero).
>
>I've done post-sim using the .sdf and .vhd files generated by M1 in synopsys
>and the it works well (not any glitch problems ) and the timing 
>requirement for my circuit is not tight at all.
>
>does anyone have the same experience? I've already spent 2 weeks time in
>debugging this problem but don't have any idea up till now.....
>
>Thanks a lot.
>
>Rgds,
>
>Oliver
>


Article: 12113
Subject: Re: Using Xilinx TBUF?
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: 29 Sep 1998 18:49:04 GMT
Links: << >>  << T >>  << A >>
Thomas Reinemann <thomas.reinemann@mb.uni-magdeburg.de> wrote in
article <3610C2C7.B19A3B8A@mb.uni-magdeburg.de>...
> I'm using Xilinx M1 (Syntesys FPGA Express).
> 
> I've a shift register and every output must drive some inputs. I
want to
> 
> avoid a slow slew rate. Is there an explicit possibility to use
Xilinx
> TBUF?
> 

You're being vague.

Do you mean that every output of the shift register must drive some
inputs to other *chips* or just inputs to other modules inside your
chip?

-- 
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
apeters@noao.edu.NOSPAM

Article: 12114
Subject: USA EDA rel. jobs+work visa
From: garynlang@aol.com (Garynlang)
Date: 29 Sep 1998 20:33:01 GMT
Links: << >>  << T >>  << A >>


We are looking for: 
designers, programmers, engineers:
We provide working visa if needed.
3 years exp. required
Permanent positions only
Pls. send your TEXT only resume as an EMAIL
if you are interested

1. Standard ASIC designers:
Arizona, US. 

2. EDA Tool Software Development
Arizona, US.
Candidates should possess strong software development skills (C++,
configuration management tools), experience developing EDA tools is
preferred. Knowledge in Verilog, VHDL and synthesis are also preferred. 
The main products of this group are model generators for EDA tools and VLSI
EDA tools such as Delay Calculators, netlist screeners.


3. Design System Development
 I currently have two openings in this
group. These people should be familiar with using EDA tools (simulation,
static timing, synthesis, design-for-test, etc.), and preferably have a good
understanding of the modeling issues in those tools and how to integrate EDA
tools into the design environment.
The group combines commercial EDA tools, VLSI tools and libraries for VLSI
technology into a design system based on design flows and interoperability
of the tools in that environment.

4. Bay Area:  ANALOG cicuit design. We can send a simple
analog circuit for you to take a look, analyze it and apply
for the position. 


Gary Lang
Gary N. Lang
Vice President of ACD,Inc.
E-mail: garynlang@aol.com
http://www.acdcon.com/
Article: 12115
Subject: Maxplus2 Timing Analyzer
From: s9510300@cse.rmit.EDU.AU (Giang Thach Nguyen)
Date: 29 Sep 1998 22:43:20 GMT
Links: << >>  << T >>  << A >>
Does anyone know how to report delay of internal signals with Altera's Maxplus2 Timing Analyzer? I can only get the delay from one I/O pin to another I/O pin.  Any input would be appreciated. 
Article: 12116
Subject: Re: Maxplus2 Timing Analyzer
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Tue, 29 Sep 1998 23:04:16 -0400
Links: << >>  << T >>  << A >>
By internal signals, I assume you are talking about register to register delays.  If you are only getting i/o to i/o delays, then you have the analysis menu set to delay matrix, which if I
remember right is the default.  To get a listing of register to register delays:

Select the timing analyzer
On the analysis menu, select registered performance
On the options menu, select time restrictions
In the time restrictions dialog box, set either the number of paths per clock or the clocks less than frequency radio buttons and text boxes with appropriate values
Run the analysis
Push the list paths button

You'll get a listing paths sorted by longest path first

Also, if you assign any timing constraints, they are included in the *.rpt file with the assigned and realized time values for each of the setup/hold, delay matrix, and registered performance
groups.



Giang Thach Nguyen wrote:

> Does anyone know how to report delay of internal signals with Altera's Maxplus2 Timing Analyzer? I can only get the delay from one I/O pin to another I/O pin.  Any input would be appreciated.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 12117
Subject: Re: Where can I get comp.arch.fpga newsarticle archive?
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Tue, 29 Sep 1998 21:04:02 -0700
Links: << >>  << T >>  << A >>
You can find a list of newgroup pointers at
http://www.optimagic.com/newsgroups.html.

Also, you can try searching for the appropriate article at www.dejanews.com.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

Victor Levandovsky wrote in message
<1103_907072299@p-331.podol.khmelnitskiy.ua>...


Article: 12118
Subject: Re: Efficient max-function architecture? -- "parallel bitwise max"
From: Brad Taylor <blt@emf.net>
Date: Wed, 30 Sep 1998 00:10:18 -0700
Links: << >>  << T >>  << A >>
This Bit-Serial approach is very clever Jan, but if we were to pass the
16 data values sequentially into the FPGA as 2 8-Bit parallel values per
clock over a 16-Bit bus instead of 16 Serial lines (along with a sync
line), I think we can compute the max in 10 CLBs. (assuming packing the
subtractor, mux and registers in the same CLBs)

                       /=====REG==\
                       |   [MAX]  |
               [MAX]   \==>|a o|==/
 [hi_byte ]===>|a o|==REG=>|b__|
 [lo_byte ]===>|b__|
 
Result every 8 clocks,  (you have to force the max value to be loaded on
clock 0 by mucking with the carry). The problem is the speed. Current
FPGAs do an 8-Bit ripple subtract in 6 to 8 ns, but you have to
distribute the carry back to the mux in the same clock which will take
another 3-4 ns. You can pipeline the delay away, but that will cost
another 4 CLBs. (You can actually hide 2 of these registers in the carry
CLBs, but you will also need to delay sync with two registers).

 slow=12ns, 10 CLBs
 fast= 8ns, 14 CLBs
 
 Cheers,
 Brad
 




Jan Gray wrote:
> 
> I wrote in message <6u8s8g$l5s$1@news-1.news.gte.net>...
> >Algorithm analysis 101 tells us that to determine the largest item of n
> >items requires at least n-1 2-input "greater than" comparisons. ...
> 
> SEGUE
> 
> Algorithm analysis 101 also teaches us to carefully choose a model (e.g.
> elements and a 2-element comparison function) and a goal (e.g. minimize no.
> of comparisons to determine the largest element) to represent the problem.
> Only then can we compare algorithms or study optimal lower bounds on
> algorithms.
> 
> For example, using a comparison based model, it can be shown that any
> sorting algorithm on n elements must perform at least ceil lg n!
> comparisons.  But there are other sorting algorithms which do not perform
> any elementwise comparisons.  They assume a different model with different
> operations on the elements.  Consider radix sort, in which we distribute the
> n elements into r buckets, according to increasingly significant digits in
> their base r representation, and then regather them and repeat.  (Remember
> the old IBM punch card sorters?)
> 
> So, as radix sort is to a comparison-based sort, is there an analogous
> "radix max" to our comparison-based max?
> 
> "PARALLEL BITWISE MAX"
> 
> Yes.  Here's a 'digit'al method for finding the max of n k-bit words.
> 
> We scan the n inputs as n serial bit streams, all clocked together, msbs
> first.  One bit stream is the maximum if it is never observed to be less
> than some other bit stream.  For any two bit streams A and B,
>   "A < B" iff ~msb(A)&msb(B) | (msb(A)==msb(B) & "lsbs(A) < lsbs(B)").
> 
> Design: we keep n candidate-for-max state bits, one for each bit stream.
> All are initialized to 1, as each stream is initially a candidate to be the
> maximum.  A candidate stream is still a candidate if it has a current 1
> input bit.  A stream with a current 0 input bit loses its candidacy if there
> is some other remaining candidate stream that has a current 1 bit.  After
> all input bits have been clocked past, the remaining candidate is the
> maximum bit stream.  If duplicate input bit streams are possible, there can
> be more than one remaining candidate, each of which corresponds to the same
> maximum value.
> 
>   // pidgin netlist generator source:
> 
>   input reset; // 1 during the reset cycle
>   input stream[n]; // current bit of each of the n input streams
>   reg cand[n]; // 1 if the i'th stream is still a candidate for maximum.
>   net some1; // 1 if some remaining candidate stream input bit is currently
> 1
>   output answer; // result, the index of max input stream
> 
>   some1 = cand[0]&stream[0] | cand[1]&stream[1] | ... |
> cand[n-1]&stream[n-1];
>   for (i = 0; i < n; i++)
>     cand[i] := reset | cand[i]&(stream[i] | ~stream[i]&~some1);
> 
> If we know the input words are never two alike, then bitcount(cand)=1 and we
> can use
>   answer = encode(cand);
> otherwise,
>   answer = priority_encode(cand);
> 
> Implemented in an XC4000 FPGA, for n=16, requires approximately
>   4.5 CLBs for some1
>   8 CLBs for cand[16]
>   12.5 CLBs for a 16-to-4 priority encoder
> ----
> ~25 CLBs, result every 9 clocks for 8-bit input data, at perhaps 10
> ns/clock.
> 
> Radix 4 (2 bits/clock) is also possible but probably unwieldly and slow.
> 
> The nice thing about this approach is it is readily scalable to many inputs;
> the slowest part of the design would be the 'some1' or-reduction circuit,
> and even with 36 input streams this is only three CLB delays and mostly
> local interconnect.
> 
> Jan Gray
Article: 12119
Subject: Re: Efficient max-function architecture? -- "parallel bitwise max"
From: "Jan Gray" <jsgray@acm.org.nospam>
Date: Wed, 30 Sep 1998 01:25:51 -0700
Links: << >>  << T >>  << A >>
Brad Taylor wrote in message <3611D95A.527FC010@emf.net>...
>                       /=====REG==\
>                       |   [MAX]  |
>               [MAX]   \==>|a o|==/
> [hi_byte ]===>|a o|==REG=>|b__|
> [lo_byte ]===>|b__|

I like it!  Certainly nicer than the 4-way hybrid in my first posting.

To recap the thread and add yet another approach, if you have n inputs each
m bits long, some choices are :-

1. simple m/2+1 CLB max accumulator in ~n clocks
2. ~nm/2 CLB max-mux tree in 1 clock
3. hybrid which takes ~nm/2k CLBs in k clocks
4. "parallel bit serial max" in ~n CLBs in ~m clocks
5. "serial bit serial max" in ~lg m + m/16 CLBs in m*n clocks

About 5: use a bit serial max state machine together with an m-bit FIFO
implemented using dual port RAM, to store the "current max".  Operate by
streaming in all the input words, serially, one bit at a time, into the max
machine.  Each m clocks it bit serially emits the max of all inputs so far.

Jan Gray



Article: 12120
Subject: Re: Free FPGA/HDL Newsletter Announcement
From: Markus Wannemacher <markus.wannemacher@fernuni-hagen.de>
Date: Wed, 30 Sep 1998 10:36:20 +0200
Links: << >>  << T >>  << A >>
APS (Richard Schwarz) wrote:
> 
>               ------------------------------------------------------
>                APS Newsletter Interim Announcements
>                ------------------------------------------------------
> 
> The next APS EDA Newsletter is about to be released. In this issue we
> will cover:

... well, but:

> 
> For those who wish to view the APS FPGA tools and Solutions now, the
> following websites apply:

.. following many, many links to different pages of APS.


Hallo Richard,
as you know, this is a non commercial newsgroup. 
cp. the threat "Too much advertising in this news group?" in july

<irony>
btw: WWW supports multiple hops. Therefore one link to your WWW server
is sufficient. Users can branch out by using a second link at no
extra charge.
</irony>

Markus Wannemacher

Article: 12121
Subject: Xilinx XC95xx JTAG program for DOS
From: Elder V Costa <elder@dixtal.com.br>
Date: Wed, 30 Sep 1998 08:38:25 -0300
Links: << >>  << T >>  << A >>
Hello

I have Foundation 1.4 and have developed a board based on Xilinx XC95108
to be programmed in system. Foundation JTAG programming tools work only
on Windows 95 or NT so I cannot program the device on DOS. I would not
like to oblige my production personnel to install the Windows based
program (fairly complicated and tricky process) and some test tools we
have work fine only on real mode DOS so they would have to reboot their
computer to switch between programming and testing. Older versions of
Foundation software support DOS (Eztag) but it does not recognize some
commands in the version 1.4's jedec file.

Does somebody have suggestions or a software to control the parallel
programming cable through DOS?

Thanks in advance for your help
Article: 12122
Subject: Re: Which FPGA tool is better
From: John Willoughby <jww@viewlogic.com>
Date: Wed, 30 Sep 1998 11:20:29 -0400
Links: << >>  << T >>  << A >>
Check out www.Viewlogic.com. Great tools (Fusion/SpeedWave for VHDL
simulation, FPGA-Express for synthesis, etc.) integrated under the
Intelliflow manager makes a very easy-to-use package from Viewlogic, the
leader in FPGA design solutions.

John Huang wrote:

> I want to buy a FPGA tool, do you recommand which
> one is better, how about Accolade  and Aldec?
>
> John Huang



--
*-------------------------------------------------------*
* John Willoughby           ジヨン ウイロビイ         *
* System Simulation Mktg    office: 508-303-5238        *
* Viewlogic Systems         mobile: 508-254-9608        *
* 293 Boston Post Rd West   fax: 508-460-7826           *
* Marlboro, MA 01752        email: jww@viewlogic.com    *
*                                                       *
* "Well done is better than well said" - Ben Franklin   *
*-------------------------------------------------------*


Article: 12123
Subject: Re: Efficient max-function architecture? -- "parallel bitwise max"
From: "Jan Gray" <jsgray@acm.org.nospam>
Date: Wed, 30 Sep 1998 08:50:39 -0700
Links: << >>  << T >>  << A >>
Jan Gray wrote in message <6usptm$d1$1@news-2.news.gte.net>...
>5. "serial bit serial max" in ~lg m + m/16 CLBs in m*n clocks
>
>About 5: use a bit serial max state machine together with an m-bit FIFO
>implemented using dual port RAM, to store the "current max"...

Oops, we don't need an m-bit FIFO, but rather a simple m-bit shift register.
Looking to http://www.xilinx.com/xapp/xapp052.pdf for inspiration, the m-bit
SR can be implemented in just 2 + m/32 CLBs so I should rather have written:

5. "serial bit serial max" in ~4 + m/32 CLBs in m*n clocks

Jan Gray

Article: 12124
Subject: need fpga contract work
From: "K. Y. Chan" <kychan@hintcorp.com>
Date: Wed, 30 Sep 1998 10:40:09 -0700
Links: << >>  << T >>  << A >>
We have a Verilog RTL design that needs FPGA for demonstration

Gate count - less than 10K (ASIC gates)
Speed - 33Mhz
Interface - PCI
Package - 208-pin PQFP
Device - Non-SRAM based FPGA (no EPROM on board)

We need conversion, place & route and programming service.
Anybody who is interested can send me e-mail at kychan@hintcorp.com

Thanks
K. Y. Chan
HiNT Corp.




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