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Messages from 12025

Article: 12025
Subject: Re: Efficient max-function architecture?
From: s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb)
Date: Thu, 24 Sep 1998 21:40:35 GMT
Links: << >>  << T >>  << A >>
On Wed, 23 Sep 1998 20:19:47 -0400, Ray Andraka
<no_spam_randraka@ids.net> wrote:

>This is the same as a macro I use.  Synthesis won't create this structure
>without alot of monkeying around.  With schematics it works just fine with a few

BZZZT, so sorry.

max_out <= data_a when data_a > data_b else data_b ;

does just fine from Leonardo Spectrum.

Nice carry chain, plus the mux, all rolled into one CLB.
I get 5 CLBs for Xilinx as one would expect. No RLOCs, no FMAPs, just
synthesis. :-)

Stuart
For Email remove "NOSPAM" from the address
Article: 12026
Subject: Re: Design Security Question
From: madarass@cats.ucsc.edu (Rita Madarassy)
Date: 24 Sep 1998 22:18:18 GMT
Links: << >>  << T >>  << A >>
In article <fliptronEz2vAt.JC4@netcom.com>,
Philip Freidin <fliptron@netcom.com> wrote:
>Well Catalin, since you kept me honest yesterday, let me do the same for 
>you :-) :-)
>
>As has been pointed out many times in this group, the SRAM FPGAs can
>potentially be the MOST secure form of digital logic on a board, and this
>is through the use of battery back-up of the FPGA, and only loading the
>bit stream once, at the factory. More secure than EPLDs, PALs, anti-fuse
>FPGAs, and even ASICs. 

I do not think this solution is too realistic.  All these FPGAs will
draw an estimated minimum of about 1mA to about 4ma.  However, guaranteed
data book values  are about 10ma for most FPGAs out there.  

I don't think there are cheap rechargeable batteries out there
that can hold this device for more than a month without recharging.

Can you imagine having to call the board vendor because your FPGAs
are empty because your system has been in storage for a couple of months?  

For these reasons the most practical solution nowadays is a CPLD.
I know Lattice and Phillips are coming out with CPLDs in the 30K gate
range.



>
>This technique never exposes the bitstream to the potential copier, and
>the level of effort to open the package while maintaining power, so that
>the part could be put into an e-beam prober should be as impossible as
>skiing through a revolving door. (you also need an e-beam voltage contrast
>prober, which are not to cheap either).
>
>For this to be reasonably practicle, you should choose a Xilinx part that 
>is specifically designed for low power, such as the XC3000 or the XC4000L
>
>Philip.
>
>In article <35F7D624.DCE36E36@spam.com> Catalin <no@spam.com> writes:
>>Eric W Braeden wrote:
>>
>>> Q: Lets say I were going to use a Xilinx Spartan XCS40 in a design.
>>>      That would probably mean I would use the XC17S40 SPROM.
>>>      How would you keep anyone who want to from cloning your design?
>>>      I don't see any mention of security in the Xilinx pages. How do you
>>>      load your FPGA without exposing your loadable image to hardware
>>>      hackers?
>>>
>>> TIA
>>>
>>> Eric
>>
>>Hi Eric,
>>
>>There is no way to do what you ask with SRAM based FPGAs. While reverse
>>engineering of the FPGA design is hard (at least in the Xilinx case), simple
>>duplication of the bitstream is easy. No matter what FPGA configuration
>>method you use the loadable image will be exposed on the part pins at
>>startup. A simple logic analyzer is all you need to capture it.
>>
>>One solution to your problem could be the use of a small (and cheap) EPLD,
>>something like Xilinx XC9536 or Vantis MACH111SP which can be protected
>>against readback and make the FPGA design work only in the presence of this
>>EPLD.  And remember, there is no absolute copy protection scheme - all you
>>can do is make copying hard enough to deter would be hackers.
>>
>>Catalin Baetoniu
>>
>>
>
>


Article: 12027
Subject: Re: Design Security Question (another solution)
From: madarass@cats.ucsc.edu (Rita Madarassy)
Date: 24 Sep 1998 22:21:05 GMT
Links: << >>  << T >>  << A >>

Hello there

This solution sounds great.  I hope it is not in the zillion dollar range.


 
In article <35F9D6F3.DB1EDF8@cam.org>, John McCluskey  <jqm@cam.org> wrote:
>Actually, there is another solution, used by a certain company in my
>area. This is quite nice.   They use a Dallas 8051 with the encrypted
>address/data bus, and store the code in a big SRAM that has a small
>lithium cell for backup.  The 8051, of course, can download any FPGA
>on the board, since the whole board is enclosed in a hermetically sealed
>stainless steel container.  If the container is punctured, the SRAM goes
>pffff!   Along with the bitstream stored in the FPGA.   The system also
>renders it impossible to upgrade the firmware without completely rebuilding
>the enclosure, which is ultrasonically welded shut after the SRAM is loaded.
>It is so difficult to open the enclosure without damaging the board, that
>they
>typically just junk the models that need firmware updates.   From what I
>understand, the physical enclosure not only has a pressure sensor, but a
>wiring grid that dumps the memory if any wire is severed.  Real tough to
>break into without losing the data.
>
>John McCluskey
>
>Philip Freidin wrote:
>
>> In article <35F81115.49D336D4@spam.com> Catalin <no@spam.com> writes:
>> >Your solution is OK and from a security point of view has obvious
>> >advantages but is limited to small and/or low power FPGAs. What if my
>> >design is an XC4062XL-09? You have also to deal with the problem of
>> >battery discharge or failure. Your client might not like living with a
>> >Damocles sword above his head all the time
>> >:-).
>> >Catalin Baetoniu
>>
>> Two words: Big Batteries
>>
>> Seriously, when not clocked, and the I/O pins are tristated (use GTS),
>> and you have tied the design, and not used pullups on the internal tbuf
>> lines, the XL parts are supposed to have a Quiescent current of 5mA max
>> (see page 4-72 of the 1/98 data book). The real number is probably lower
>> than this.
>>
>> This is not beyond the realm of battery backup, but certainly isn't going
>> to last long on a coin-cell. Two or three AA size ni-cad batteries though
>> would be fine for a system that is not turned off for days at a time.
>> An AA rechargeable will supply 5mA for 130 hours or more, depending on
>> chemistry. AA nicads are rated for 650 to 800mAH. NMH batteries are
>> around 1250mAH ( 250 hours at 5mA).
>>
>> For this type of design protection, the effort you put into protecting
>> your design is proportional to how hard you want to make it for those who
>> you think might rip you off.
>>
>> Philip.
>
>
>


Article: 12028
Subject: Re: Xilinx Spartan vs. 4K series
From: madarass@cats.ucsc.edu (Rita Madarassy)
Date: 24 Sep 1998 22:36:58 GMT
Links: << >>  << T >>  << A >>
For practical reasons, there is absolutely no difference
between the spartan and the 4KE part.  The spartan
is just a lame re spin of the 4000E part.
Although the specification tells you that the carry chain 
in spartan goes only one way, in reality it goes both ways.
If you don't believe me just try downloading the equivalent
4000E bitstream with downwards carry chain to a spartan device
and you will see that it works!!!

Also, all the configuration modes are functional in the silicon
but they are not tested. The only important difference between spartan
and the 4000E is that only one mode pin is used so the user
is constrained to use serial configuration. This is done by bonding
all the mode pins together into one package pin.
The other not so important difference is that the spartan is a
super shrink of the 4000E (hibrid 0.5u transistor/0.35u metal)

As for the rest, spartan is  bitstream compatible with 4000E 
and EVERY SINGLE BIT OF THE CONFIGURATION BITSTREAM MEANS EXACTLY
THE SAME THING IN BOTH PARTS.
 
As for not being pin compatible, the reason spartan have more power
and ground pins is to allow footpring compatibility for the future
spartan xl parts.  But I bet you can ignore these extra pins and it will
still work.

This is what you get from a company that is obviously running out of ideas
:
 

In article <6ta2v7$q14$1@news-2.news.gte.net>,
Jan Gray <jsgray@acm.org.nospam> wrote:
>Allan Herriman wrote in message <35f8827c.4654371@newshost>...
>>On Thu, 10 Sep 1998 17:26:09 -0700, "Matthew Robinson"
>><NOSPAMmprREMOVE@dolby.com> wrote:
>>>Hello,
>>>I've used xilinx 4KE series in the past, and am interested in the Spartan
>>>series -- what is the down side?  I can't see andy differences in the Data
>>>Sheets - am I missing something?
>>
>>1. Lower cost
>>2. Not pin compatible.  (more VCC pins, which is a good thing)
>>3. No wide decoders.
>>4. Carry chains only go in one direction.
>
>
>5. No parallel configuration modes -- only master serial and slave serial.
>6. No MD0, MD1, MD2 pins.
>7. No asynchronous distributed RAM mode -- only synchronous.
>8. No WANDs on long lines -- but tristate buses OK.
>
>See e.g. http://www.xilinx.com/xcell/xl28/xl28_4.pdf.
>
>Jan Gray
>
>
>


Article: 12029
Subject: Re: How to reduce ringing/ground bounce from FPGA output pin?
From: Nestor Caouras <nestor@macbeth.ece.concordia.ca>
Date: 24 Sep 1998 22:38:20 GMT
Links: << >>  << T >>  << A >>


Thanks for all the suggestions.
 
For the time being I could only try the ones with discrete components.  I
I believe that I do need 50 ohm line drivers since I am using a 50 ohm coax
cable to deliver the clock to its destination. Termination resistors do help
but don't alleviate the problem completely which why I probably need the 50
ohm line drivers.
 
A diode clipping circuit does seem to help as well by limiting the negative
spike to the forward bias voltage of the diode.  A 0.3V fast switching diode
does the trick but I suspect this should only be a temporary solution.
 
Thanks again for your advice.
 
Nestor
 

Article: 12030
Subject: Re: Xilinx Spartan vs. 4K series
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: 24 Sep 1998 23:10:00 GMT
Links: << >>  << T >>  << A >>
Rita   Madarassy <madarass@cats.ucsc.edu> wrote in article
<6uehia$3k@darkstar.ucsc.edu>...

[snip]
 
> This is what you get from a company that is obviously running out
of ideas
> :

Do you have any better ideas? 

-- 
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
apeters@noao.edu.NOSPAM


Article: 12031
Subject: Re: FPGA information
From: Phil Hays <spampostmaster@sprynet.com>
Date: Thu, 24 Sep 1998 21:06:25 -0700
Links: << >>  << T >>  << A >>
Peter wrote:
> 
> Could anyone point me in the right direction as to where I could get
> some broad information about FPGAs?

The big two are:

http://www.xilinx.com

and

http://www.altera.com


Other interesting vendors include:

atmel, cypress, gatefield, quicklogic and others.


>  I have searched the web to no avail and require information such 
> as performance, software, gate length, number of metal levels, 
> density, I/O, speed, turn time and cost.

FPGA's are field programmable gate arrays.  The time to load a design
into a part is on the very rough order of seconds.  The main decision is
between RAM based parts, which load fast and need to be loaded
everytime, flash based parts and one-time programable parts.

Performance for a few specialized tasks can be in the 100's of MHz, but
a more realistic range is 30-70 MHz.

Software ranges from free packages for a very few parts to about $US 100
for some nice basic packages covering a lot of parts to very nice
toolsets for many thousands of $US.

Gate lenght and metal levels are not important.  The user doesn't see
them.

Density and number of I/O's go up to perhaps a million gates and many
hundreds of pins: far more than a novice user can use.

Turn time of a design is on the very rough order of an hour.  Can be a
lot less for small designs: can be a lot more for huge designs.

Cost for the parts range from a few $US to thousands $US.


-- 
Phil Hays
"Irritatingly,  science claims to set limits on what 
we can do,  even in principle."   Carl Sagan
Article: 12032
Subject: Re: How to reduce ringing/ground bounce from FPGA output pin?
From: Rickman <spamgoeshere4@yahoo.com>
Date: Fri, 25 Sep 1998 00:33:30 -0400
Links: << >>  << T >>  << A >>
Nestor Caouras wrote:
> 
> Thanks for all the suggestions.
> 
> For the time being I could only try the ones with discrete components.  I
> I believe that I do need 50 ohm line drivers since I am using a 50 ohm coax
> cable to deliver the clock to its destination. Termination resistors do help
> but don't alleviate the problem completely which why I probably need the 50
> ohm line drivers.
> 
> A diode clipping circuit does seem to help as well by limiting the negative
> spike to the forward bias voltage of the diode.  A 0.3V fast switching diode
> does the trick but I suspect this should only be a temporary solution.
> 
> Thanks again for your advice.
> 
> Nestor
 
It sounds like you are on the right track, but I doubt that a new driver
will cure your problem. The ringing you describe is not caused by the
driver. It is caused by a mismatch in the impedance of the line with the
receiver. You should try a parallel termination at the receiver. 

A weak driver will cause a slow edge which can allow noise to cause
multiple triggering. But you don't sound like you have that problem. 

-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.
Article: 12033
Subject: Re: Which FPGA tool is better
From: Richard Schwarz <aps@associatedpro.com>
Date: Fri, 25 Sep 1998 01:12:56 -0400
Links: << >>  << T >>  << A >>


John,

Aldec(Foundatiom)  and Accolade are both great tools. Both are available
from APS at http://www.associatedpro.com
I can go over the plus and minus of each. Drop me a line.



John Huang wrote:

> I want to buy a FPGA tool, do you recommand which
> one is better, how about Accolade  and Aldec?
>
> John Huang
>





--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

    Richard Schwarz, President
    Associated Professional Systems Inc. (APS)
    email: richard@associatedpro.com
    web site: http://www.associatedpro.com
    Phone: 410-569-5897
    Fax:   410-661-2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/




Article: 12034
Subject: Re: FPGA information
From: Richard Schwarz <aps@associatedpro.com>
Date: Fri, 25 Sep 1998 01:17:19 -0400
Links: << >>  << T >>  << A >>


There are any number of sites. Try these:

http://www.associatedpro.com
http://www.xilinx.com
http://www.optimagic.com
http://www.lucent.com
http://www.altera.com

Peter wrote:

> Could anyone point me in the right direction as to where I could get
> some broad information about FPGAs?
>  I have searched the web to no avail and require information such as
> performance, software, gate length, number of metal levels, density,
> I/O, speed, turn time and cost.
> Any help on this matter would be sincerely appreciated.
>





--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

    Richard Schwarz, President
    Associated Professional Systems Inc. (APS)
    email: richard@associatedpro.com
    web site: http://www.associatedpro.com
    Phone: 410-569-5897
    Fax:   410-661-2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/




Article: 12035
Subject: Re: FPGA information
From: Daniel K Elftmann <elftmann@ix.netcom.com>
Date: Fri, 25 Sep 1998 10:33:38 GMT
Links: << >>  << T >>  << A >>
In article <360B16C1.7D53@sprynet.com>,
	Phil Hays <spampostmaster@sprynet.com> wrote:

>Peter wrote:
>> 
>> Could anyone point me in the right direction as to where I could get
>> some broad information about FPGAs?
>
>The big two are:
>
>http://www.xilinx.com
>
>and
>
>http://www.altera.com
>
>
>Other interesting vendors include:
>
>atmel, cypress, gatefield, quicklogic and others.
>

Dan Elftmann
Actel Northeast Field Applications Engineer

There's also a little FPGA company called ACTEL, which was the first company to offer Antifuse
based FPGAs.  We are the #1 supplier of FPGAs to the HiRel (Military/Avionics/Space) marketplace. 
The newest family of devices, the SX devices (.35u metal to metal antifuse) can easily operate in
the 100-150MHz range.  We recently acquired the rights to market and sell the .25u Gatefield
devices as well.  

http://www.actel.com

Phil must have something against Actel.  Sorry, just hate being left off the list.

>
>>  I have searched the web to no avail and require information such 
>> as performance, software, gate length, number of metal levels, 
>> density, I/O, speed, turn time and cost.
>
>FPGA's are field programmable gate arrays.  The time to load a design
>into a part is on the very rough order of seconds.  The main decision is
>between RAM based parts, which load fast and need to be loaded
>everytime, flash based parts and one-time programable parts.
>
>Performance for a few specialized tasks can be in the 100's of MHz, but
>a more realistic range is 30-70 MHz.
>
>Software ranges from free packages for a very few parts to about $US 100
>for some nice basic packages covering a lot of parts to very nice
>toolsets for many thousands of $US.

The Actel Designer Lite software can be downloaded from our web site for free and includes VHDL
synthesis, timing driven place and route, and static timing analysis tools for devices up to the
A42MX16 or A54SX16.

>
>Gate lenght and metal levels are not important.  The user doesn't see
>them.
>

Not totally true, user sees this in the routability, die size (thus cost), and performance.

>Density and number of I/O's go up to perhaps a million gates and many
>hundreds of pins: far more than a novice user can use.
>
>Turn time of a design is on the very rough order of an hour.  Can be a
>lot less for small designs: can be a lot more for huge designs.
>
>Cost for the parts range from a few $US to thousands $US.
>
>
>-- 
>Phil Hays
>"Irritatingly,  science claims to set limits on what 
>we can do,  even in principle."   Carl Sagan

 
Article: 12036
Subject: Re: Design Security Question
From: Daniel K Elftmann <elftmann@ix.netcom.com>
Date: Fri, 25 Sep 1998 10:41:15 GMT
Links: << >>  << T >>  << A >>
In article <6uegfa$s4o@darkstar.ucsc.edu>,
	madarass@cats.ucsc.edu (Rita   Madarassy) wrote:

>In article <fliptronEz2vAt.JC4@netcom.com>,
>Philip Freidin <fliptron@netcom.com> wrote:
>>Well Catalin, since you kept me honest yesterday, let me do the same for 
>>you :-) :-)
>>
>>As has been pointed out many times in this group, the SRAM FPGAs can
>>potentially be the MOST secure form of digital logic on a board, and this
>>is through the use of battery back-up of the FPGA, and only loading the
>>bit stream once, at the factory. More secure than EPLDs, PALs, anti-fuse
>>FPGAs, and even ASICs. 
>
>I do not think this solution is too realistic.  All these FPGAs will
>draw an estimated minimum of about 1mA to about 4ma.  However, guaranteed
>data book values  are about 10ma for most FPGAs out there.  

I agree, but if re-programmability is required, it may be the only solution.  If re
programmability is not needed then the Antifuse devices are a better solution.

>
>I don't think there are cheap rechargeable batteries out there
>that can hold this device for more than a month without recharging.
>
>Can you imagine having to call the board vendor because your FPGAs
>are empty because your system has been in storage for a couple of months?  
>
>For these reasons the most practical solution nowadays is a CPLD.
>I know Lattice and Phillips are coming out with CPLDs in the 30K gate
>range.
>

Don't forget that these CPLDs also have a maximum data retention time (10-20 years).  
If you look at security, cost, and total complexity of the solution the Antifuse FPGAs are the
best solution.  Careful about the gate range of the large CPLDs, the coarse grained architecture
can be very difficult to deal with above 10K gates and the deterministic delays of the old 22v10
architecture are not there anymore.  

Daniel K. Elftmann 
Actel Northeast Field Applications Engineer
>
>
>>
>>This technique never exposes the bitstream to the potential copier, and
>>the level of effort to open the package while maintaining power, so that
>>the part could be put into an e-beam prober should be as impossible as
>>skiing through a revolving door. (you also need an e-beam voltage contrast
>>prober, which are not to cheap either).
>>
>>For this to be reasonably practicle, you should choose a Xilinx part that 
>>is specifically designed for low power, such as the XC3000 or the XC4000L
>>
>>Philip.
>>
>>In article <35F7D624.DCE36E36@spam.com> Catalin <no@spam.com> writes:
>>>Eric W Braeden wrote:
>>>
>>>> Q: Lets say I were going to use a Xilinx Spartan XCS40 in a design.
>>>>      That would probably mean I would use the XC17S40 SPROM.
>>>>      How would you keep anyone who want to from cloning your design?
>>>>      I don't see any mention of security in the Xilinx pages. How do you
>>>>      load your FPGA without exposing your loadable image to hardware
>>>>      hackers?
>>>>
>>>> TIA
>>>>
>>>> Eric
>>>
>>>Hi Eric,
>>>
>>>There is no way to do what you ask with SRAM based FPGAs. While reverse
>>>engineering of the FPGA design is hard (at least in the Xilinx case), simple
>>>duplication of the bitstream is easy. No matter what FPGA configuration
>>>method you use the loadable image will be exposed on the part pins at
>>>startup. A simple logic analyzer is all you need to capture it.
>>>
>>>One solution to your problem could be the use of a small (and cheap) EPLD,
>>>something like Xilinx XC9536 or Vantis MACH111SP which can be protected
>>>against readback and make the FPGA design work only in the presence of this
>>>EPLD.  And remember, there is no absolute copy protection scheme - all you
>>>can do is make copying hard enough to deter would be hackers.
>>>
>>>Catalin Baetoniu
>>>
>>>
>>
>>
>
>

 
Article: 12037
Subject: Re: Design Security Question
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Fri, 25 Sep 1998 07:44:28 -0400
Links: << >>  << T >>  << A >>
Rita,

Although this is not practical in many applications, Philip's point is valid.
SRAM FPGAs offer the highest level of design security if you are willing to accept
the price.  There are many applications where this price is acceptable:  The most
notable are high security crypto and set-top boxes.  Basically, it comes down to
what price you are willing to pay to prevent access to your design.

The static power consumption also depends on the device.  For instance, an XC3000L
series has a power down mode which will hold the configuration while drawing a
maximum of 10uA.  If power-off current is critical in your application, you can
put the secret or key parts of your design in a part like the 3000L which is
protected as Philip described, and put less sensitive parts in other FPGAs which
are loaded in a more conventional manner.

For the record, here are the specified max quiescent currents for different
flavors of the XC4000 families:
4000E    3 mA (commercial range)
4000E    6 mA (industrial and mil temp range)
4000EX 25mA
4000XL  5mA
4000XV  5mA
Spartan   3mA (commercial temp range)
Spartan   6mA (industrial temp range)


Rita Madarassy wrote:

> >As has been pointed out many times in this group, the SRAM FPGAs can
> >potentially be the MOST secure form of digital logic on a board, and this
> >is through the use of battery back-up of the FPGA, and only loading the
> >bit stream once, at the factory. More secure than EPLDs, PALs, anti-fuse
> >FPGAs, and even ASICs.
>
> I do not think this solution is too realistic.  All these FPGAs will
> draw an estimated minimum of about 1mA to about 4ma.  However, guaranteed
> data book values  are about 10ma for most FPGAs out there.
>
> I don't think there are cheap rechargeable batteries out there
> that can hold this device for more than a month without recharging.
>
> Can you imagine having to call the board vendor because your FPGAs
> are empty because your system has been in storage for a couple of months?
>
> For these reasons the most practical solution nowadays is a CPLD.
> I know Lattice and Phillips are coming out with CPLDs in the 30K gate
> range.
>
> >
> >This technique never exposes the bitstream to the potential copier, and
> >the level of effort to open the package while maintaining power, so that
> >the part could be put into an e-beam prober should be as impossible as
> >skiing through a revolving door. (you also need an e-beam voltage contrast
> >prober, which are not to cheap either).
> >
> >For this to be reasonably practicle, you should choose a Xilinx part that
> >is specifically designed for low power, such as the XC3000 or the XC4000L
> >
> >Philip.



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 12038
Subject: Announcement: 200.000 Gates FPGA Prototyping Board
From: Lothar Brodbeck <brod@ks.sel.alcatel.de>
Date: Fri, 25 Sep 1998 14:13:22 +0200
Links: << >>  << T >>  << A >>


Hello reader,

i would announce two development boards of Alcatel Telecom.
The two boards are useful for ASIC prototyping and simulation.
We already used the boards to verify DSP algorithms written in
VHDL, to test the behaviour of PLL circuits, to built test
equippment (complex signal generators written in VHDL) for our
fab and for other applications.


Short description of the boards:

HW_SIM

* 200.000 gates logical resources (4*Altera EPF10K50)
  (300.000 gates if equpipped with 1EPF10K70)
* 2 Slots for SIMM memory modules (30 pin types)
* 2 on board oscillators (48,640 MHz, 16,384MHz)
* PBA size 233mm*210mm
* breadboard area
* reset circuit
* ...

DEV_KIT

* 20.000 gates logical resource (2*Altera EPF81188)
* on board oscillator (16,384 MHz)
* PBA size 233mm*160mm (possible splitting 2 times 100mm*160mm)
* breadboard area
* reset circuit
* ...

For more information about the development boards contact
one of the persons listed below.


Financial Questions:    R.Prestin@alcatel.de

Technical Questions:    brod@lts.sel.alcatel.de


Best regards Lothar Brodbeck

p.s.

An user wrote:  ... We successfully used the HW_SIM development
                board to verify our complex signal processing
                algorithm. ... The programming and the handling
                of the evaluation board stands out. ...


You can find a description and pictures of the boards using the
following address:

http://www.alcatel.de/telecom/asd/test_hw/topdevboard.htm





Article: 12039
Subject: FIR Filter Design
From: Juergen Otterbach <jotterba@rcs.sel.de>
Date: Fri, 25 Sep 1998 14:25:42 +0200
Links: << >>  << T >>  << A >>
Dear FPGA and VHDL users,
please let me know if you heard about problems using the Altera DSP Kit
to design a FIR filter in FLEX10K. Please let me know from what I have
to be aware.


Article: 12040
Subject: Cypress CPLDs
From: "Dan Parent" <dparent@itis.com>
Date: Fri, 25 Sep 1998 09:32:51 -0500
Links: << >>  << T >>  << A >>
I would like to here any comments/performance issues stemming from new
designs using the Cypress CYC374i-66JC CPLD or related Cypress CPLD parts.

We have just introduced a new product which utilizes the Cypress CPLD part
and are looking at re-designing the pcb to add additional features.  One
concern I had with the CPLD is the 5volt logic output only reaches
aproximately 3.7 to 4volts due to a diode drop.  No negative side effects
have been detected in the product's logic levels yet but we have only
produced about 500 units.   We may be switching to an Atmel or Altera
solution on the next pcb to overcome the voltage problem.

Otherwise, the CPLD has performed very well in the design.  The routing
capability of the Cypress part out performed Altera's early in the design
and timing has never been a problem.

Any design comments/suggestions are welcome.




Article: 12041
Subject: CardBus CIS useless?
From: gfang@pop.slkc.uswest.net
Date: Fri, 25 Sep 1998 08:55:28 -0600
Links: << >>  << T >>  << A >>
Hi everyone,
    I was trying to change the VPP power supply from the 3.3V default to
5V for the design I'm working on. No matter what value I put in the
ConfitEntry tuple (05) the VPP doesn't change, it's always the default
3.3V. Out of curiosity I deleted the CIS (output all '0'), the card
still works as if nothing happened, of course the VPP is still 3.3V.
    The information in the CIS seems to have been completely ignored by
the system!
    Another thing I noticed is that all the CardBus cards I tested,
including a network card, a SCSI card and the card I'm working on are
all listed in the system registry under the key PCI instead of PCMCIA. I
can't seem to find any trace of information provided in the CIS anywhere
in the system. I checked the device manager, also searched the entire
system registry, no identification or configuration information seems to
have be in anyway related to the CIS.
    Can someone provide some explanation to this? How to change VPP to
5V?
    Thanks in advance for any information.

George

Article: 12042
Subject: Re: CardBus CIS useless?
From: "Austin Franklin" <dar4kroom@ix.netcom.com>
Date: 25 Sep 1998 15:50:06 GMT
Links: << >>  << T >>  << A >>
>     Another thing I noticed is that all the CardBus cards I tested,
> including a network card, a SCSI card and the card I'm working on are
> all listed in the system registry under the key PCI instead of PCMCIA. I
> can't seem to find any trace of information provided in the CIS anywhere
> in the system.

CardBus IS PCI.  The CardBus devices are configured by the BIOS just like
PCI devices, they have exactly the same configuration space (except the
aforementioned CIS stuff...) and exactly the same bus pins and protocol
(with the excepetion of power and a few information pins).  All a CardBus
controller is, effectively, is a PCI bridge chip (though most CardBus
interface chips also recognize PCMCIA cards, and configure the slots bus
accordingly...PCMCIA is almost identical to ISA, and will not contain the
configuration etc. that CardBus cards do).

As far as power goes, that is determined by pins on the CardBus card, and
the card instructs the slot to power the card accordingly.  You can not
change this.

Austin Franklin
darkroom@ix.netcom.com

Article: 12043
Subject: Re: Design Security Question
From: madarass@cats.ucsc.edu (Rita Madarassy)
Date: 25 Sep 1998 16:26:59 GMT
Links: << >>  << T >>  << A >>
In article <6ufs5j$35j@sjx-ixn2.ix.netcom.com>,
Daniel K Elftmann  <elftmann@ix.netcom.com> wrote:
>>I do not think this solution is too realistic.  All these FPGAs will
>>draw an estimated minimum of about 1mA to about 4ma.  However, guaranteed
>>data book values  are about 10ma for most FPGAs out there.  
>
>I agree, but if re-programmability is required, it may be the only solution.  If re
>programmability is not needed then the Antifuse devices are a better solution.
>
>>
>>I don't think there are cheap rechargeable batteries out there
>>that can hold this device for more than a month without recharging.
>>
>>Can you imagine having to call the board vendor because your FPGAs
>>are empty because your system has been in storage for a couple of months?  
>>
>>For these reasons the most practical solution nowadays is a CPLD.
>>I know Lattice and Phillips are coming out with CPLDs in the 30K gate
>>range.
>>
>
>Don't forget that these CPLDs also have a maximum data retention time (10-20 years).  
>If you look at security, cost, and total complexity of the solution the Antifuse FPGAs are the
>best solution.  Careful about the gate range of the large CPLDs, the coarse grained architecture
>can be very difficult to deal with above 10K gates and the deterministic delays of the old 22v10
>architecture are not there anymore.  

There is a good reason why antifuse parts are slowly losing popularity.
Once companies like Actel or Quicklogic lose their juicy deals with the
military they will be out of business in no time.  As a matter of fact
there are already FPGA and CPLD parts in the military as well as in space.

Also, I never encountered an issue in the market with the 10 or 20 year
retention time.  Frankly speaking,  I don't think anybody cares anymore.
Thhe reprogramming can be part of a maintenance procedure after 10 years sinc
most systems with an expected lifespan of 10 years or more should require
maintenance.

Antifuse are a nightmare when it comes to prototyping.  A designer
will probably burn 20 or 30 parts before getting to the final design.
FAEs will  probably be nice and supply the designer with 2 or 3 parts
for the average oportunity design but I bet they will never give 30
or 40 spares to any ACTEL designer.

Xilinx dropped out of the antifuse business because they saw it as
a slow  growing market.  They would rather be a bit more rational
and lose money with the CPLD business for a while instead.
Maybe the Xilinx FAEs were getting sick of having to visit costumers



Anyways, getting back to the security business.  Even CPLDs are impossible
to break when it comes to security since it will require to look at all
the layers of the silicon and that is practically impossible.
I would say it should be easier to bribe the designer!!! :)





Article: 12044
Subject: Re: CardBus CIS useless?
From: "tom picard" <tomp@pvinc.com>
Date: Fri, 25 Sep 1998 09:27:40 -0700
Links: << >>  << T >>  << A >>
>CardBus IS PCI.  The CardBus devices are configured by the BIOS just like
>PCI devices, they have exactly the same configuration space (except the
>aforementioned CIS stuff...) and exactly the same bus pins and protocol
>(with the excepetion of power and a few information pins).  All a CardBus
>controller is, effectively, is a PCI bridge chip (though most CardBus
>interface chips also recognize PCMCIA cards, and configure the slots bus
>accordingly...PCMCIA is almost identical to ISA, and will not contain the
>configuration etc. that CardBus cards do).

All the above is the same as I understand it, ( well, no BIOS I am aware of
actually configures the cards, OSR2+   does it).

>As far as power goes, that is determined by pins on the CardBus card, and
>the card instructs the slot to power the card accordingly.  You can not
>change this.


My understanding is that there is a pointer in PCI config space that MUST
point to the CIS.
If this pointer is NULL, the OS will make its best guess what the voltage
the card requires, and program the controller accordingly. (maybe it guesses
a lower voltage so as not to damage the card, by a wrong guess).
maybe there is a new spec wherein the voltages are specified thru the pins
on the card, but i don't understand how it works..

>> The information in the CIS seems to have been completely ignored by the
system!
Is this "CIS pointer" in PCI config space setup?

tom



Article: 12045
Subject: Re: Xilinx 3000 family
From: z80@ds2.com (Peter)
Date: Fri, 25 Sep 1998 16:41:40 GMT
Links: << >>  << T >>  << A >>

There is nothing wrong with using XC3k devices today. They are
shipping by the million. The newer versions should run the old
bitstream without modifications, but due to the increased speeds you
may find some problems if you have e.g. used long lines to distribute
clocks.

>We were reworking a design on a board containing an old xc3030 Xilinx
>chip. In the mean time the xc3030 was substituted by Xilinx with the
>xc3030a or xc3030l. Lucent still does the original chips. Since the
>old boards still have the chip of the original families
>we would like to compile the design using the new Merged release, but
>doing a xc3030 compatible bitfile. The new SW does force you to chose a
>new family. In the Xilinx manual it states that the A and L families
>can use the old bitfiles.


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 12046
Subject: Re: Which FPGA tool is better
From: z80@ds2.com (Peter)
Date: Fri, 25 Sep 1998 16:41:40 GMT
Links: << >>  << T >>  << A >>

Viewlogic 4 (DOS, ex-1992) and XACT6.01, ex-1996.

No significant known bugs. Supports only older devices, but *they* are
cheap.

Only partly kidding :)

>I want to buy a FPGA tool, do you recommand which
>one is better, how about Accolade  and Aldec?


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 12047
Subject: Re: CardBus CIS useless?
From: gfang@pop.slkc.uswest.net
Date: Fri, 25 Sep 1998 11:09:02 -0600
Links: << >>  << T >>  << A >>
Yes, the CIS pointer points to an available space above 40h in the configuration
space where my CIS is located.
By the way, the CVS and CCD pins are only used to configure the VCC voltage, VPP
is supposed to be configured according to information in the ConfigEntry tuple
in the CIS.

============

tom picard wrote:

> Is this "CIS pointer" in PCI config space setup?
>
> tom



Article: 12048
Subject: Re: 3.3V PCI to 5V local bus interface?
From: "Stephen Peddle" <smp@spam.com>
Date: Fri, 25 Sep 1998 17:58:02 GMT
Links: << >>  << T >>  << A >>
I've also chosen to use the Spartan XL this way, but I'm going to bite the
bullet and add the buffers to isolate my XL from 5V signals.  There are two
other options however:

Option 1:
Leave the 3.3VPCI switch off and add your own clamping diodes externally.

Option 2:
10K10A parts have individually programable pin clamping switches.
caveat: Altera claims PCI compliance but won't guarantee CompactPCI
    compliance.  (and I thought they were the same?)


Steve


Article: 12049
Subject: Re: Anyone received Xilinx Foundation 1.5 ?
From: "Stephen Peddle" <smp@spam.com>
Date: Fri, 25 Sep 1998 18:04:37 GMT
Links: << >>  << T >>  << A >>
I just talked to my rep yesterday and was told Foundation 1.5 is shipping
... BUT
there are a lot of us using it, and it could take up to a month to complete
all the shipments.

ie if you need it right away, you should probably ask for it.

Also, when you get your 1.5, don't forget to check the web site for the
latest patches.  (Yes they have already uploaded some!)





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