Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
John_H wrote:
>
> Personally, for looking at common mode voltage, I'd connect the signal
> to the normal CML receiver and use the high-impedance FET probe to tap
> onto the signal. The signal fidelity may go from good to miserable with
> the extra impedance even if it is a "small" impedance; nothing's really
> "small" at Rocket IO rates.
>
Although not of help to the original poster with a non-balanced code,
a handy lab parlo{u}r trick from my long-gone-by OC-192 days is to run
the serializer output _backwards_ through a broadband bias-T.
Then just hang your scope or multimeter off the bias-T DC input to
look at the {low frequency} common mode levels.
( The notion of using a bias-T backwards to AC couple while measuring
DC levels is, for me, one of those obvious-after-the-fact things that
has come in handy on a number of occasions. )
Brian
Article: 121876Hello, I have to do some video scaling on 24-bit video for a 8-bit video dac and am looking for some help in scaling the data. The video image is 512 x 512 and each pixel is 24-bits. The video DAC is only 8- bits so I need to do some rescaling of the pixels. The images are arriving every 10msec but it is not crucial that I process each frame in 10msec, it could be 20msec but I cannot go beyond that because it will be noticable on the display. Does anyone know of some real-time algorithms that can help be scale my data without just throwing aways the LSB's. If anyone has done such a thing in an FPGA or know where I could get more information please let me know. Thanks, joeArticle: 121877
On Jul 13, 10:21 pm, "jjlind...@hotmail.com" <jjlind...@hotmail.com> wrote: Your pixel frequency seems to be about 25 MHz, i.e 40 nanoseconds per pixel. That should give you plenty of time for all sorts of algorithms, pipelined or not pipelined, if you really want to convert 24 bits into 8 bits. Or am I missing something? Peter Alfke > Hello, I have to do some video scaling on 24-bit video for a 8-bit > video dac and am looking for some help in scaling the data. The video > image is 512 x 512 and each pixel is 24-bits. The video DAC is only 8- > bits so I need to do some rescaling of the pixels. The images are > arriving every 10msec but it is not crucial that I process each frame > in 10msec, it could be 20msec but I cannot go beyond that because it > will be noticable on the display. Does anyone know of some real-time > algorithms that can help be scale my data without just throwing aways > the LSB's. If anyone has done such a thing in an FPGA or know where I > could get more information please let me know. > > Thanks, > joeArticle: 121878
My company may soon have to put together our first embedded system. Since we're beginners, we're probably not going to (a) know what we're doing, (b) have a good firm set of application requirements, (c) have a lot of embedded/programming experience. The target hardware would most likely be one of the Tensilica 32-bit cores, or an ARM/922 (probably not an ARM7 TDMI.) I realize that makes this question really really loaded, but given the criteria of "needs to be maintainable by non linux-gurus", what's the better embedded O/S choices? Can be commercial or open-source...since we're willing to pay a little more upfront for (hopefully) eaiser learning curve.Article: 121879
hi , i have a probelm while i am using the DCM for clock mutiply. i am using single DCM for my virtex 2 pro device. i have two sub modules and a top module. i need to use DCM in all the 3 modules (2 sub modules and top module). so i invoked dcm and component instantiation in all the 3 modules. but i am facing the problem while i am mapping . its throwing the error... like error: ERROR:LIT - IPAD symbol "clk77p76" is driving more than one loads. IPAD can only drive a single IBUF or two IBUFDS. If you are using a BUF instead of an IBUF, it may have been simplified, please use an explicit IBUF instead. can my dcm clk cannnot drive more than 2 loads ..... regards srikArticle: 121880
jjlindula@hotmail.com wrote: > Hello, I have to do some video scaling on 24-bit video for a 8-bit > video dac and am looking for some help in scaling the data. The video > image is 512 x 512 and each pixel is 24-bits. The video DAC is only 8- > bits so I need to do some rescaling of the pixels. The images are > arriving every 10msec but it is not crucial that I process each frame > in 10msec, it could be 20msec but I cannot go beyond that because it > will be noticable on the display. Does anyone know of some real-time > algorithms that can help be scale my data without just throwing aways > the LSB's. If anyone has done such a thing in an FPGA or know where I > could get more information please let me know. So this is RGB data, at 8 bits/channel, to monochrome 8 bits ? Simplest conversion is a sum and divide by 3. If you have multipliers, this could be appx as * 21 and /64 (Shift 6) You can do LSB rounding, to get within half a LSB, but you probably will not actually see that. Beyond that, what other scale did you have in mind ? - you could weight each of the RGB, and even do a Contrast/Brightness/Offset calc, -jgArticle: 121881
"Cla" <cla@sbcglobal.net> wrote: >My company may soon have to put together our first embedded system. >Since we're beginners, we're probably not going to (a) know what we're >doing, >(b) have a good firm set of application requirements, (c) have a lot of >embedded/programming experience. > >The target hardware would most likely be one of the Tensilica 32-bit >cores, or an ARM/922 (probably not an ARM7 TDMI.) > >I realize that makes this question really really loaded, but given the >criteria >of "needs to be maintainable by non linux-gurus", what's the better >embedded O/S choices? Can be commercial or open-source...since we're >willing to pay a little more upfront for (hopefully) eaiser learning curve. From what I've seen from Windows CE5.0 choose an OS where you have access to all the source (which isn't the case for WinCE 5.0). You'll need it to be able to fix bugs! I it where my call, I would choose Linux. It has a more layered structure which makes it possible to isolate a problem more quickly. Besides, you can prototype your software on a PC and then compile it for the embedded platform without changes. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 121882
<ekavirsrikanth@gmail.com> wrote in message news:1184395776.985541.34040@j4g2000prf.googlegroups.com... > hi , > > i have a probelm while i am using the DCM for clock mutiply. i am > using single DCM for my virtex 2 pro device. i have two sub modules > and a top module. i need to use DCM in all the 3 modules (2 sub > modules and top module). so i invoked dcm and component instantiation > in all the 3 modules. but i am facing the problem while i am mapping . > its throwing the error... like > > error: ERROR:LIT - IPAD symbol "clk77p76" is driving more than one > loads. IPAD can only > drive a single IBUF or two IBUFDS. If you are using a BUF instead > of an > IBUF, it may have been simplified, please use an explicit IBUF > instead. > > can my dcm clk cannnot drive more than 2 loads ..... > > regards > srik > You only need to instantiate a DCM in the top module.Article: 121883
Eilert, Thanks very much for your detailed response that is exactly what I needed. I have written a bash script that automatically verifies the functionality of a series of test circuits that use a specific module I've developed. I was trying to come up with a way to quickly verify that I haven't violated any rules with change I've made to that module. However, I have a college that developed part of his work in schematic, and I was having to open up ISE each time to convert the files into Verilog. Now I can do it with my bash script! It will save me quite a few steps. Thanks, CraigArticle: 121884
On 13 Jul, 16:11, Sandro <sdro...@netscape.net> wrote: > > Usually most command issued by the ISE GUI are appended to a file > <PATH_TO_THEPROJECT>/<PROJECT_NAME>.cmd_log Yes, this works, and I can see the commands that Eilert referred to in his post! This will be very handy in the future if I can't figure out how the GUI is doing something! Thanks, Craig.Article: 121885
On 13 Jul, 16:33, Duth <premd...@gmail.com> wrote: > As Eilert pointed out, you can use sch2verilog and sch2vhdl to convert > the schematic file that comes from ECS. This is the biggest confusion > I am hearing. ECS is the schematic capture tool you probably have > never heard this name used before. XST does not write out schematics. > XST is the Xilinx Synthesis tool. Basically what happens in the back > end is for us to convert it to HDL and then run XST on it. Yes, I used xst as an example because I did not know the name of the tool to use. I though it might be xst because the schematic files are always converted inside the ISE GUI whenever I run the ISE simulator, and this is where xst is run to compile the verilog files. > Regarding your question on whether you can mix schematic and HDL in > modelsim, the answer is no. Modelsim is a HDL simulator only. It > cannot simulate gates. This is why you can psuedo implement this by > the method that Eilert provided that is to write a tcl script that > runs sch2verilog and then runs the simulation. You can combine the > shell script and do file into one Tcl file if you use the exec > command. Thanks for confirming this. You've saved a lot of time looking for a way to do something that cannot be done! Regards, CraigArticle: 121886
In article <f78slk$fkp5@cnn.xilinx.com>,
austin <austin@xilinx.com> writes:
|> Seriously, a ohmmeter check may be dangerous: many use a 9 volt battery.
...but only as a supply voltage, not for testing.
Typically, the test voltage is below 2V on modern handheld instruments. My
4.5-digit Metex has 1.25V in all ranges, maximum current is about 0.5mA. The
diode tester runs with 3V, the max. current is about 1.3mA. I doubt that these
currents and voltages will in any way affect the chip, especially when the
operating (and leakage) currents are larger by a few orders.
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 121887>> So, the question is, would experienced people be willing to spend a few >> minutes reviewing my schematics to tell me if I have some obvious >> errors ? >> What format should I use ? I use Eagle, so I can give Eagle files or >> plain PDF. > > If you posted a link to the PDF, people would probably look... Obviously ! I wanted to ask for the preferred format first, though. I have used FPGAs but this is the first time I design a FPGA board, so it would really be cool to have some "divine intervention" from the experts here to zap my bugs before they are comitted into copper. So, here is a PDF of the schematics : http://home.peufeu.com/nik/fpga/board_v01/schema.pdf Since the free version of Eagle supports only one schematic sheet, this isn't very printable (since everything is on one page !)... also, it somehow converted the text to vector. Duh. Anyway, this is a simple FPGA board with a Spartan 3E-500, 32 bit SDRAM, and a SMSC LAN9117 as network MAC+PHY. I went for simplicity so it has linear regulators ; and I didn't try to use the OpenCores MAC. This MAC chip has a nice interface and is supposed to be easy to program. Also drivers are available for happy hacking. I won't be using any OS since application is Ethernet streaming up to 100 Mbps and the Linux TCP/IP overhead is way too large for poor Microblaze. SDRAM and MAC do NOT share a multiplexed bus since I want to be able to extract some good network performance from this design. Board layout needs to be done. This depends on the actual parts matching the Eagle libraries. Since I drew most of the large parts footprints from the datasheets, this means this will have to wait until I actually order and receive the parts from DigiKey, and put them into a laser printed paper version of the PCB to check alignment of the pins with the pads and holes. I hate it when the pins don't fit in the holes. And, the FPGA pin-swapping obviously depends on the routing. Which is waiting for the parts. Chicken and egg ! Hence, in this schematic, all the address and data busses are not connected, and some signals too. Please do not look at this, since this is the easy part. Instead, I would really like some advice on the FPGA specific stuff, which is the hard part for me since it's the first time : - did I route the clocks to the right pins so the DCMs are happy ? - should the FPGA generate the clock to be sent through the connector or should I send the oscillator's output ? - is the power supply OK ? - will it really program itself from the flash as the datasheet says ? - will my JTAG work ? - is my Ethernet jack schematic and layout OK ? - will it smoke ? - will my SPI interface & prog_b jumper be enough to rescue a crapped up flash bitstream ? - does it suck ? - do I need to add resistors to the data lines ? Well I guess you get the idea ;) I will build a shrine to a guy nice enough to save me a PCB iteration !!! Thanks a lot, PierreArticle: 121888
On Jul 14, 12:05 am, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:
> jjlind...@hotmail.com wrote:
> > Hello, I have to do some video scaling on 24-bit video for a 8-bit
> > video dac and am looking for some help in scaling the data. The video
> > image is 512 x 512 and each pixel is 24-bits. The video DAC is only 8-
> > bits so I need to do some rescaling of the pixels. The images are
> > arriving every 10msec but it is not crucial that I process each frame
> > in 10msec, it could be 20msec but I cannot go beyond that because it
> > will be noticable on the display. Does anyone know of some real-time
> > algorithms that can help be scale my data without just throwing aways
> > the LSB's. If anyone has done such a thing in an FPGA or know where I
> > could get more information please let me know.
>
> So this is RGB data, at 8 bits/channel, to monochrome 8 bits ?
> Simplest conversion is a sum and divide by 3.
> If you have multipliers, this could be appx as * 21 and /64 (Shift 6)
>
> You can do LSB rounding, to get within half a LSB, but you probably
> will not actually see that. Beyond that, what other scale did you have
> in mind ? - you could weight each of the RGB, and even do a
> Contrast/Brightness/Offset calc,
>
> -jg
Hello all, thanks for responding to my post. The data rate may seem
strange 10msec, but that's the rate. The video data is actually
grayscale or I guess that would be monochrome data. I did find an
algoritm off the net :
pix + frameminValue
y = ----------------------------------------------- * 2^b
framemaxValue - frameminValue
where b is the number of bits of the video dac. In this equation I
need to find the max and min values of the image frame. I might have
to apply the max and min value on the next image frame which shouldn't
be a problem. Does this equation sound do-able for a Stratix II FPGA?
thanks,
joe
Article: 121889jjlindula@hotmail.com wrote: > On Jul 14, 12:05 am, Jim Granville <no.s...@designtools.maps.co.nz> > wrote: >> jjlind...@hotmail.com wrote: >>> Hello, I have to do some video scaling on 24-bit video for a 8-bit >>> video dac and am looking for some help in scaling the data. The video >>> image is 512 x 512 and each pixel is 24-bits. The video DAC is only 8- >>> bits so I need to do some rescaling of the pixels. The images are >>> arriving every 10msec but it is not crucial that I process each frame >>> in 10msec, it could be 20msec but I cannot go beyond that because it >>> will be noticable on the display. Does anyone know of some real-time >>> algorithms that can help be scale my data without just throwing aways >>> the LSB's. If anyone has done such a thing in an FPGA or know where I >>> could get more information please let me know. >> So this is RGB data, at 8 bits/channel, to monochrome 8 bits ? >> Simplest conversion is a sum and divide by 3. >> If you have multipliers, this could be appx as * 21 and /64 (Shift 6) >> >> You can do LSB rounding, to get within half a LSB, but you probably >> will not actually see that. Beyond that, what other scale did you have >> in mind ? - you could weight each of the RGB, and even do a >> Contrast/Brightness/Offset calc, >> >> -jg > > Hello all, thanks for responding to my post. The data rate may seem > strange 10msec, but that's the rate. The video data is actually > grayscale or I guess that would be monochrome data. I did find an > algoritm off the net : > pix + frameminValue > y = ----------------------------------------------- * 2^b > framemaxValue - frameminValue > > where b is the number of bits of the video dac. In this equation I > need to find the max and min values of the image frame. I might have > to apply the max and min value on the next image frame which shouldn't > be a problem. Does this equation sound do-able for a Stratix II FPGA? > > thanks, > joe This is doable in the FPGA only if you can read the frame twice. The internal storage won't buffer a 512x512x24 image. Once past that, this method is beyond simple but probably not accurate for your needs. If your 24 bits are true grayscale, this shift of black and white levels may be desirable but it may be detrimental depending on your image. What is the nature of your 24 bit data? To have so much grayscale information usually suggests there's specific purpose besides grayscale display. If you wish to display the nuances of the grayscale so your 8-bit output doesn't present "terracing" for a smooth transition between two close levels of gray, you can dither the error (the fraction that doesn't fit in 8 bits) in the adjacent pixels. Error diffusion is used extensively in imaging - at least from the print and copy side - and is probably documented for display applications as well. If your grayscale isn't typically spread across most of the full 24'h000000 -> 24'hffffff range, the algorithm you found on the net will help expand the dynamic range of your image but will still throw away the lower bits. If your image is a polar bear eating vanilla ice cream in a snowstorm, this re-scaled image will produce VERY unusual results since many of those white, white, white pixels are now black or dark gray. I'd suggest that for a 512x512 image where the total visual integration isn't very large, 8 bits are easily discarded and not all of the remaining 8 "fraction" bits are useful; for grayscale, I'd think 4 bits of fraction would be hard to discern from 3. But it's a pretty simple matter to retain the full 16-bit error for the one line of data that has to be retained for a proper error diffusion. Its overkill to use 16 bits when 3 is wholly sufficient, but you have 24 bits of data. I'm still not sure why. No application I've ever known has 24 bits of grayscale data. A good error diffusion for large, smooth areas isn't the simplest thing to do but can easily be done (performance and resource-wise) in an inexpensive FPGA family. For print purposes I worked on a design recently that was running error diffusion (proprietary algorithm, sorry) at a mild 50 MHz. Because of all the tweaks for high-quality printing at high resolution (compared to your image, at least) the resources were much larger than most other functions we needed but at 512 pixel width AND use of grayscale rather than bi-level, your requirements would drop significantly. If all you want is a "rough stab" at diffusing the error to avoid the terracing in a grayscale image, the implementation is probably extremely simple compared to our bi-level output requirements in printing where there's either a dot or there isn't. If your 24-bit video isn't really 24 bits of grayscale, I hope you figure out what you want to accomplish. If it is RGB data that you want to convert to monochrome, look for colorspace conversion. The matrix operations are simple to convert from one color space to another (such as RGB to YCrCb or just Y for your grayscale needs) but is not a simple "sum and divide" suggested earlier. It's simple, but not that simple. Good luck in defining your requirements and I hope your implementation is fun!Article: 121890
Georg. Good to know! AustinArticle: 121891
Dear I need to "make a script (or batch file) for ISE tool" in order to "crate and map" user libraries". My VHDL code looks like following : ------------------------------------------------------------- -- vhdl for TOP module ..... LIBRARY submodulelib; USE submodulelib.submodule_cmp_pkg.ALL; ..... ------------------------------------------------------------- In ISE tool, I did MANUALLY in the GUI as following : Project -> Add Source -> VHDL source Problem is that there are too many user libraries, so that these steps in GUI are too time-consuming. I want to use a script (in command-line) for "library creation and mapping". Could anyone help me with "how to create library and map user libraries", without using GUI? I am using Linux (also Windows) and ISE 8.2. By the way, I did following for MODELSIM simulation and it worked : -------------------------------------------------------------- -- script for MODELSIM -------------------------------------------------------------- /* generating library */ vlib submodulelib /* library mapping */ vmap submodulelib /opt/data/design/sim/submodulelib /* source compile */ /* package */ vcom -work submodulelib /opt/data/design/src/submodule_cmp_pkg.p.vhdl /* entity */ vcom -work submodulelib /opt/data/design/src/submodule.e.vhdl /* architecture */ vcom -work submodulelib /opt/data/design/src/submodule_rtl.a.vhdl /* configuration */ vcom -work submodulelib /opt/data/design/src/submodule_cfg.c.vhdlArticle: 121892
"John_H" <newsgroup@johnhandwork.com> wrote in message news:wY5mi.4113$225.2543@trndny03... > If all you want is a "rough stab" at diffusing the error to avoid the > terracing in a grayscale image, the implementation is probably extremely > simple compared to our bi-level output requirements in printing where > there's either a dot or there isn't. I find a one dimensional diffusion works suprisingly well, if you're just dropping a few lsbs.Article: 121893
On 2007-07-14, PFC <lists@peufeu.com> wrote: > > http://home.peufeu.com/nik/fpga/board_v01/schema.pdf Normally I would illustrate the regulator (like your LT1764A) with the required output cap right next to it, just to clarify which cap is meeting the requirements of the regulator. Considering the datasheet dedicates about 3.5 pages to the output cap... Also, I'd question your 220u on that rail. Take a look at the datasheet figure 9 -- it illustrates the performance of the 1.2V regulator with different output cap networks. Notice the 100u poly cap has a 35mOhm ESR. If your 220u is a plain old elecrolytic it's probably useless. Offhand I'm not seeing where you get voltage rails like MAC_VDD_PLL, but if they are other common voltages you should make semi-isolated versions of them with cap-ferrite bead-cap. If any of the key analog voltages are your 3.3V (which you get from off-board) I'd strongly consider making a special, clean 3.3V from some higher rail just for that. You might need a multi-voltage reset controller to avoid power sequencing problems. You'd have to check all the datasheets to see if they're all tolerant of their rails coming up in the order produced by your board. Speaking of which, I wouldn't drive your MAC reset with FPGA_DONE. Use a dedicated IO for it. You can end up making it 'assign MAC_RESET=0' but if you need it it will be changable. Where you split your clk into CLK_OUT and FPGA_CLK, put a series R on both legs. > - will my JTAG work ? You need some pullups there for when the jtag connector is not hooked up. > - will it smoke ? Nah, if you make schematic errors it probably just "won't work", unless your symbols have mistakes, in which case it might smoke. ;-) > - will my SPI interface & prog_b jumper be enough to rescue a crapped up > flash bitstream ? Via what? You'll be able to load bitstreams directly via JTAG no matter what the state of the flash. > - does it suck ? It's probably going to cost you more than buying a dev board with equivalent functionality. But what would you learn from that?? > - do I need to add resistors to the data lines ? You can always stuff them with 0R if you need to. If your design rules allow it, something like a CTS 742C083 series resistor array would be easy to fit in the layout. That package is basically 3 0603 resistors side by side in one 1206 package. Oh yeah, give yourself some pushbuttons to force reprogram, reset, etc. And some LEDs. You'll want something dead simple to do your initial bringup tests. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 121894
On Jul 13, 3:21 am, "John_H" <newsgr...@johnhandwork.com> wrote: > You're seriously overthinking your problem. Please indicate the data speeds > you're encountering to help bound the problems in peoples' minds. > > Consider the lowly HDMI interface. These are ~1.8 Gbit/s signals that go > over flimsy, mass-produced cables with flawless digital performance to get > 1080p signals. I'd second HDMI, certainly worth looking at. I just added HDMI to a Virtex-4 myself. The Virtex-4 doesn't have the TMDS signaling used on the real HDMI interface, but you can use LVDS or whatever over the standard connector. The Type A connector has 4 pairs, and the Type B has 7 pairs per connector. If you are short on space, the HDMI Mini connector has just been released. Dave.Article: 121895
Pasacco wrote: > Could anyone help me with "how to create library and map user > libraries", without using GUI? Easiest way is to compile everything into work and vmap everything to work look in here for details: http://groups.google.com/groups/search?q=treseler+vmap+vlib+workArticle: 121896
Thank you very much for taking the time to have a look and give advice = ! > Normally I would illustrate the regulator (like your LT1764A) with the= > required output cap right next to it, just to clarify which cap is > meeting the requirements of the regulator. Considering the datasheet > dedicates about 3.5 pages to the output cap... I was thinking about 10 uF X7R ceramic. Upon re-reading LT1764A datasheet I think a 100u low ESR / low Z (like = = panasonic Special Polymer) in parallel with a 10u ceramic will be more = suitable ; with a trace of suitable length between the two to add a bit = of = ESR to the ceramic cap so the regulator is happy. > Also, I'd question your 220u on that rail. Take a look at the datashe= et > figure 9 -- it illustrates the performance of the 1.2V regulator with > different output cap networks. Notice the 100u poly cap has a 35mOhm > ESR. If your 220u is a plain old elecrolytic it's probably useless. Thanks for pointing this one out ! This cap was intended for the 3.3V main power supply actually, it's a = low-ESR type (computer motherboard switching regulator style). Correction : the cap now sits on the +3.3V rail. > Offhand I'm not seeing where you get voltage rails like MAC_VDD_PLL, The MAC chip has internal regulators which take 3.3V and generate the = internal VDD_CORE, VDD_PLL, and friends. So, it just wants the help of external decoupling caps. Correction : Note added to schematic. > but if they are other common voltages you should make semi-isolated > versions of them with cap-ferrite bead-cap. If any of the key analog > voltages are your 3.3V (which you get from off-board) I'd strongly > consider making a special, clean 3.3V from some higher rail just for > that. The module will be fed from 3.3V from a supply connector (from testing)= = or from carrier board (via Hirose connector). As the carrier board will have analog circuits I will make separate 3.3= V = supplies for the FPGA module and for the ADC/DACs running from 3.3V. > You might need a multi-voltage reset controller to avoid power sequenc= ing > problems. You'd have to check all the datasheets to see if they're > all tolerant of their rails coming up in the order produced by your > board. Actually, 3.3V will come up, then 2.5V and 1.2V for the FPGA in an = undetermined order. From Xilinx datasheets this is OK. All the other chips (SDRAM, Flash, MAC) only feed from 3.3V so I think = = this will be OK. I have set HSWAP to use pull-up resistors on all pins during config, so= = the /CS, /RD, /WR etc won't be asserted. > Speaking of which, I wouldn't drive your MAC reset with FPGA_DONE. > Use a dedicated IO for it. You can end up making it 'assign MAC_RESET= =3D0' > but if you need it it will be changable. You're right, you never know ;) Done. > Where you split your clk into CLK_OUT and FPGA_CLK, put a series R > on both legs. Done. >> - will my JTAG work ? > > You need some pullups there for when the jtag connector is not hooked > up. I never saw this in any of the schematics I studied... Well, I guess a = = few SMD pullups aren't gonna cost me a lot ! >> - will it smoke ? > > Nah, if you make schematic errors it probably just "won't work", unles= s > your symbols have mistakes, in which case it might smoke. ;-) My head still hurts from rechecking all the chip symbols twice from rhe= = datasheets ;) >> - will my SPI interface & prog_b jumper be enough to rescue a crapped= up >> flash bitstream ? > > Via what? You'll be able to load bitstreams directly via JTAG no matt= er > what the state of the flash. I meant reprogram the flash in system (since it's soldered). But if JTA= G = works, I can always use iMPACT in the worst case. >> - does it suck ? > > It's probably going to cost you more than buying a dev board with > equivalent functionality. But what would you learn from that?? Yeah ; I want to do it and I think it's both interesting and fun. >> - do I need to add resistors to the data lines ? > > You can always stuff them with 0R if you need to. If your design rule= s > allow it, something like a CTS 742C083 series resistor array would be > easy to fit in the layout. That package is basically 3 0603 resistors= > side by side in one 1206 package. I'll check this when I route. Isn't the FPGA drive strength option = suficient ? > Oh yeah, give yourself some pushbuttons to force reprogram, reset, etc= . > And some LEDs. You'll want something dead simple to do your initial > bringup tests. Damn, I have forgotten the Reset Switch ! (too much time using Linux I = = guess). I'll add one. I have a PROG_B jumper (to stop the boot and use JTAG instead). Updated schematics : http://home.peufeu.com/nik/fpga/board_v01/schema2.pdf Thanks a lot. I think it's getting closer !Article: 121897
> But for an individual with a hobby, we are unable to offer this service. > Perhaps someone else will volunteer? Yeah, this is the case ! Thanks anyway. > http://www.xilinx.com/products/boards/files/ml401_2_3_schematics.pdf Interesting ; however for my first FPGA design I guess Spartan-3 is more appropriate than Virtex-4 ;)Article: 121898
This is a generic standard called the Application Binary Interface (ABI) that gcc holds to. You can read about this or find more links to other ABI references at IBM DeveloperWorks. ---Matthew Hicks > Jeff Cunningham wrote: > >> Where is the documentation that shows the details of the calling >> sequence between C and assy functions - I have never been able to >> find that. Stuff like how arguments are put into registers/stack, >> what registers must be preserved, etc.? >> > I think this might be what you're looking for: > > http://the.wall.riscom.net/books/proc/ppc/cwg/a_abi.html#46046 > > (note it's generic PowerPC; it may reference stuff the embedded 405 > doesn't support). > > ken >Article: 121899
On Sat, 14 Jul 2007 14:17:53 -0400, krw <krw@att.bizzzz> wrote: >In article <670i93lg7f1m4jhrcu9l48hjosvoo0jcdv@4ax.com>, >jjlarkin@highNOTlandTHIStechnologyPART.com says... > >> [1] statistical analysis of some FPGA configuration patterns, leading >> up to a fast, small compression/decompression algorithm. We need to >> fit an application program and 6 megabits of Xilinx config stuff into >> a 4 mbit Eprom. >> >I think Xilinx has some stuff on their site regarding compressing >FPGA patters. IIRC, they're quite compressible, easily (RLL or some >such). I'm looking for something that will be fast and easy to decode at fpga config time. I just did some statistical analysis of a bunch of existing Spartan 3 bit streams. If you treat them as bytes, and histogram the byte codes, there's some impressive stats, with code 0x00 of course dominant, then 0xFF, and the next 16 most common codes huge, tapering off pretty hard. That makes sense, since LUT bits are usually zero, so simple codes like 0x01...0x80 and simple 2-bit combos are most common. Block ram is usually 0 in our designs, too. So a fixed dictionary should work pretty well. So it looks like a byte stream would do, with byte codes that say stuff like... 00000000 end of file 001nnnnn make N zero bytes, N=1 to 31 010nnnnn make N 0xFF bytes, ditto 011nnnnn the following N bytes are raw, unencoded stuff 1nnnnnnn look up code N in dictionary, N = 1 to 127 where the dictionary is a list of the most common 96 single bytes followed by the most common 32 byte pairs. Net compression in this case is just about 1:1! Something like that. Now the question is, how much compression will this give? I suppose I'll have to code it and see. I need less than 2:1 now, and that shouldn't be hard. John
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z