Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Jun 19, 3:27 am, Ankit <ankitanand1...@gmail.com> wrote: > Hey Duth.. > > Hi..Thanx for taking time and replying to my query..I > have been trying to run the command you mentioned in your posts but > this what it says.. > > [ankit@localhost Xilinx91i]$ mv $XILINX/gnu/gcc/3.2.3/lin/bin/ld > $XILINX/gnu/gcc/3.2.3/lin/bin/ > mv: cannot stat `/gnu/gcc/3.2.3/lin/bin/ld': No such file or directory > Plus i am a liitle new to linux so pleas dont mind if 1 of my queries > turn out to be stupid.. > I ran these commands in the terminal i am hoping thats where i should > have run them..Or i should have executed these in the TCL shell.. > > Please do help me out of this dilemma as my mentor is admanat that i > run Xilinx on linux.. > > Waiting for your reply.. > > Regards > Ankit Hi Ankit, Please follow the recommendation that Guenter provides, what you are seeing here are just user errors of not setting up the environment correctly. I would also recommend that you try to have a linux specialist assist you out as well, as it may make this process a lot smoother. Additionally you can also try Laurents recommendation of just loading isimwave after simulation. Thanks DuthArticle: 120876
On Jun 17, 9:52 am, John_H <newsgr...@johnhandwork.com> wrote: > fpgabuilder wrote: > > > Thanks John for this insight. Very helpful. But this has raised some > > questions in my mind. Xilinx uses DCMs and they add jitter to the > > clocks. On the other hand Altera uses PLLs and they actually filter > > out the jitter. So in this case it would be good to go with an Altera > > device and drive the clocks to ADC? Or do you see some other problems > > as well. > > > Thanks. > > -sanjay > > The use of a PLL will help your situation. But keep in mind that FPGAs > are ALL concerned with digital signals and are NOT designed as analog > devices! Although the Altera device has significantly less jitter than > the Xilinx DCM output, the output will be contaminated by other FPGA > characteristics. Just having other I/O switching on the same bank is > enough to generate noise in the output clock. > > Your best bet is to NEVER drive the ADC directly from your FPGA > independent of the brand. > > But you can get by without the cleanup PLL (the dedicated, external > analog device) *if* you do an error analysis to determine how much > jitter is tolerable on your ADC clock. If, for instance, you have an > audio stream used for communications (14 bits or fewer at 8 kS/s, > encoded to 8 bits) then your worries are pretty limited. If you have a > 16-bit ADC running at 400 MHz, you're in a world of hurt without extreme > design constraints for a clean sampling timebase. > > You will ALWAYS benefit from having a fixed sampling clock fed to the > ADC from the oscillator rather than from the FPGA. If that clock > topology is impractical, you have to decide how much error or noise > floor is acceptable for your application and guarantee that your logic > device won't degrade the clock beyond your acceptable level. While the > Altera solution *may* be better than the Xilinx solution by 20 dB, I > would suspect the improvement is more on the order of 12-14 dB without > extreme care in the power supply and I/O activity for the Altera > alternative. I don't have evidence to support my numbers, just > expectations in raw performance. > > - John_H Thanks John. This is great stuff. I also found a recent article that confirms your thesis. 5 stars to your post. http://www.embedded-control-europe.com/c_ece_knowhow/25/ECEapr07p41.pdf -sanjayArticle: 120877
Here is my code, and please take a look and give me some advice.
/*
req_phase_y, phase_y_value, phase_y_sign[0] are I2c data received to
start the phase change. After receive req_phase_y, req_phase_y_ack will
be asserted. Wait until req_phase_y is clear, then proceed to state
8'h02. And state 3 and 4 is to send psen and receive psdone. The probem
is psdone never asserted and phase shift never applied.
I feed CLKIN_IN(.clk4phaseChange)
PSCLK_IN(.pixel_clk)
*/
always @ (posedge pixel_clk)
begin
if (rst) begin
y_dynamic <= 8'h00;
PSEN_INy <= 0;
dcm_status <= 0;
phaseDoneCnt <= 0;
ps_cnt <= 0;
end
else begin
if(!req_phase_y)begin req_phase_y_ack <= 0; end
y_dynamic_state <= y_dynamic;
case(y_dynamic)
8'h00:begin
if(req_phase_y)begin
y_dynamic <= 8'h01;
req_phase_y_ack <= 1;
end
else begin
y_dynamic <= 8'h00;
end
PSEN_INy <= 0;
phase_y_cnt <= 0;
ps_cnt <= 0;
end
8'h01:begin
if(req_phase_y==0)begin
y_dynamic <= 8'h02;
end
else begin
y_dynamic <= 8'h01;
end
end
8'h02:begin
PSEN_INy <= 0;
if(phase_y_cnt <= phase_y_value)begin
PSINCDEC_INy <= phase_y_sign[0];
phase_y_cnt <= phase_y_cnt + 1;
y_dynamic <= 8'h03;
end
else begin
phase_y_cnt <= 0;
y_dynamic <= 8'h00;
dcm_status <= dcm_status + 1;
end
end
8'h03:begin
PSEN_INy <= 1;
y_dynamic <= 8'h04;
end
8'h04:begin
PSEN_INy <= 0;
if(PSDONE_OUTy)begin
y_dynamic <= 8'h02;
end
else begin
if(ps_cnt < 500)begin
ps_cnt <= ps_cnt + 1;
y_dynamic <= 8'h04;
end
else begin y_dynamic <= 8'h00; end
end
end
default:begin end
endcase
end
end
Article: 120878On 19 jun, 14:46, Antti <Antti.Luk...@googlemail.com> wrote: > On 19 Jun., 14:19, Pablo <pbantu...@gmail.com> wrote: > > > If I download ddr_sdr core from Opencore, how could I use it with > > PowerPC or Microblaze to access memory with C code. Is it enough to > > load this core in c:\EDK\hw\XilinxProcessorIPLib\pcores? But I need to > > create mpd and pao files. > > > Must I implement C functions to access to it or it is enough to create > > a pointer to the memory direction? > > there are things you can do, and thing you should not. > "using opencores DDR with EDK" is something you should not do. > > Antti That core is an example about what I want to do. I have a ddr core for a non Xilinx Board so I must use this core, but I want to do a PowerPC model and the unique method I know is about using Xilinx Platform Studio. I have to use C code so I need PowerPC and the interface between C code and the core. I hope this could respond to your advice. Regards PabloArticle: 120879
"Vince" <claesvincent@gmail.com> wrote in message news:1182264292.465496.281830@e9g2000prf.googlegroups.com... > Hi all, > > > just for curiousity anyone knows if Actel is working on some tools to > include SystemC synthesis in the future for their Libero IDE? I would be surprised if they did unless of course they team up with say Celoxica or some new synthesis company, there are others like Catapult/Forte/Bluespec but they are probably outside of the average Actel designer EDA budget :-) Hans www.ht-lab.com >This > would be a great advantage for some of their developers since most of > the are working on System Level at the moment. > Kind regards, > Vince > > http://mobile.skynetblogs.be >Article: 120880
"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:5do1g3F34iqk0U1@mid.individual.net... > Ankit wrote: > >> A few days back I installed xilinx ISE webpack 91i on fedora core 6 >> everything worked out fine but i have not been able to simulate the >> testbench using the simulator provided by xilinx..whenever i double >> click on simulate behavioral model nothing happens..guys do help me >> out i am in a fix.. > > Two choices: > 1. Load the windows version of ISE > 2. Buy a modelsim SE floating license. 3. Complain to Mentor for penalizing Linux users! yes I know there is Modelsim LE but that is just ^$&%£") Verilog only :-( Hans www.ht-lab.com > > -- Mike TreselerArticle: 120881
Does anyone if "//synthesis translate_off" in Xilinx is also honored by ASIC synthesis tool (Design compiler) ? ThanksArticle: 120882
> > So far we have found out that we would need to use the light weight IP > (lwIP) library in Socket API mode, but we are totally lost in terms of > how to configure the project in EDK properly to allow such thing. > Should we use the "standalone" OS or "xilkernel"? And how do we If you want sockets, you need to use xilkernel. If you can use the RAW API, then use the standalone BSP. > configure the linker script for the software project so that we can > utilize the 512MB RAM correctly? Create a BSB design for the project and take a look at the linker script used for TestApp_Peripheral. -SivaArticle: 120883
Hi Laurent
I think it would be really great if you could tell the exact bash
script because i would not mind that too..My aim here is to run xilinx
on linux it does not matter how it is done..
@ Duth i will try that also let us see what happens...
Regards
Ankit
Article: 120884On 19 jun, 18:26, "HT-Lab" <han...@ht-lab.com> wrote: > "Vince" <claesvinc...@gmail.com> wrote in message > > news:1182264292.465496.281830@e9g2000prf.googlegroups.com... > > > Hi all, > > > just for curiousity anyone knows if Actel is working on some tools to > > include SystemC synthesis in the future for their Libero IDE? > > I would be surprised if they did unless of course they team up with say > Celoxica or some new synthesis company, there are others like > Catapult/Forte/Bluespec but they are probably outside of the average Actel > designer EDA budget :-) > > Hanswww.ht-lab.com > > > Fully correct but maybe they can fix some arrangment where they will pay the license for their users like the ModelSim Actel Edition etc. I am happy they do things like this (they want to sell silicon not software); by this I can experiment with it in my free time :-)Article: 120885
On Jun 18, 11:16 pm, "Lasse Eriksson" <> wrote: > Hi gseegmiller, > > Do you have an uart16550 or do you use the opb_uartlite? > > If you are using the uartlite the you have to change the cmd line for the kernel. > > console=ttys0,9600 is for the uart16550. > > think it should read this for the uartlite. > > console=ttyl0,9600 > > best regards Lasse Hello, I'm using the uart16550. I've also used the uartlite with the same results. Thank you for responseding! GladeArticle: 120886
I have implemented a base builder system for the Spartan3e starter kit where i have a TestApp_memory.c which is downloaded in blockram and works fine. Then i have another program also generated by the base system builder, TestAppPeripheral.c which i download to the extern memory with XMD which downloads fine and execute with con address. But when it tests interrupts in dosent catch any interrupts, so i wanted to debug the program to see if i could locate the problem (there is definitely some weird beheaviour since the interrupts sometimes work !!) But anyway, i wanted to debug the program using the debugger, i connected fine and started to debug, i placed a breakpoint at the start of the interrupt test, and i started debuggin. Now comes the weird beheaviour, the programtracer jumps back and forward and sometimes skips instructions. It evens jumps into a if statement which it cannot go into according to the data. So anyone have any ideer what is going on ? Maybe the base system builder code is rubish? Anyone have had trouble using interrupts and XMD together ?Article: 120887
On Jun 19, 4:12 am, rbmm...@gmail.com wrote: > Hi, > I have designed a IP core, how can i add my IP to EDK? > Anyone who can help me? If you are attaching to the OPB, PLB, or FSL, you can use the Create/ Import Peripheral Wizard to create a skeleton for you. I thing there are some tutorials out there that describe using the IPIF. If you prefer not to use the IPIF, you are using another bus (custom, point-to-point, DCR, or LMB), or you just want to do this manually, you can follow the conventions used by other IP cores (check under EDK/ hw). You need to follow a certain folder structure and have correct MPD (Microprocessor Peripheral Description) and PAO (Peripheral Analyze Order) files. Use existing IP core MPD and PAO files as a reference along with the Platform Specification Format Reference Manual (psf_rm.pdf). Once you have these finished, you just need to put your IP core in a user repository and it will show up under EDK (assuming EDK was closed when you were doing this, or you manually refreshed the user IP cores through EDK).Article: 120888
Hello, Why does Xilinx MIG controller support DDR dimm at only 165 MHz in Virtex-4 ? (175MHz in -12). I remember seeing a 200 MHz reference designs for DDR memory in a V2Pro! Quoting from the white paper "Memory Interfaces Made Easy with Xilinx FPGAs and the Memory Interface Generator": "For high-performance applications, pushing the limits of the memory interface bandwidth like 533 and 667 Mb/s per pin DDR2 SDRAMs, Xilinx offers the Virtex=E2=84=A2-4 and Virtex-5 FPGAs, which are capable of meeting the highest bandwidth requirements of most systems today." 533? That's like 266 MHz. 200 MHz should be easy for MIG then. 165 MHz is a far cry from the marketed 266 MHz. AR23862 answers part of this question (something about idelay jitter). Still, I feel that the MIG design should be able to extract more performance from the V4 fabric. Side question, why can MIG acheive 220 MHz with DDR2? That's like 33% faster. Thanks. PatrickArticle: 120889
I want to put the PPC running linux in my virtex-4 to sleep to save power. Apparently, the official software suspend mechanism isn't supported/present in our kernel but the standard linux tree does have an include/asm-ppc/suspend.h file. Unfortnately, it's basically blank. Can't believe I'm the first guy to try to save and restore the state of the ppc405 in a virtex chip? Any pointers would be appreciated. Thanks, ClarkArticle: 120890
That core is not an example of what you want to do. It provides a simple interface for FPGA logic to interface with SDRAM. It does not provide an interface to the PLB or OPB, so you would not be able to connect it up to the Power PC without creating another IP core to act as an interface layer. If you are using EDK, I'm assuming you have a board with a Xilinx part on it. If not, why are you using EDK? I don't quite understand how having a DDR core for a non-Xilinx board affects anything. EDK comes with DDR cores that connect directly to the PLB or OPB. This is what you need. Based upon your post, I'm going to assume that you have a non Xilinx board with a Virtex2 or 4 on it. You have an example with this board that utilizes the Opencores DDR controller, but it uses an ISE project flow and does not utilize a PPC or Microblaze. Is this correct? If so, you need to get or create an XBD file (Xilinx Board Definition) that essentially defines the pinout for the FPGA on your board. Using an existing Xilinx board example will not work unless your board has the same pinout for the FPGA (unlikely). Once you have a good XBD, you can create a project that includes a PPC, a DDR memory controller, and other peripherals. Your best bet is probably to adapt one of the existing reference designs to your board. On Jun 19, 12:26 pm, Pablo <pbantu...@gmail.com> wrote: > On 19 jun, 14:46, Antti <Antti.Luk...@googlemail.com> wrote: > > > On 19 Jun., 14:19, Pablo <pbantu...@gmail.com> wrote: > > > > If I download ddr_sdr core from Opencore, how could I use it with > > > PowerPC or Microblaze to access memory with C code. Is it enough to > > > load this core in c:\EDK\hw\XilinxProcessorIPLib\pcores? But I need to > > > create mpd and pao files. > > > > Must I implement C functions to access to it or it is enough to create > > > a pointer to the memory direction? > > > there are things you can do, and thing you should not. > > "using opencores DDR with EDK" is something you should not do. > > > Antti > > That core is an example about what I want to do. I have a ddr core for > a non Xilinx Board so I must use this core, but I want to do a PowerPC > model and the unique method I know is about using Xilinx Platform > Studio. I have to use C code so I need PowerPC and the interface > between C code and the core. > > I hope this could respond to your advice. > > Regards > > PabloArticle: 120891
Dear
I want to synthesize "opb_arbiter" in ISE.
What I did was
(1) Locate "opb_arbiter_v02_e" and "proc_utils_v1_00_a" (located in
EDK directory)
(2) Set up parameter : number of master = 4 (default)
(3) Compile top module "opb_arbiter".
However an error occurs, as indicated in the source codes below.
/opb_arbiter_v1_02_e/hdl/vhdl/opb_bus_arbiter/onehot2encoded.vhd
Error : or_bits is not an entity name
Let us know how to synthesize, if anyone has this experience.
Thank you in advance.
-----------------------------------------------------------------------------------------------------
-- /opb_arbiter_v1_02_e/hdl/vhdl/opb_bus_arbiter/onehot2encoded.vhd
-----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- OPB_ARB_PKG includes necessary constants and functions
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library opb_arbiter_v1_02_e;
use opb_arbiter_v1_02_e.opb_arb_pkg.all;
library proc_common_v2_00_a;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_1HOT_BUS_SIZE -- number of bits in the 1-hot bus
--
-- Definition of Ports:
-- Bus_1hot -- input 1-hot bus
-- Bus_enc -- output encoded bus
--
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity onehot2encoded is
generic (
C_1HOT_BUS_SIZE : integer := 8
);
port (
Bus_1hot : in std_logic_vector(0 to
C_1HOT_BUS_SIZE-1);
Bus_enc : out std_logic_vector(0 to
log2(C_1HOT_BUS_SIZE)-1)
);
end onehot2encoded;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of onehot2encoded is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- encoder logic requires that the 1hot bus be padded to next power of
2
constant PAD_1HOT_BUS_SIZE : integer := pad_power2(C_1HOT_BUS_SIZE);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pad_1hot_bus : std_logic_vector(0 to PAD_1HOT_BUS_SIZE-1) := (others => '0');
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- OR_BITS is used to determine if segments of the 1-hot bus are '1'
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Padded bus generation
-------------------------------------------------------------------------------
pad_1hot_bus(0 to C_1HOT_BUS_SIZE-1) <= Bus_1hot;
-------------------------------------------------------------------------------
-- Encoded Bus generation
-------------------------------------------------------------------------------
-- Note this logic uses the padded version of the 1hot bus to insure
that
-- the calculations are on a constant which is a power of 2
ENC_BUS_GEN: for i in 0 to log2(PAD_1HOT_BUS_SIZE)-1 generate
signal temp_or : std_logic_vector(0 to 2**i) := (others => '0');
begin
OR_GENERATE: for j in 1 to 2**i generate
---------------------------------------------------------------------------------
---- Here error occurs :
---- Error : or_bits is not an entity name
----------------------------------------------------------------------------------
BUS_OR: entity proc_common_v2_00_a.or_bits
generic map ( C_NUM_BITS => PAD_1HOT_BUS_SIZE/2**(i+1),
C_START_BIT => PAD_1HOT_BUS_SIZE/2**(i+1)
+ (j-1)*PAD_1HOT_BUS_SIZE/
2**i,
C_BUS_SIZE => PAD_1HOT_BUS_SIZE
)
port map (
In_Bus => pad_1hot_bus,
Sig => temp_or(j-1),
Or_out => temp_or(j)
);
end generate OR_GENERATE;
Bus_enc(i) <= temp_or(2**i);
end generate ENC_BUS_GEN;
end implementation;
Article: 120892On Jun 18, 9:27 pm, Maverick <> wrote: > I have a Xilinx design that uses mainly verilog RTL and some .xco >file for coregen FIFOs and such. I am using vcs compiler from >synopsys. This compiler does not recgonize the xco files. Is there any >way I can convert .xco file into verilog file using Xilinx coregen? > > I do not know why this shareware design does not provide the verilog >file for coregen fifo and instead it has the .xco file. Is there any >advantage in doing so? > > It will be great if I can convert the .xco file into .v for vcs >verilog simulation. vcs compiler is able to compile the xilinx >primitves .v files provided by Xilinx. > > Thanks for your help. > > Maverick You can run coregen in batch mode to generate simulations files from .xco files: The table below lists the options to the coregen command. Option Description -b <command_file_name> Invokes the CORE Generator=99 in batch mode and executes the commands in the specified command file during the batch mode run. The command_file_name argument specifies the path to the command file to be executed. XCO files are commonly specified as the argument to the -b option, but you can specify any file containing valid CORE Generator commands. Cheers, Jim http://home.comcast.net/~jimwu88/tools/Article: 120893
Thanks. I changed the modelsim.ini in the ModelTech directory but not in the location where I was simulating from. I suppose you have to do it there. It works now.Article: 120894
Honestly, I thought you had a state machine that contolled the dynamic phase shifting only and that was the problem. This appears to be a design that has the dyanmic phase shift control inside of it and there could be multiple sources of error. Dumb question, but have you simulated this? That is where I would start. This is too complicated to look at right now. I thought there was going to be some quick 'aha' code problem.Article: 120895
We are having some tests failing under certain clock signals. The clock signal is generated in an external device with different drive strengths. The external clock is used to clock some Virtex2P internal FFs which outputs goes to the DUT. We tried different drive strength for the clock such as: 1mA, 2mA, 3mA, 4mA,and 6mA. The test only fails with 2mA drive strength. Analyzing the captured waveforms, we found that there are some ringing (non-monotonicity) in the 2mA clock at around 1V and 2V. Since we are using LVCMOS33. From the V2P data sheet, on page 76, it's stated that for LVCMOS33 VIL min = -0.2 VIL max = 0.8 VIH min = 2.0 VIH max = 3.45 Since the clock signal has a 'draw-back' (ringing) at ~1.0 and at ~2.0V, is that what actually cause the problem with the clock? On the other hand, I read on the xilinx's Answer Database, answer # 11308, that there is a transition point at Vcc/2 with a hyteresis of ~100mV and this apliable to both data and clock inputs. I was looking for more detailed information on the hysteresis (in X FPGAs) , but I could not find anything else. So, my first question: is Vcc/2 the 'real transition' point for the clock? for 3.3Vcc that point is at 1.65V. In my case the clock is clean and monotonic between 1.1 and 1.9. So, why should I have problem based on the Vcc/2 transition point? However, using the values from the data sheet, VIL min = -0.2 VIL max = 0.8 VIH min = 2.0 VIH max = 3.45 I see that the 'draw-back' happens very close to the borders, close to Vilmax and Vihmin, and could cause some problems. I do understand that the non-monotonic clock can cause problem, but at this moment there no much we can do with the board. I'd also like to find any doc on Xilinx website related to the integrity of the clock signal. If you can point to me to some document that could clarify the behave of the FFs with noisy clocks, I'd really appreciate it. Thanks, Cris PS: the rise time for the 2mA is ~22nsArticle: 120896
<csisterna@hotmail.com> wrote in message news:1182286871.788231.92360@c77g2000hse.googlegroups.com... > > I do understand that the non-monotonic clock can cause problem, but > at this moment there no much we can do with the board. I'd also like > to find any doc on Xilinx website related to the integrity of the > clock signal. If you can point to me to some document that could > clarify the behave of the FFs with noisy clocks, I'd really appreciate > it. > Hi Cris, Your problem is probably the falling edge of the clock being seen by your cct as a rising edge... > > Thanks, > > Cris > PS: the rise time for the 2mA is ~22ns > ...because you have a clock that is very slow. Really, very slow. You need to fix this, maybe with a Schmitt trigger buffer. HTH, Syms.Article: 120897
Comments in the text.
<SNIP>
> >>
> >>
> >>>-- decoding signals
> >>>p_signal1 <= '1' when addr = x"123" else
> >>> '0';
> >>>p_signal2 <= '1' when addr = x"456" else
> >>> '0';
> >>>
> >>>
> >>>-- writing process
> >>>
> >>>process (clk, nrst)
> >>>begin
> >>> if nrst = '0' then
> >>> signal1 <= '0';
> >>> signal2 <= '0';
> >>> elsif rising_edge (clk) then
> >>> if wr = '1' then
> >>> if p_signal1 = '1' then
> >>> signal1 <= data;
> >>> elsif p_signal2 = '1' then
> >>> signal2 <= data;
> >>> ...
> >>>end process;
> >>
> >>So it happens that writing to addr = x"123" it will change signal2 as
> >>well...how can it be possible???
> >>
> >>I did prefer to have "p_signals" and not use directly the "addr" in the
> >>process just because in the very beginning I thought about latching the
> >>"p_signals" to have them stable, but then I realized it wouldn't have
> >>fit in the logic (I have already an occupancy of 84% and I have more
> >>than 300 addresses to decode).
> >>Do you have any explanation of this behaviour?
> >
> >
> > Hi Alessandro,
> >
> > What do you mean with postsynthesis and postlayout? Gatelevel with and
> > without timing?
>
> Well, the postlayout is gatelevel with timing of logic elements but not
> the routes (I think there's just an estimation of which will be the
> route and timing is computing based on this estimation). Postlayout is
> considering the actual routes after place&route process and all delays
> are taken into account. Moreover I had to implement a simulation
> considering the INDUSTRIAL ranges in temperature and voltage to take
> into account timing changing according to these two parameters.
> >
> > Also, what did you do with your write signal? Normally, you wouldn't
have to
> > delay it in a synchronous environment.
> >
> Unfortunately the p_signals are really many, in the order of 300 and,
> for the Actel chip I'm using, there's a long delay introduced in the
> decode chain of all this combinatorial logic. That's why, to overcome
> this, I needed to add some latency in the write signal which will allow
> me to have the data stable and the p_signal stable when the write signal
> arrives.
This is wrong. Normally you specify your I/O timing and clock constraints
and the synthesis tool should tell you if it met those or not. Combinatorial
delay will be optimized away anyway.
> > Your code seems ok, even though I would replace the elsif p_signal2 by
> > regular ifs: the reason is that you're now describing a priority decoded
> > block, whik this is unnescessary.
> >
> I agree with you, even if I thought that the if elsif structure would
> have been much simpler to write, otherwise I have to implement a process
> for any register, turning out with a less readable code. But I will try
> with a case when structure and try to see if there are any differences
> in the implementation.
>
Currently, each of the "p_signal<i> <=" statements creates a process.
Combining these in a single process would require a process with a case
statement and addr in it's sensitivity list. You would then have to assign
every p_signal<i> to '0' by default or you would end up with latches. But
this wasn't the point I was making. The elsif construct in your clocked
process creates superfluous priority logic. You're telling the compiler the
following:
if p_signal1, then ...
else (if not p_signal1) and p_signal2, then ...
else (if not p_signal1 or p_signal2) and p_signal3, then ...
This will create a very large expression for the very last action. If the
compiler is smart enough, it may see that the p_signal<i> signals are
mutually exclusive and remove this logic. Things would go smoother if you
put:
if p_signal1, then ...
if p_signal2, then ...
if p_signal3, then ...
> By the way I did registered the p_signal, fearing that the synthesizer
> would have put the write signal at the very beginning of the chain
> instead at the end, but the simulation didn't work either.
If timing is an issue, you will have to register the addr and wr signals an
equal amount. A simple trick would be to replicate addr a few times and
decode a reduced number of addresses from each copy (use boundaries of 2^n).
Some tools (Synplify at least) will merge these registers back to one unless
you add a syn_keep attribute (or was it keep?). If your routing resources
are still widely available, you could register partially decoded p_sigs:
p_sig2, p_sig1, p_sig0 : STD_LOGIC_VECTOR(15 downto 0)
if rising_edge
p_sig2 <= decode16(addr(11 downto 8))
p_sig1 <= decode16(addr( 7 downto 4))
p_sig0 <= decode16(addr( 3 downto 0))
wr_dec <= wr
if (wr_dec = '1')
if (p_sig2(0) and p_sig1(0) and p_sig0(0) = '1') then ...
if (p_sig2(0) and p_sig1(0) and p_sig0(1) = '1') then ...
Regards,
Alvin.
Article: 120898Chris, -snip- > So, my first question: is Vcc/2 the 'real transition' point for the > clock? Vcc/2 is the design center by simulation for perfectly "typical" process corners. In reality, this does vary. If the p is stronger, and the n is weaker (for example) the transition point is no longer Vcc/2. Generally, CMOS varies from ~33%, to ~66%. The thick oxide devices are not so variable as the mid, or thin oxide devices, but 33 to 66% is a good guideline. If you want to switch at a precise level, then you should be using a standard that uses the Vref input to the input comparatot. If you can point to me to some document that could > clarify the behave of the FFs with noisy clocks, I'd really appreciate > it. http://www.xilinx.com/products/design_resources/signal_integrity/ http://www.xilinx.com/products/design_resources/signal_integrity/resource/si_pcb.htm Your problem is incredibly basic, and is not uniquely a "clock" problem. It is just that having this problem on a clock signal can cause multiple problems. You need to fix the signal integrity, as changing the threshold may fix this one board, and may not be what works for another board. The fact that changing the drive strength does little to affect the shape of the received signal implies that there is no match from the source to the line, to the load that will work. Often this is due to the line itself having a discontinuous impedance (it may have multiple drop off points, which means that series termination can never work -- parallel termination will only work in such cases). You may wish to enable the parallel split DCI termination option in the IOB. You will need to connect the reference resistor pins to resistors to use this feature. For V4: http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex4/capabilities/selectio.htm Also exists for V2, V2P, and V5. AustinArticle: 120899
The EDK will search the libraries you list in the pao. I do all my cores in verilog and don't ever have problems. I don't understand what you mean by the EDK going 'defautly' to the vhdl folder. Is simpl_tx the fifo? If it is, put the verilog file (generated by core gen) in the hdl/verilog folder and include it in the pao. Then put the ngc in the netlist folder and include it in the bbd file. Somehwere/somehow the EDK thinks it is searching for a VHDL file called simpl_tx...and I really don't think that is in a script anywhere....at least one that isn't generated via files you have access to in the core. Post the pao (at least to make me shut up about that). I can't think of why your core is behaving badly. But maybe if it was in front of me I'd understand better.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z