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Messages from 12325

Article: 12325
Subject: Re: FIR Filter Design
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Thu, 08 Oct 1998 21:46:00 -0400
Links: << >>  << T >>  << A >>
Actually, the Viterbi algorithm is a very good demonstration of the power of an
FPGA.  Each level in the algorithm requires six adds or subtracts to be performed
(four to produce the four possible path metrics, and two to compare the metrics
from each node.  The compare result's MSB operates a mux to select the survivor for
each path.  In a DSP processor, each of these has to be done independently and the
results stored.  In an FPGA, all of these operations can be done in parallel using
separate adders and muxes.  Note that registers in the FPGA can be used for storage
too, so there is no need for external memory.  You should have no problem fitting
this in even a considerably smaller FPGA (4020 sized ought to do it).  I think if
you check the Xilinx alliance cores, there may even be a parameterizable viterbi
core available.  Greg Goslin, formerly of Xilinx did a paper that included a
viterbi design a few years ago for designCon (96 I think?)  You can probably find
that paper on Xilinx's web site as well (do a search on viterbi on the xilinx site:
http://www.xilinx.com ).  I think his conclusion was that half of an FPGA (4020?)
replaced an entire 66MHz DSP processor plus some external memory and outperformed
it by a significant margin (x2 or x3) while drawing less power.

Again, if your data rates are low enough, this can be implemented as a bit serial

Kartheepan, Madasamy wrote:

> Thank you for the last two informative emails. I definitely understand the need
> to have a different design philosophy when tackling hardware implementations of
> signal processing functions.A little off topic, I want to bounce this off you.
> I have been thinking of  putting  Viterbi algorithm for finding MLS onto an
> FPGA. Have you come across similar implementations and what is your take on the
> feasibility of putting the algorithm handling 32 states (5 memory elements) on
> a 100K FPGA?. I would appreciate any input from you,
>
> Thank you,
> Kartheepan, M



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 12326
Subject: Re: Synthesis: Exemplar or Synopsys
From: Rickman <spamgoeshere4@yahoo.com>
Date: Thu, 08 Oct 1998 22:08:23 -0400
Links: << >>  << T >>  << A >>
ems@nospam.riverside-machines.com wrote:
> 
> On Wed, 07 Oct 1998 11:31:23 -0700, Derek Palmer <derekp@synopsys.com>
> wrote:
> 
> >Let's make rumor fact!
> >FPGA Express 3.0 will have VHDL 93 support.
> >Available on the Synopsys web site at the end of Oct.
> 
> great news, and nice to see synopsys here. however, the last
> i heard from xilinx was that it would support "some" '93
> features; they weren't specific. can you tell us more? does
> this mean (a) a normal synthesisable subset of '93, or
> (b) limited support of '93? and what about VSS/DC?
> 
> will the new version be shipped with foundation, or will
> it be an (expensive) upgrade?
> 
> evan

I called Xilinx last night and asked your last question. I was told that
version M1.5 includes FPGA Express 2.1.2 I believe and will later have a
patch available to 2.1.3. 

But the main point was that you won't get VHDL '93 support until M2.0
which will not be shipping until early next year. 

So if you are a Foundation user, don't hold your breath. 


-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.
Article: 12327
Subject: Re: Design security again - the Actel solution
From: Rickman <spamgoeshere4@yahoo.com>
Date: Thu, 08 Oct 1998 22:13:25 -0400
Links: << >>  << T >>  << A >>
Steven K. Knapp wrote:
> 
> At these "costs", the weak link is probably the design engineer.  Hiring him
> or her away (or the whole team) at a fraction of the cost would be the easy
> solution. :)
> 
> Also, if the devices are _really_ that secure, Actel should offer a big cash
> prize to "crack" a secured device.  A $250,000 prize should be risk-free for
> Actel according to their arguments.  Imagine the marketing messages they
> could make then.

I don't think they will ever do this. It comes under the heading of "It
is better to remain silent and appear to be a fool than to speak and
remove all doubt". As long as no one cracks it, they can claim this
advantage. But if they offer a prize and someone does crack it... they
have lost a lot more than the $1/4 mil. 


-- 

Rick Collins

redsp@XYusa.net

remove the XY to email me.
Article: 12328
Subject: Re: VHDL'93 in MaxPlus
From: Davor Lukacic <dlukacic@eis.k8.rt.bosch.de>
Date: Fri, 09 Oct 1998 09:46:30 +0200
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------C8C12CB4143F1A30C7089B57
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Ido Kleinman wrote:

> Hi,
> Anyone knows how do I activate VHDL93 compiling ability in MaxPlus2?
>
> I wrote some code with direct component instanciation that would compile
> nice in Aldec, but won't in Maxplus...
>
> MaxPlus specifies many VHDL93 constructs in its help so I guess the VHDL93
> compiling ability exists. (I have the full software, no "unavailable
> features"...)
>
> --
>
>  Ido Kleinman.
>  kleinn@mail.biu.ac.il

  Hi Ido,

You just have to open the compiler window, be sure to have the compiler
window active. Choose menu "Interfaces" ->
and then i'm not so sure, but i think there must be something like
"VHDL-Compiler -Settings"  ....there you find a
switch for VHDL 93 ....

Hope this helps !!!

--------------C8C12CB4143F1A30C7089B57
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begin:          vcard
fn:             Davor Lukacic
n:              Lukacic;Davor
org:            Robert BOSCH GmbH
adr:            Tuebinger Str. 123;;P.O. Box 1342;Reutlingen;;72703;Germany
email;internet: dlukacic@eis.k8.rt.bosch.de
title:          Development of Integrated Circuits
tel;work:       ++49 7121 35 4430
x-mozilla-cpt:  ;0
x-mozilla-html: FALSE
end:            vcard


--------------C8C12CB4143F1A30C7089B57--

Article: 12329
Subject: Re: LCELL delay of Altera 10K's
From: "John Huang" <hungi@tpts4.seed.net.tw>
Date: Fri, 9 Oct 1998 16:25:05 +0800
Links: << >>  << T >>  << A >>
Hi:

What is the best way to make delay in FPGA?

Regards

John Huang

emmanuel jolly ¼¶¼g©ó¤å³¹ <361d1908.103204@news.hol.fr>...
>LCell time depends on Component family and speed grade (10K, 10KA,
>10KE, -4, -3, -2, -1).
>It is not a good design rule to use LCELL to implement delay. Use it
>only if you have no other solution
>
>Regards
>
>On Fri, 9 Oct 1998 01:08:15 +0800, "John Huang"
><hungi@tpts4.seed.net.tw> wrote:
>
>>Hi all:
>>
>>    Does anyone know the delay time of one LCELL,
>>if I implement an VHDL statement
>>
>>  U1: LCELL(CLK1, CLK2);
>>
>>  the CLK2 will be delay how many ns?
>>
>>    John Huang
>>
>>
>
>---
>Pour me contacter enlever "removethis." de mon adresse Email.
>To contact me, remove "removethis." from my Email address.


Article: 12330
Subject: LUXEMBOURG: DEMOCRACY OR POLICE STATE
From: "sotl" <lisa@pt.lu>
Date: Fri, 9 Oct 1998 10:50:14 +0200
Links: << >>  << T >>  << A >>
Sorry i know i am out of topic. This will be the first and once time.Thanks
to all other PC-user for your understandling. Bye and great thanks



LUXEMBOURG: DEMOCRACY OR POLICE STATE

As an italian citizen born in Luxembourg and still married
to a luxembourg woman, I am raising questions to myself
every day. In January this year my wife left our home.The
day after 4 police officers (Gendarmerie Grand-Ducale) entered
in my home and picked up my 4 children (Julie,Mélissa,Andy and
Laurent) in order to bring them to their mother. This was done
without any written protocol, or either without any written
aproval from any court.In South-America and Eastern-Europe
a few years ago some dictatures was the objective of our medias
for these same police activities. I would like to believe that
in Luxembourg we still have democracy order and not same destination.

Regards  Jean


Article: 12331
Subject: Re: clock divider chips
From: msimon@tefbbs.com
Date: Fri, 09 Oct 1998 08:54:14 GMT
Links: << >>  << T >>  << A >>
Have you tried the 74ACT161 - clocks at >100MHz. Synchronous.

Don't know about skew.

Simon
=================================
"Thomas Dölle" <doelle@fb.sony.de> wrote:

>Hi,
>
>I'm looking for high speed (up to 80 MHz input) clock divider chips with
>
>programmable ratio (1/2, 1/4, 1/8). The outputs should be at CLK and
>CLK/X with low skew (100 - 1000ps) and low jitter. The input is driven
>by a external clock source. Does anybody know whether there are chips
>commercially available?
>
>Thomas
>
>
>
>
>
>

Design Your Own MicroProcessor(tm) http://www.tefbbs.com/spacetime/index.htm
Article: 12332
Subject: clock divider chips
From: "Thomas Dölle" <doelle@fb.sony.de>
Date: Fri, 09 Oct 1998 10:04:52 +0100
Links: << >>  << T >>  << A >>
Hi,

I'm looking for high speed (up to 80 MHz input) clock divider chips with

programmable ratio (1/2, 1/4, 1/8). The outputs should be at CLK and
CLK/X with low skew (100 - 1000ps) and low jitter. The input is driven
by a external clock source. Does anybody know whether there are chips
commercially available?

Thomas






Article: 12333
Subject: Re: FPGA core design
From: msimon@tefbbs.com
Date: Fri, 09 Oct 1998 10:16:46 GMT
Links: << >>  << T >>  << A >>
Error in the URL - revised below:

>I have a nifty - I think - tool for designing cores.
>
>Check out:
>


Design Your Own MicroProcessor(tm) http://www.tefbbs.com/spacetime/index.htm
Article: 12334
Subject: Re: VHDL'93 in MaxPlus
From: A.Biniszkiewicz@pz.zgora.pl (Adam Biniszkiewicz)
Date: Fri, 09 Oct 1998 11:40:20 GMT
Links: << >>  << T >>  << A >>
Hi,
Open the Compiler window. 
Go to the "Interfaces" -> "VHDL Netlist Reader Settings" menu. 
Check VHDL 93 and accpet.

Regards,
Adam Biniszkiewicz

--------------------------------------------
Adam Biniszkiewicz
Technical University of Zielona Gora, Poland
e-mail: A.Biniszkiewicz@pz.zgora.pl
--------------------------------------------

On Fri, 9 Oct 1998 01:38:30 +0200, "Ido Kleinman"
<kleinn@mail.biu.ac.il> wrote:

>Hi,
>Anyone knows how do I activate VHDL93 compiling ability in MaxPlus2?
>
>I wrote some code with direct component instanciation that would compile
>nice in Aldec, but won't in Maxplus...
>
>MaxPlus specifies many VHDL93 constructs in its help so I guess the VHDL93
>compiling ability exists. (I have the full software, no "unavailable
>features"...)
>
>--
>
>
> Ido Kleinman.
> kleinn@mail.biu.ac.il
>
>
>
>

Article: 12335
Subject: Re: VHDL'93 in MaxPlus
From: A.Biniszkiewicz@pz.zgora.pl (Adam Biniszkiewicz)
Date: Fri, 09 Oct 1998 11:50:11 GMT
Links: << >>  << T >>  << A >>
Hi,

1. Open the Compiler window.
2. Go to the "Interfaces" - > "VHDL Netlist Reader Settings" menu.
3. Check VHDL 1993 and accept.


Regards,
Adam Biniszkiewicz

--------------------------------------------
Adam Biniszkiewicz
Technical University of Zielona Gora, Poland
e-mail: A.Biniszkiewicz@pz.zgora.pl
--------------------------------------------

Article: 12336
Subject: Re: Xilinx F1.5/FPGA Express wackiness
From: gd@nospam.heliontech.com (Graeme Durant)
Date: Fri, 09 Oct 1998 12:16:14 GMT
Links: << >>  << T >>  << A >>
On Thu, 8 Oct 1998 12:11:10 -0700, "Andy Peters"
<apeters@noao.edu.NOSPAM> wrote:

>
>1) Supposedly there's a way to keep revs of source code with implementation
>revs but I can't figure out how to do it.
>

We received our copy of Foundation 1.5 this very morning, and quite
out-of-character had a look through the bright yellow 'Read Me First'
leaflet inside whilst consuming my second cup of tea of the day.

Under Known Issues it says that the revision control mechanism only
handles implementation data, and that you have to manually handle 
your source code/netlists if you want to keep them.

I guess this answers your question 1.....it's a crying shame they
didn't include source control in the Project Manager, along with
implementation revision management.  Unless you are scrupulously
careful with versions and revisions etc., you can come very unstuck
later, as I'm sure most of us have discovered at one time or another!

Sorry, no answers yet to your other points....I need to spend some
time with it myself first!

Graeme Durant
HELION Technology Limited
Programmable Logic Design Specialists
The Granary, Home End, Fulbourn, Cambridge CB1 5BS, UK.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
mailto:gd@heliontech.com
http://www.heliontech.com

XILINX CERTIFIED GOLD LEVEL DESIGN CONSULTANT
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Article: 12337
Subject: Re: VHDL'93 in MaxPlus
From: Dave D'Aurelio <daurelio@capture.kodak.com>
Date: Fri, 09 Oct 1998 08:34:30 -0400
Links: << >>  << T >>  << A >>
To turn on VHDL93 support in MaxPlus2, do the following:
1) Bring up the compiler window
2) Go to the Interfaces-VHDL Netlist Reader menu pulldown
3) In the dialog box, click the VHDL93 button and click OK

That's all there is to it !


Ido Kleinman wrote:

> Hi,
> Anyone knows how do I activate VHDL93 compiling ability in MaxPlus2?
>
> I wrote some code with direct component instanciation that would compile
> nice in Aldec, but won't in Maxplus...
>
> MaxPlus specifies many VHDL93 constructs in its help so I guess the VHDL93
> compiling ability exists. (I have the full software, no "unavailable
> features"...)
>
> --
>
>  Ido Kleinman.
>  kleinn@mail.biu.ac.il



Article: 12338
Subject: What is an embedded IrDA (infrared) software protocol stack?
From: Rick
Date: Fri, 09 Oct 1998 15:04:07 GMT
Links: << >>  << T >>  << A >>
Anyone interested in learning about what
a truly embedded IrDA infrared 
software protocol stack is, should check out:

http://www.embednet.com

This stack is: 
. modular and written in "clean" C.
. small (<10K bytes) 
. efficient ( Zero copy buffer management )
. able to support speeds from 9.6Kbps to 4Mbps
. RTOS ready
. simple to port
. well tested.
. supported on all popular platforms: MIPS, ARM, Motorola, Intel,
Hitachi SH, etc ... 
. (not to forget) inexpensive (<$6k)


Article: 12339
Subject: FCCM 99?
From: christof@goya.WPI.EDU (Christof Paar)
Date: 9 Oct 1998 15:17:30 GMT
Links: << >>  << T >>  << A >>
Is the Call for Papers for FCCM 99 already out? If so, where can I find it? 

Thanks,

Christof

-- 
*************************************************************************
Christof Paar                   http://ee.wpi.edu/People/faculty/cxp.html
Assistant Professor             email:  christof@ece.wpi.edu
Cryptography Group              phone:  (508) 831 5061
ECE Department, WPI             fax:    (508) 831 5491
100 Institute Road 
Worcester, MA 01609, USA 
*************************************************************************
Article: 12340
Subject: Re: Software tool
From: "Son P. Huynh" <sphuynh@micron.net>
Date: Fri, 9 Oct 1998 09:37:43 -0600
Links: << >>  << T >>  << A >>
Hello,

I'm using Active-VHDL now and I like it a lot.  Very nice GUI and
loaded with features.  You can always request a CD or have your
computer running overnight...  It worth the download.

Son Huynh

Ido Kleinman wrote in message <6vjffo$nir$1@news.inter.net.il>...
>Dear all,
>
>I am looking for a good VHDL development (compiling, simulation,
gate-level
>sim/FSM support, Testbench generator) software tool. I need it to
have a
>comfortable interface to maxplus2 for exporting compiled designs for
>synthesis in Altera's devices.
>I've been looking around lately and I've evaluated Aldec's
"Active-VHDL" and
>quite happy with it, but I have a slow internet connection,
therefore,
>before I start downloading tens of megabytes again, I would like to
know if
>there are any other compact software tools worth looking at...?
>
>Anyone got any experience with Aldec's tool?
>Are the big ones (Synopsys, Examplar..) worth the investment?
>
>
>--
>
>
> Ido Kleinman.
> kleinn@mail.biu.ac.il
>
>
>
>

Article: 12341
Subject: Re: Xilinx F1.5/FPGA Express wackiness
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Fri, 9 Oct 1998 09:17:43 -0700
Links: << >>  << T >>  << A >>
I got a great note yesterday from David Dye of Xilinx answering my comments.

Graeme Durant wrote in message <361df931.81804368@news.force9.net>...

re: source code revs w/implementation revs.

>I guess this answers your question 1.....it's a crying shame they
>didn't include source control in the Project Manager, along with
>implementation revision management.  Unless you are scrupulously
>careful with versions and revisions etc., you can come very unstuck
>later, as I'm sure most of us have discovered at one time or another!


David says that it's going to be in the "next full release."

>Sorry, no answers yet to your other points....I need to spend some
>time with it myself first!

They're also working w/Synopsys to reduce the amount of timing constraints
exported to the .XNF file, and also trying to have one constraints editor.
It turns out that the constraints editor needs information that's generated
by the Translator, so you have to do a translate, then kill the
implementation, the import the necessary files into the constraints editor.

The constraints editor is not included in Project Manager because it was
decided late in the game to add it.  Hey, as long as it's there, I'm
happy...

There's a patch to the constraints editor up on the Xilinx Web site.

-a
--
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
520-318-8191
apeters@noao.edu



Article: 12342
Subject: Re: FCCM 99?
From: hauck@ece.nwu.edu (Scott Hauck)
Date: Fri, 09 Oct 1998 16:18:23 GMT
Links: << >>  << T >>  << A >>
The Call for Papers for FCCM 99 is not out as far as I know (and the program 
committee usually gets it first).  It usually comes out pretty late, and the 
due date is normally in the 1st week of January.

Scott

In article <6vl9ea$3fp$2@bigboote.WPI.EDU>, christof@goya.WPI.EDU (Christof 
Paar) wrote:
>Is the Call for Papers for FCCM 99 already out? If so, where can I find it? 
>
>Thanks,
>
>Christof
>
Article: 12343
Subject: Re: Synthesis: Exemplar or Synopsys
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Fri, 9 Oct 1998 09:20:10 -0700
Links: << >>  << T >>  << A >>
Rickman wrote in message <361D7017.200058C5@yahoo.com>...

>I called Xilinx last night and asked your last question. I was told that
>version M1.5 includes FPGA Express 2.1.2 I believe and will later have a
>patch available to 2.1.3.
>
>But the main point was that you won't get VHDL '93 support until M2.0
>which will not be shipping until early next year.

Won't that be when VHDL 2000 is out?

Oh, wait, that's Office 2000.

Silly me.

--
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
520-318-8191
apeters@noao.edu



Article: 12344
Subject: Re: FCCM 99?
From: Martin Rosner <mcr@philabs.research.philips.com>
Date: Fri, 09 Oct 1998 12:28:52 -0400
Links: << >>  << T >>  << A >>
Christof Paar wrote:

> Is the Call for Papers for FCCM 99 already out? If so, where can I find it?
>
> Thanks,
>
> Christof
>
> --
> *************************************************************************
> Christof Paar                   http://ee.wpi.edu/People/faculty/cxp.html
> Assistant Professor             email:  christof@ece.wpi.edu
> Cryptography Group              phone:  (508) 831 5061
> ECE Department, WPI             fax:    (508) 831 5491
> 100 Institute Road
> Worcester, MA 01609, USA
> *************************************************************************

  I don't think it's out yet. The fccm.org page (i have a link to
it from my page [lab staff]) is not updated yet.

regards
-martin

Article: 12345
Subject: Altera embedded FIFO RAM (using EABs)
From: "SFCFM Volunteer" <stahr@andix.com>
Date: 9 Oct 1998 11:37:05 -0500
Links: << >>  << T >>  << A >>
How can I implement this very simple dual port RAM using genmem
to embed it on a Flex10K device. Altera memory type "csfifo" is
a "cycle-shared" FIFO (what is that?)


***************************************************************
module fram2_8 (
   clk,
   write_n,   // Write enable
   write_ptr, // Write Address
   read_ptr,  // Read Address
   data_in,   // Write Data
   data_out   // Read Data
.
.
.

always @(read_ptr or reg0 or reg1 or reg2 or reg3 or reg4 or reg5 or
             reg6 or reg7)
       casez (read_ptr)
          3'b000 : data_out = reg0;
          3'b001 : data_out = reg1;
          3'b010 : data_out = reg2;
          3'b011 : data_out = reg3;
          3'b100 : data_out = reg4;
          3'b101 : data_out = reg5;
          3'b110 : data_out = reg6;
          3'b111 : data_out = reg7;
       endcase

    // Update RAM on a write pulse
    always @(posedge clk)
       if( !write_n)
       casez (write_ptr)
          3'b000   : reg0  <= data_in;
          3'b001   : reg1  <= data_in;
          3'b010   : reg2  <= data_in;
          3'b011   : reg3  <= data_in;
          3'b100   : reg4  <= data_in;
          3'b101   : reg5  <= data_in;
          3'b110   : reg6  <= data_in;
          3'b111   : reg7  <= data_in;
       endcase

endmodule
*********************************************************************



Article: 12346
Subject: Re: clock divider chips
From: "Sri Saripalle" <sri@spiketech.com>
Date: 9 Oct 1998 16:54:12 GMT
Links: << >>  << T >>  << A >>
Hi,

I have not heard of any but we had done one way back using a
microcontroller. Do let me know if you ultimately land up looking for guys
who can program a microcontroller.

My company offers such services, we shall identify an appropriate
microcontroller, program it and give you some prototypes. If they work you
can tell us how many you need. We shall get them for you. Visit our
web-site at http://www.spiketech.com

- Sri
(sri@spiketech.com)

Thomas Dölle <doelle@fb.sony.de> wrote in article
<361DD1B3.4EFC8575@fb.sony.de>...
> Hi,
> 
> I'm looking for high speed (up to 80 MHz input) clock divider chips with
> 
> programmable ratio (1/2, 1/4, 1/8). The outputs should be at CLK and
> CLK/X with low skew (100 - 1000ps) and low jitter. The input is driven
> by a external clock source. Does anybody know whether there are chips
> commercially available?
> 
> Thomas
> 
> 
> 
> 
> 
> 
> 
Article: 12347
Subject: Re: LCELL delay of Altera 10K's
From: "Ken Coffman" <kcoffman@intermec.com>
Date: 9 Oct 1998 17:47:24 GMT
Links: << >>  << T >>  << A >>
One method: Run the signal off-chip into a fast buffer, then through an RC
delay, then buffer it again with another fast buffer, and run it back into
your chip. It would be nice if the RC part of the delay is large compared
to the sum of the clock-->output delay, the pin buffer I/O delays, and the
buffer delays.
You could consider getting rid of the fast buffer if your R is large.
The best method would be to get rid of the delay requirement if at all
possible. If it's not possible, your synchronous design is entering the
nasty asynchronous world where you have to actually think carefully about
what you are doing.

John Huang <hungi@tpts4.seed.net.tw> wrote in article
<6vkgsh$jok$1@news.seed.net.tw>...
> Hi:
> 
> What is the best way to make delay in FPGA?
> 
> Regards
> 
> John Huang
> 
> emmanuel jolly ¼¶¼g©ó¤å³¹ <361d1908.103204@news.hol.fr>...
> >LCell time depends on Component family and speed grade (10K, 10KA,
> >10KE, -4, -3, -2, -1).
> >It is not a good design rule to use LCELL to implement delay. Use it
> >only if you have no other solution
> >
> >Regards
> >
> >On Fri, 9 Oct 1998 01:08:15 +0800, "John Huang"
> ><hungi@tpts4.seed.net.tw> wrote:
> >
> >>Hi all:
> >>
> >>    Does anyone know the delay time of one LCELL,
> >>if I implement an VHDL statement
> >>
> >>  U1: LCELL(CLK1, CLK2);
> >>
> >>  the CLK2 will be delay how many ns?
> >>
> >>    John Huang
> >>
> >>
> >
> >---
> >Pour me contacter enlever "removethis." de mon adresse Email.
> >To contact me, remove "removethis." from my Email address.
> 
> 
> 
Article: 12348
Subject: Re: What is an embedded IrDA (infrared) software protocol stack?
From: "Scot E. Wilcoxon" <sewilco@fieldday.mn.org>
Date: Fri, 09 Oct 1998 12:51:20 -0500
Links: << >>  << T >>  << A >>
> . RTOS ready

You sent this to a Linux group but did not mention
if it's available as a Linux module.
Article: 12349
Subject: Re: Design security again - the Actel solution
From: z80@ds2.com (Peter)
Date: Fri, 09 Oct 1998 18:36:41 GMT
Links: << >>  << T >>  << A >>

I have met someone from a major ASIC house who described to me how
firms in Hong Kong have reverse engineered their clients' (digital)
ASICs back to a netlist of gates (!!) and done it reportedly for $25k;
this cost was for a 10k gate device but they can do much bigger ones
since the process is quite straightforward, for a given ASIC vendor.

One gets a hex listing of the ROM of an on-chip micro, or a normal
masked micro, for a similar amount. This firm offers 8051 cores and
they had this done to them.

All the above is done purely optically.

I don't know if an antifuse is optically visible, but Neocad obviously
did not spend $300M reverse engineering Xilinx's bitstream, and all
the "secrets" of every FPGA's SRAM/antifuse mapping are in any case
revealed when you disassemble their place & route tools.


--
Peter.

Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.


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