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Messages from 12550

Article: 12550
Subject: Re: XILINX 4000XL configuration using M 1.5 JTAG programmer
From: daveb@iinet.net.au (David R Brooks)
Date: Thu, 15 Oct 1998 22:06:39 GMT
Links: << >>  << T >>  << A >>
sucharita@my-dejanews.com wrote:

:Hi all,
:
:I am trying to configure a Xilinx XC4000XL part through  boundary scan using
:the JTAG programmer. I was wondering if anyone has been able to do this
:succesfully.
:
:I never see the "DONE" signal going high.
:I would really appreciate it if someone could give me some guidelines.
:
 I have done it for a XC4005, though not a 'XL. The story is on my
website, at:
http://www.iinet.net.au/~daveb/tricks/fpga-ldr/loader.html

--  Dave Brooks    <http://www.iinet.net.au/~daveb>
PGP public key via <http://www.iinet.net.au/~daveb/crypto.html>, or servers
Article: 12551
Subject: Re: 100 MHz FPGA
From: "Daniel K. Elftmann" <elftmann@ix.netcom.com>
Date: Thu, 15 Oct 1998 20:36:03 -0400
Links: << >>  << T >>  << A >>
Actel A54SX16-2 VQ100 doing 125MHz 8B/10B Encoding and decoding is working
at customer in system, with no heat sink, and completely done in RTL Verilog
(No structural instantiation).  We successfully ran test vectors at 125MHz
on the tester at 105 degrees C per customer request.  See app. note:

http://www.actel.com/appnotes/5192650-0.pdf


Bruno Fierens wrote in message <704pn5$ge1@miura.gent.bg.barco.com>...
>> We are developing a high bandwidth switch architecture and we need to
>>test each switch interface at maximum speed of 100MB/s, which with an
>>8-bit interface requires a clock of 100MHz. Is there any FPGA out
>>there that would be able to sustain pumping data at this rate? I
>>thought of using a slower clock and a 32-bit interface from the FPGA
>>and then probably use a CPLD to multiplex the data to the switch 8-bit
>>interface. But there are problems associated with this. Any
>>suggestions?
>>
>In a Xilinx 4010XL-2, we built a 106.25MHz 8B/10B encoder/decoder
>which has a 2x10bit interface with an external component running at
>106.25MHz. With carefull pipelined design and proper timing constraints,
>this design even autoroutes without placement. And if this is not enough
>there are the brand new XLA devices, starting at 0.9 speed grades.
>
>Regards,
>Bruno
>
>
>


Article: 12552
Subject: Re: PCI target code
From: "Daniel K. Elftmann" <elftmann@ix.netcom.com>
Date: Thu, 15 Oct 1998 20:38:54 -0400
Links: << >>  << T >>  << A >>

Rickman wrote in message <3620F549.80B76A75@yahoo.com>...
>Gerald Coe wrote:
>>
>> I'm looking to implement a PCI target. I've found a chip from AMCC that
>> does it, but at a cost of uk26.00 100 off, its too expensive - costing
>> more than fpga real estate.
>>
>> I've also contacted xilinx but the PCI logicCore is well over uk3000.00
>> and a full development system well over uk5000.00.
>>
>> I can currently use xilinx devices and vantis cpld's, but for the right
>> target I'm will to look elsewhere. I have downloaded the vantis pci kit,
>> but it is undocumented and dosen't look complete.
>>
>> Does anyone know of free or low cost HDL/Schematic for a PCI target?
>
>The cost of development tools is always a problem for a low end user.
>Sometimes you can get your FAE to lend/give you the tools. Usually this
>is when you are a potentially big customer.
>
>If you can get the tools, Lucent has a chip that already has a PCI
>interface in it. So you don't have to pay for the IP of a core. It only
>comes in a 55K gate size so it may still be expensive. But you can check
>it out at <http://www.lucent.com/micro/fpga/series3plus.html>
>
>
>--
>
>Rick Collins
>
>redsp@XYusa.net
>
>remove the XY to email me.

The Lucent solution looks real good on paper.  I'd appreciate any feedback
from users who actually have this device on a board (not just in design).
Any cost info would be interesting as well, I've heard that it is very
expensive.


Article: 12553
Subject: How to decrease the XC95144's work current?
From: channing-wen@usa.net
Date: Fri, 16 Oct 1998 01:54:19 GMT
Links: << >>  << T >>  << A >>
I move a design to the Xilinx XC95144-TQ100, but I cannot bear the current
when it work, its about 220mA, could anybody tell me if somewhere is wrong
and how to deal with this?

Thanks.

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 12554
Subject: Re: PCI target code
From: tken%nedy@%primenet.com (Tim Kennedy)
Date: Thu, 15 Oct 1998 21:54:25 -0400
Links: << >>  << T >>  << A >>
I've spoken with Lucent within the last month or so, and the number I got
was $89 in lots of 25K or more. Too rich for my budget.

If you check out <http://www.isdmag.com/EEdesign/SoftCoretables.html>
about halfway down the page is Cypress' section, listing a free PCI core.
It only supports cypress parts, but the price is right.

Tim.
<tken%nedy@%primenet.com>
remove % to send mail


In article <7064u5$qof@sjx-ixn2.ix.netcom.com>, "Daniel K. Elftmann"
<elftmann@ix.netcom.com> wrote:

> Rickman wrote in message <3620F549.80B76A75@yahoo.com>...
> >Gerald Coe wrote:
> >>
> >> I'm looking to implement a PCI target. I've found a chip from AMCC that
> >> does it, but at a cost of uk26.00 100 off, its too expensive - costing
> >> more than fpga real estate.
> >>
> >> I've also contacted xilinx but the PCI logicCore is well over uk3000.00
> >> and a full development system well over uk5000.00.
> >>
> >> I can currently use xilinx devices and vantis cpld's, but for the right
> >> target I'm will to look elsewhere. I have downloaded the vantis pci kit,
> >> but it is undocumented and dosen't look complete.
> >>
> >> Does anyone know of free or low cost HDL/Schematic for a PCI target?
> >
> >The cost of development tools is always a problem for a low end user.
> >Sometimes you can get your FAE to lend/give you the tools. Usually this
> >is when you are a potentially big customer.
> >
> >If you can get the tools, Lucent has a chip that already has a PCI
> >interface in it. So you don't have to pay for the IP of a core. It only
> >comes in a 55K gate size so it may still be expensive. But you can check
> >it out at <http://www.lucent.com/micro/fpga/series3plus.html>
> >
> >
> >--
> >
> >Rick Collins
> >
> >redsp@XYusa.net
> >
> >remove the XY to email me.
> 
> The Lucent solution looks real good on paper.  I'd appreciate any feedback
> from users who actually have this device on a board (not just in design).
> Any cost info would be interesting as well, I've heard that it is very
> expensive.
Article: 12555
Subject: Re: gray code counter in a Xilinx fpga???
From: rk <stellare@NOSPAMerols.com>
Date: Thu, 15 Oct 1998 23:22:25 -0400
Links: << >>  << T >>  << A >>

--------------059036281B46B503EE72BDB8
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Dan Kuechle wrote:        <snip>

> Next question:
> Is there a similar relationship to convery the gray code back to binary?

yup, but at least the one i know isn't as nice as going the other way.

gray code number is:  G7 G6 G5 G4 G3 G2 G1 G0

binary code # is:     B7 B6 B5 B4 B3 B2 B1 B0

now, for each index j do

   for all Gi, i = 7 DownTo j, see if the number of 1's is even.

      if it's even
        then Gj = 1
        else Gj = 0

example: Gray       Binary

         1001011    1110010

rk





--------------059036281B46B503EE72BDB8
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<HTML>
<TT>Dan Kuechle wrote:</TT><TT></TT><TT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
&lt;snip></TT>
<BLOCKQUOTE TYPE=CITE><TT>Next question:</TT>
<BR><TT>Is there a similar relationship to convery the gray code back to
binary?</TT></BLOCKQUOTE>
<TT>yup, but at least the one i know isn't as nice as going the other way.</TT><TT></TT>

<P><TT>gray code number is:&nbsp; G7 G6 G5 G4 G3 G2 G1 G0</TT><TT></TT>

<P><TT>binary code # is:&nbsp;&nbsp;&nbsp;&nbsp; B7 B6 B5 B4 B3 B2 B1 B0</TT><TT></TT>

<P><TT>now, for each index j do</TT><TT></TT>

<P><TT>&nbsp;&nbsp; for all Gi, i = 7 DownTo j, see if the number of 1's
is even.</TT><TT></TT>

<P><TT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; if it's even</TT>
<BR><TT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; then Gj = 1</TT>
<BR><TT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; else Gj = 0</TT><TT></TT>

<P><TT>example: Gray&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Binary</TT><TT></TT>

<P><TT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 1001011&nbsp;&nbsp;&nbsp;
1110010</TT><TT></TT>

<P><TT>rk</TT><TT></TT>

<P><TT>&nbsp;</TT>
<BR><TT></TT>&nbsp;
<BR><TT></TT>&nbsp;</HTML>

--------------059036281B46B503EE72BDB8--

Article: 12556
Subject: What's wrong at this Address decoder?
From: leslie.yip@asmpt.com
Date: Fri, 16 Oct 1998 06:16:51 GMT
Links: << >>  << T >>  << A >>
Hello Everybody,

I would like to know what is worng with the ViewLogic's Synthesizer "Aurora"
to interpret the following code.

The error message is as follows:

The following is a list of the navigable error/warning messages in the
preceding run. Double clicking on a message will bring up the Viewer with the
cursor positioned at the offending line of code. VHDL: Error:
d:\vhdl_mfb3\mem_dec\mem_dec.vhd, line 28:   impossible to determine the type
of this parameter VHDL: Error: d:\vhdl_mfb3\mem_dec\mem_dec.vhd, line 30:    
 impossible to determine the type of this parameter VHDL: Error:
d:\vhdl_mfb3\mem_dec\mem_dec.vhd, line 32:	impossible to determine the
type of this parameter End navigable error/warning messages.

The code:
--------

-- Leslie Yip, ASM;     Jun, 8, 1998
-- Mem_dec.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

Entity MEM_DEC is
  port( ADDR:	 		in		std_logic_vector(19 downto 11);
        NMEMR,NMEMW:		in		std_logic;
--        NRST:			in		std_logic;
        RAMCE:			out		std_logic;
        DPRA,DPRB:		out		std_logic);
end MEM_DEC;

architecture MEM_DEC_ARCH of MEM_DEC is
-- signal dint,ddint: std_logic;
-- signal rint,fint: std_logic;

begin

process(ADDR, NMEMR, NMEMW)
begin
  DPRA <= '0';
  DPRB <= '0';
  RAMCE <= '0';
 if NMEMR='0' or NMEMW='0' then
   if ADDR >= x"D4000" and ADDR <= x"D47FF" then
     DPRA <= '1';
   elsif ADDR >= x"D4800" and ADDR <= x"D4FFF" then
     RAMCE <= '1';
   elsif ADDR >= x"DB000" and ADDR <= x"DB7FF" then
     DPRB <= '1';
   end if;
 end if;
end process;

end MEM_DEC_ARCH;

-----------== Posted via Deja News, The Discussion Network ==----------
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Article: 12557
Subject: Re: What's wrong at this Address decoder?
From: Geir Harris Hedemark <geirhe@hridil.ifi.uio.no>
Date: 16 Oct 1998 08:41:04 +0200
Links: << >>  << T >>  << A >>
leslie.yip@asmpt.com writes:
> The following is a list of the navigable error/warning messages in the
> preceding run. Double clicking on a message will bring up the Viewer with the
> (...)
>    if ADDR >= x"D4000" and ADDR <= x"D47FF" then
>      DPRA <= '1';

The comparison operators in std_logic_unsigned are only defined for
std_logic_vectors and integers. x"D47FF" is, as far as I can tell, a
bit vector, which is neither.

Try saying 

	if ADDR >= conv_integer(x"D4000") (...)

instead, and I think things will improve.

I am a Synopsys user. YMMV.

Geir

Article: 12558
Subject: Re: gray code counter in a Xilinx fpga???
From: fliptron@netcom.com (Philip Freidin)
Date: Fri, 16 Oct 1998 06:53:16 GMT
Links: << >>  << T >>  << A >>
In August of 1993, the most useful book on TTL design was published by 
Fairchild Semiconductor. The Title is "The TTL Application Handbook".
The book was written by several authors, some of whom I have had the 
pleasure of working with. It was edited by Peter Alfke!

On Page 5-60 are the following 4 gems. (with some slight editing
by me for current symbols). I assume you will all appreciate the
schematic nature of this post. All these designs have been simulated
with ViewSim, which worked just fine, and timing analysis was a snap.

Best viewed with a monospaced font (courier  :-)


Serial gray to binary, MSB first

                             +-----+
                             |     |
serial gray in --+-----------|J   Q|----binary out
                 |           |     |
                 |           |     |
                 +-----------|K    |
                             |     |
                             |     |
                 CLK --------|>    |
                             |     |
                             +-----+


Serial binary to gray, MSB first



                    +-----------------+
                    |                 |  \\---)  (an xor gate)
                    |        +-----+  +---\\   )
                    |        |     |       >>   )---- gray out
serial binary in-+--+--------|J   Q|------//   )
                 |           |     |     //---)
                 |  |\       |     |
                 +--| >o-----|K    |
                    |/       |     |
                             |     |
                 CLK --------|>    |
                             |     |
                             +-----+






Parallel gray to binary   (gates are all XOR)

     G0          G1          G2          Gn-1    Gn
     |           |           |           |       |
     |   +---+   |   +---+   |   +---+   |   +---+
     |   |   |   |   |   |   |   |   |   |   |   |
    \\   //  |  \\   //  |  \\   //  |  \\   //  |
    |\\ //|  |  |\\ //|  |  |\\ //|  |  |\\ //|  |
    | \v/ |  |  | \v/ |  |  | \v/ |  |  | \v/ |  |
    |  v  |  |  |  v  |  |  |  v  |  |  |  v  |  |
     \   /   |   \   /   |   \   /   |   \   /   |
      \ /    |    \ /    |    \ /    .    \ /    |
       v     |     v     |     v     .     v     |
       |     |     |     |     |     .     |     |
       |     |     |     |     |     .     |     |
       |     +-----+     +-----+     +-----+     |
       |           |           |           |     |
       |           |           |           |     |
       |           |           |           |     |
       B0         B1          B2         Bn-1    Bn


Parallel binary to gray   (gates are all XOR)



     B0          B1          B2          Bn-1    Bn
     |           |           |           |       |
     |   +-------+   +-------+   +--...--+   +---+
     |   |       |   |       |   |       |   |   |
    \\   //     \\   //     \\   //     \\   //  |
    |\\ //|     |\\ //|     |\\ //|     |\\ //|  |
    | \v/ |     | \v/ |     | \v/ |     | \v/ |  |
    |  v  |     |  v  |     |  v  |     |  v  |  |
     \   /       \   /       \   /       \   /   |
      \ /         \ /         \ /         \ /    |
       v           v           v           v     |
       |           |           |           |     |
       |           |           |           |     |
       |           |           |           |     |
       |           |           |           |     |
       |           |           |           |     |
       |           |           |           |     |
       G0         G1          G2         Gn-1    Gn



Enjoy

Philip Freidin
Article: 12559
Subject: Re: FOCUS FOCUS FOCUS
From: rk <stellare@NOSPAMerols.com>
Date: Fri, 16 Oct 1998 06:02:57 -0400
Links: << >>  << T >>  << A >>
ems@nospam.riverside-machines.com wrote about viewsim:

        < snip >

> 2) checking for errors is very difficult. you get lots of messages on
> the screen, and buried in them you may find that a notification that a
> check statement has failed.

during simulation try the following in your .cmd file:

check <node> <answer you want> >>  IScrewedUp.txt

then you don't have to look at anything in the screen log for error
notification.

IScrewedUp.txt will have a list of places where, well, you screwed up.

you can run the whole simulation from a batch file and then just look at
the file when it's done.  [running on win '95 pc].

rk


Article: 12560
Subject: Xilinx Virtex Experiences
From: "Reid Wender" <arw@asicint.com>
Date: Fri, 16 Oct 1998 08:44:47 -0400
Links: << >>  << T >>  << A >>
Has anyone been using the new Xilinx Virtex parts?

What are your thoughts?

Reid Wender


Article: 12561
Subject: Re: Fixed-point arithmetic coding
From: Iain Richardson <richardson@4i2i.com.REMOVE>
Date: Fri, 16 Oct 1998 13:45:36 +0100
Links: << >>  << T >>  << A >>
There are some useful pointers in "Digital Video Compression...." by
Vasudev Bhaskaran.
Alternatively, you could subcontract the work to us: we have developed
several successful Verilog that manipulate fixed point image data. Let
me know if this is of interest !

Iain Richardson.

junsc@sysic.hei.co.kr wrote:
> 
> Hi, All
> 
> I'm currently involved with the design that implements image signal
> processing. And there are some pipeline stages to manipulate one-byte RGB
> pixel values[0-255] by fixed point arithmetics[multiplication and divide].
> The fixed point arithmetic should be implemented with minimum hardware
> resources in order to be implemented in XILINX FPGA xc40000 series.
> 
> The problem is that I'm very new to this fixed point arithmetics coding and
> FPGA implementation.
> 
> Is there any good web/ftp site related to fixed point arithmetics HDL coding,
> especially Verilog and FPGA insight. Tutorial and examples would be great.
> 
> Any help would be greatly appreciated.
> 
> Thanks in advance.
> 
> Sungchun

-----
Iain E G Richardson, Technical Director
4i2i Communications Ltd
Doig Scott Building, Craibstone Estate, Bucksburn,
Aberdeen AB21 9YA, UK
Email richardson@4i2i.com.REMOVE, Web http://www.4i2i.com/
Tel +44 1224 712844, Fax +44 1224 714413
Article: 12562
Subject: Re: Digital Sine Generator
From: msimon@tefbbs.com
Date: Fri, 16 Oct 1998 12:48:18 GMT
Links: << >>  << T >>  << A >>
There is a way to sum a series of square waves to make any desired
waveshape.

Walsh transform I believe.

Simon
=====================================================================
Jonathan Bromley <jsebromley@brookes.ac.uk> wrote:

>Yves Vandervennet wrote:
>> Hi everybody,
>>         does anybody know how to digitally realize a sine generator
>> other than sampling a sine period and storing it in a ROM ?
>> We have to integrate it in an FPGA.
>
>How desperate are you for accuracy?  There are some simple cheap
>piecewise linear approximations that have fairly low total harmonic
>distortion (ones of percent) even though they look crude.  If you
>want the best you can get, find out about CORDIC generators - any
>search engine should make a good job of that.
>
>Aonther possibility which may be interesting in some FPGA
>architectures is to create a square wave (left as an exercise
>for the student!) and then pass it through some kind of DSP filter
>that lops off all the higher harmonics.  Full-blown FIR filters 
>are clearly out (cheaper to build the ROM), but there are other
>possibilities that are quite economical of resources.
>
>Enjoy
>Jonathan Bromley

Design Your Own MicroProcessor(tm) http://www.tefbbs.com/spacetime/index.htm
Article: 12563
Subject: Re: Digital Sine Generator
From: msimon@tefbbs.com
Date: Fri, 16 Oct 1998 12:51:28 GMT
Links: << >>  << T >>  << A >>
Very useful in machine tools where everything happens in steps.

Simon
========================================================
Jonathan Bromley <jsebromley@brookes.ac.uk> wrote:

>Peter wrote:
>> 
>> I have some old appnotes from Thomson-CSF from ~ 15 yrs ago when they
>> used to make the 9365/9367 CRT controller chip.
>> 
>> This implemented line drawing with the standard Bresenham algorithm,
>> and the appnotes contained details of what they called the Horn
>> algorithm  for drawing circles; the alg. actually generated the y
>> value for incrementing x, for an octant, and then one swapped x/y
>> values round in the obvious way to draw the complete circle. One could
>> always tell if some (slow!) graphics system used this algorithm
>> because circles were drawn starting in 8 places at once.
>
>Don't know if it's the same, but I have an appnote for the NS 32CG16
>which describes an algorithm attributed to Bresenham for drawing
>circles - once again, it only does one octant and you get the
>remaining seven by symmetry.  It's amazingly neat!  But beware: it's
>a tangent calculator, really - since one of the coordinates is
>incremented linearly - you never get to find out the angle (argument)
>of the point you are currently drawing.  I still say that CORDIC
>is the best way to go for most purposes.
>
>Jonathan Bromley

Design Your Own MicroProcessor(tm) http://www.tefbbs.com/spacetime/index.htm
Article: 12564
Subject: Re: Degradation of results from Xilinx F1.3 -> F1.4 -> F1.5
From: Nestor Caouras <nestor@macbeth.ece.concordia.ca>
Date: 16 Oct 1998 12:54:53 GMT
Links: << >>  << T >>  << A >>

Here is the reply I got from Xilinx regarding this problem.

Nestor.


-- Reply from Xilinx:

In response to your question(s):

1.) Yes the way of measuring Minimum Period (Maximum Frequency)
 has changed between Foundation 1.4 and 1.5.  This was
done to better represent the device.  So now in 1.5 the
 Minimum period is based upon the Maximum delay seen.

2.) Yes, each design is going to have a different operating 
frequency.  This is because every design was routed 
differently. The fact the performance is degrading is 
merely a coincidence.  The answer is based on two parts.
part 1.) The difference between Foundation 1.3 and 1.4 
is that the default effort level has changed (been reduced).
If you increase the effort level in 1.4 or 1.5 it should 
improve performance.
part 2.) 1.5 uses a different method of evaluating Minimum
period.  If one looks at the individual values between 
1.4 and 1.5 one can see that performance is increasing.
If one increased the effort level on 1.5 to that of 1.3.
The minimum period should be less than that of 1.3.
One final possiblity for the degradation in performance 
is the Foundation 1.3 & 1.4 used a different routing 
algorithim than 1.5 did and this may be a case where 
the new algorithim did not improve performance.

3.)  Regarding the warning (bitgen antenna warning...) 
it is impossible to say without having the Bitgen error.
Try the design in 1.5 with a higher effort level.

To increase the effort level on design go to your
implementation options, edit template for implementation
and the Place and Route tab.  This is where one can change 
the effort level.




Article: 12565
Subject: Where to find comp.arch.fpga newsgroup archive (please answer by e-mail vic@alpha.podol.khmelnitskiy.ua) (nothing inside)
From: vic@alpha.podol.khmelnitskiy.ua
Date: Fri, 16 Oct 1998 14:42:36 GMT
Links: << >>  << T >>  << A >>
:)
Article: 12566
Subject: Re: What's wrong at this Address decoder?
From: Dave D'Aurelio <daurelio@capture.kodak.com>
Date: Fri, 16 Oct 1998 10:50:57 -0400
Links: << >>  << T >>  << A >>
  I noticed that the ADDR port in the entity declaration is a std_logic_vector(19
downto 11) and that the decoder is being asked to decode values which are larger
than will fit within the 9 bits of address you have specified. Perhaps that is
causing part of the problem ?
The other problem - as noted in a previous post is that you are trying to compare
an integer value to a std_logic_vector type.




Article: 12567
Subject: Re: gray code counter in a Xilinx fpga???
From: "Austin Franklin" <darkroo3m@ix.netcom.com>
Date: 16 Oct 1998 14:58:36 GMT
Links: << >>  << T >>  << A >>
> Next question:
> Is there a similar relationship to convery the gray code back to binary? 


Wouldn't it depend on how you got there in the first place (as there are
different ways of generating grey code sequences)?

Austin

Article: 12568
Subject: Re: gray code counter in a Xilinx fpga???
From: iachetta@us.ibm.com (Richard Iachetta)
Date: Fri, 16 Oct 1998 10:16:31 -0500
Links: << >>  << T >>  << A >>
In article <01bdf853$558e3900$1f38d926@dank.i-tech.com>, dan_kuechle@i-
tech.com says...
> Many thanks to all who responded.  For my application, a fast carry binary
> counter followed by a registered xor array to convert binary to gray code
> will work beautifully.  I didn't realize the conversion from binary to gray
> code was so simple:
> q0(gray) = q0(bin) XOR q1(bin)
> q1(gray) = q1(bin) XOR q2(bin)
> q2(gray) = q2(bin) XOR q3(bin)

Dan, I haven't followed this whole thread so maybe its been mentioned but 
unless you re-latch q(gray) before using it, the combinatorial logic 
creating the gray code defeats the reason for gray code counters; i.e. that 
you can be sure that logic which decodes q(gray) doesn't glitch because 
only one q(gray) is guaranteed to change at a time.  But q(gray) generated 
with combinational logic from a binary count (without re-latching) will 
glitch.

-- 
Rich Iachetta
iachetta@us.ibm.com
I do not speak for IBM.
Article: 12569
Subject: Re: Xilinx may not support schematics for Virtex?????
From: "Austin Franklin" <darkroo3m@ix.netcom.com>
Date: 16 Oct 1998 17:19:32 GMT
Links: << >>  << T >>  << A >>
> > Try doing a functional simulation....I believe the underlying
simulation
> > libraries are not there....
> 
> >>I believe that is because the Virtex timing files were not in place
when they
> shipped F1.5 however, the timing models are coming.

That was the point.  The FAEs said that Xilinx has NO plans on providing
these, or supporting ANY schematic tools for Virtex.

Austin

Article: 12570
Subject: Re: Digital Sine Generator
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Fri, 16 Oct 1998 10:21:31 -0700
Links: << >>  << T >>  << A >>
msimon@tefbbs.com wrote in message <36274043.3771315@news.megsinet.net>...
>There is a way to sum a series of square waves to make any desired
>waveshape.
>
>Walsh transform I believe.
>

Additive synthesis!  (sorry, musician here...)

--
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
520-318-8191
apeters@noao.edu


Article: 12571
Subject: Re: Xilinx may not support schematics for Virtex?????
From: madarass@cats.ucsc.edu (Rita Madarassy)
Date: 16 Oct 1998 17:52:26 GMT
Links: << >>  << T >>  << A >>
In article <01bdf929$1e70db90$55f65ecf@drt1>,
Austin Franklin <darkroo3m@ix.netcom.com> wrote:
>> > Try doing a functional simulation....I believe the underlying
>simulation
>> > libraries are not there....
>> 
>> >>I believe that is because the Virtex timing files were not in place
>when they
>> shipped F1.5 however, the timing models are coming.
>
>That was the point.  The FAEs said that Xilinx has NO plans on providing
>these, or supporting ANY schematic tools for Virtex.

I do not understand how anyone would make a big deal about this.
Mentor Graphics uses vhdl models to simulate their schematic
capture tool and it works great.


>
>Austin
>


Article: 12572
Subject: Re: gray code counter in a Xilinx fpga???
From: fliptron@netcom.com (Philip Freidin)
Date: Fri, 16 Oct 1998 18:05:26 GMT
Links: << >>  << T >>  << A >>
It was late when I type the following article, and not all the proof
reading neurons were interconnected correctly. The screwup is the date
given for the apps book. The correct date was August 1973, not 1993. 

In article <fliptronF0wr4s.MII@netcom.com> fliptron@netcom.com (Philip Freidin) writes:
>In August of 1993, the most useful book on TTL design was published by 
>Fairchild Semiconductor. The Title is "The TTL Application Handbook".
>The book was written by several authors, some of whom I have had the 
>pleasure of working with. It was edited by Peter Alfke!

etc ...etc...etc ...
Article: 12573
Subject: Re: gray code counter in a Xilinx fpga???
From: rk <stellare@NOSPAMerols.com>
Date: Fri, 16 Oct 1998 14:59:41 -0400
Links: << >>  << T >>  << A >>
hi rich,

good point.  for the code results that i posted i had a register after the xor's
and evaluated that for the timing, although i didn't explicitly mention the
registers when i copied down the formulas.

rk

Richard Iachetta wrote:

> In article <01bdf853$558e3900$1f38d926@dank.i-tech.com>, dan_kuechle@i-
> tech.com says...
> > Many thanks to all who responded.  For my application, a fast carry binary
> > counter followed by a registered xor array to convert binary to gray code
> > will work beautifully.  I didn't realize the conversion from binary to gray
> > code was so simple:
> > q0(gray) = q0(bin) XOR q1(bin)
> > q1(gray) = q1(bin) XOR q2(bin)
> > q2(gray) = q2(bin) XOR q3(bin)
>
> Dan, I haven't followed this whole thread so maybe its been mentioned but
> unless you re-latch q(gray) before using it, the combinatorial logic
> creating the gray code defeats the reason for gray code counters; i.e. that
> you can be sure that logic which decodes q(gray) doesn't glitch because
> only one q(gray) is guaranteed to change at a time.  But q(gray) generated
> with combinational logic from a binary count (without re-latching) will
> glitch.
>
> --
> Rich Iachetta
> iachetta@us.ibm.com
> I do not speak for IBM.



Article: 12574
Subject: Re: PCI target code
From: "Austin Franklin" <darkroo3m@ix.netcom.com>
Date: 16 Oct 1998 23:43:41 GMT
Links: << >>  << T >>  << A >>
One of the problems with cheap and PCI in the same sentence is you have to
have a 32 bit address/data bus in/out to/from the PCI bus....in order to
support configuration space information.....and for address decode etc.

The above causes a problem when using a CPLD, as they don't have any
storage, except flops, and they are few compared to an FPGA.  I went to the
Cypress web site, and couldn't find a damn thing on PCI on their site...if
you do find anything, I'd be interested in looking at it...

Austin Franklin
darkroom@ix.netcom.com



Gerald Coe <gerry@see-sig.co.uk> wrote in article
<wscsnBA5TOI2EwkN@devantech.demon.co.uk>...
> 
> I'm looking to implement a PCI target. I've found a chip from AMCC that
> does it, but at a cost of uk26.00 100 off, its too expensive - costing
> more than fpga real estate. 
> 
> I've also contacted xilinx but the PCI logicCore is well over uk3000.00
> and a full development system well over uk5000.00. 
> 
> I can currently use xilinx devices and vantis cpld's, but for the right
> target I'm will to look elsewhere. I have downloaded the vantis pci kit,
> but it is undocumented and dosen't look complete.
> 
> Does anyone know of free or low cost HDL/Schematic for a PCI target?   
> 
> -- 
> Kindest Regards | gerry@devantech | We manufacture Pic programmers, 8031,
> Gerald Coe      | .demon.co.uk    | 68302, 64180, 80C188EB cpu modules. 
> http://www.devantech.demon.co.uk  | Full custom uP control systems
designed.
> 


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