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Messages from 129850

Article: 129850
Subject: XC3S50-4VQ100C fpga chip
From: Fei Liu <fei.liu@gmail.com>
Date: Thu, 6 Mar 2008 18:36:03 -0800 (PST)
Links: << >>  << T >>  << A >>
Hello,

  Not knowing better, I purchased a couple of these chips and now
realize they are 'not simulation ready'. Is there a way for me to use
these chips through breadboard or wiring? Or they are only supposed to
be part of a PCB board? In which case, can I order PCB boards using
chips? How do I do it?

  Also it seems to me it's way too expensive to build special purpose
IC device such as a door bell etc with fpga boards. FPGA boards are
general purpose device, like computers in a sense.

Fei

Article: 129851
Subject: how to Load file data into memory by NIOS II IDE?
From: Yao Sics <yao.sics@gmail.com>
Date: Thu, 6 Mar 2008 19:11:46 -0800 (PST)
Links: << >>  << T >>  << A >>
Dear all,

Please enlighten me on this!

Thanks in advance,

Sics

Article: 129852
Subject: Xilinx MIG2.0 DDR2 memory controller
From: chestnut <adam0818@gmail.com>
Date: Thu, 6 Mar 2008 19:34:09 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi,


I am using Xilinx Virtex5 to build a DDR2 SODIMM memory controller. It
is working well at 200MHz while having calibration problems at 300MHz.
after carefully debugging and simulation, I think that Xilinx
calibration algorithm didn't work well for big skews (about 900 ps
between DQS and its associated DQs) at 300MHz.

Anyone has know about Xilinx DDR2 calibration algorithm, please
advise. Thank you.

Article: 129853
Subject: Spartan-3A DSP Starter: JX Connector Part number
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Fri, 7 Mar 2008 09:56:12 +0000 (UTC)
Links: << >>  << T >>  << A >>
for trying to get a head start with embedded CPUs and Gigabit Ethernet, the 
Spartan-3A DSP Starter Platform seems a good deal. I tried hard, but didn't
find the specification of the JX1 and JX2 expansion connector specification.

Has anybody the part number of the connectors and the mating parts at hand?

Thanks
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 129854
Subject: Re: Xilinx MIG2.0 DDR2 memory controller
From: techG <giuliopulina@gmail.com>
Date: Fri, 7 Mar 2008 02:00:48 -0800 (PST)
Links: << >>  << T >>  << A >>
On Mar 7, 4:34 am, chestnut <adam0...@gmail.com> wrote:
> Hi,
>
> I am using Xilinx Virtex5 to build a DDR2 SODIMM memory controller. It
> is working well at 200MHz while having calibration problems at 300MHz.
> after carefully debugging and simulation, I think that Xilinx
> calibration algorithm didn't work well for big skews (about 900 ps
> between DQS and its associated DQs) at 300MHz.
>
> Anyone has know about Xilinx DDR2 calibration algorithm, please
> advise. Thank you.

I can't get it working even at 200 mhz.. I connected differential
clock of the board to ddr2 (200mhz), I followed instructions contained
in the pdf for writing the state machine for a test, but data I write
in ddr2 is always different from data I read, even I get init_done
signal and read_data_valid signal. Is your design with or without DCM?

Article: 129855
Subject: Re: how to Load file data into memory by NIOS II IDE?
From: =?ISO-8859-1?Q?G=F3rski_Adam?=
Date: Fri, 07 Mar 2008 11:42:14 +0100
Links: << >>  << T >>  << A >>
Yao Sics pisze:
> Dear all,
> 
> Please enlighten me on this!
> 
> Thanks in advance,
> 
> Sics
NIOS IDE : Tools->Flash Programmer....

Adam

Article: 129856
Subject: Re: Anyone to open "FPGA museum" ? Here is first item :)
From: Totally_Lost <air_bits@yahoo.com>
Date: Fri, 7 Mar 2008 03:58:08 -0800 (PST)
Links: << >>  << T >>  << A >>
On Mar 6, 1:18 am, -jg <Jim.Granvi...@gmail.com> wrote:
> Yes and no.  If you make devices that still need export licenses, it
> may not be a good idea to have visible displays for the spooks, of
> how these did get (easily) into the 'wrong' hands :)

Except for the fact that much of their production is offshore, where
export rules do not apply. Somebody in the US would only be liable if
there was a verified audit trail that the parts passed thru the US.


Article: 129857
Subject: Fixing design, leaving BRAMS variable
From: =?ISO-8859-1?Q?J=FCrgen_B=F6hm?= <jboehm@gmx.net>
Date: Fri, 07 Mar 2008 14:45:07 +0100
Links: << >>  << T >>  << A >>

Hi,

  currently I am about to finish a design for a Spartan 3 chip. The
design uses nearly all slices (98%, 5 slices left) and so PAR times are
very long.
   When the design is finished I just want to make changes to the
contents of the Block-Rams, leaving everything else untouched. What is
the best way to do this? Are relative placement macros needed? If yes I
would be very happy if someone could give me a short "recipe" for
working with RPMs as this seems to be a quite intricate theme. Maybe
there are good explanatory resources on the net, but I haven't found
them yet. Also I am still looking for a good way to learn how to
actually use the floorplanner - it seems to me like a black art...

Let me finish with a concrete question: Suppose I want to generate a RPM
from a hierarchy of modules of the form

module main (....)

wire memconnect

cpu cpu0 (...)
mem mem0 (...memconnect...)

endmodule

module cpu (..)
endmodule

module mem (..memconnect..)

BRAM bram0 (...)

defparam bram0/...

endmodule

where BRAM is one of the Spartan BRAMs and defparam bram0/.. setting the
contents of the BRAM. Is the contents of the BRAM fixed too in the
generated RPM? And can I circumvent this by restructuring the modules as

module main (....memconnect..)

inout memconnect;

cpu cpu0 (...)

endmodule

module cpu (..)

endmodule

module mem (..memconnect..)

BRAM bram0 (...)

defparam bram0/...

endmodule

and now building a RPM for main but not for mem?



Thanks in advance for all answers

Jürgen


-- 
Jürgen Böhm                                            www.aviduratas.de
"At a time when so many scholars in the world are calculating, is it not
desirable that some, who can, dream ?"  R. Thom

Article: 129858
Subject: Re: Spartan-3E + SPI EEPROM
From: Gabor <gabor@alacron.com>
Date: Fri, 7 Mar 2008 05:50:29 -0800 (PST)
Links: << >>  << T >>  << A >>
On Mar 6, 8:39 pm, sky46...@trline5.org wrote:
> Antti <Antti.Luk...@googlemail.com> wrote:
> >On 5 Mrz., 17:30, sky46...@trline5.org wrote:
> >> Would this eeprom work as a configuration boot eeprom for Xilinx XC3S500E ..?
> >>  http://ww1.microchip.com/downloads/en/DeviceDoc/22065A.pdf
> >generic answer: RTFM
> >25xxx chips are what is normally described "standard SPI", and have
> >0x03 READ command, so i would say its ok. But to be sure please verify
> >that it is OK, dont take my word (or anyone elses)
>
> When designing for Spartan-3E I stumbled on a post regarding Sp3E+SPI+SDcard
> and it got my thinking due that the the XCFxxS chips is harder to source than
> any "standard spi" eeprom. The price seems to be lower, and the wiring mess
> less. The only catch is the lack of Jtag port then.
>

Lack of JTAG is made up for by the programming software.  It bit-
wiggles
the FPGA pins to program the SPI PROM indirectly.

> However I was a bit unsure as to what the Spartan-3E required for a spi eeprom.
> At the distributor there are several "3-wire serial eeprom" chips. So the
> confusion was to make the correct match.

It's important to make sure the PROM supports the commands used by the
FPGA.  I ran into a problem with a smaller SPI PROM that didn't
support
a fast-mode read, usd by the Lattice ispVM software for verification.
It
worked OK for the FPGA's self-programming, however.  Eventually the
ispVM software was updated to work with the part.

HTH,
Gabor

Article: 129859
Subject: Re: Spartan-3E + SPI EEPROM
From: Antti <Antti.Lukats@googlemail.com>
Date: Fri, 7 Mar 2008 06:03:33 -0800 (PST)
Links: << >>  << T >>  << A >>
On Mar 7, 2:50 pm, Gabor <ga...@alacron.com> wrote:
> On Mar 6, 8:39 pm, sky46...@trline5.org wrote:
>
> > Antti <Antti.Luk...@googlemail.com> wrote:
> > >On 5 Mrz., 17:30, sky46...@trline5.org wrote:
> > >> Would this eeprom work as a configuration boot eeprom for Xilinx XC3S500E ..?
> > >>  http://ww1.microchip.com/downloads/en/DeviceDoc/22065A.pdf
> > >generic answer: RTFM
> > >25xxx chips are what is normally described "standard SPI", and have
> > >0x03 READ command, so i would say its ok. But to be sure please verify
> > >that it is OK, dont take my word (or anyone elses)
>
> > When designing for Spartan-3E I stumbled on a post regarding Sp3E+SPI+SDcard
> > and it got my thinking due that the the XCFxxS chips is harder to source than
> > any "standard spi" eeprom. The price seems to be lower, and the wiring mess
> > less. The only catch is the lack of Jtag port then.
>
> Lack of JTAG is made up for by the programming software.  It bit-
> wiggles
> the FPGA pins to program the SPI PROM indirectly.
>
> > However I was a bit unsure as to what the Spartan-3E required for a spi eeprom.
> > At the distributor there are several "3-wire serial eeprom" chips. So the
> > confusion was to make the correct match.
>
> It's important to make sure the PROM supports the commands used by the
> FPGA.  I ran into a problem with a smaller SPI PROM that didn't
> support
> a fast-mode read, usd by the Lattice ispVM software for verification.
> It
> worked OK for the FPGA's self-programming, however.  Eventually the
> ispVM software was updated to work with the part.
>
> HTH,
> Gabor

well, I think the OP meant that cant use JTAG to program the SPI flash
at the moment this needs either custom application (what I use myself)
or ISE 10.1 should support SPI indirect for S3E

Antti





Article: 129860
Subject: Re: Spartan-3A DSP Starter: JX Connector Part number
From: John_H <newsgroup@johnhandwork.com>
Date: Fri, 07 Mar 2008 06:15:11 -0800
Links: << >>  << T >>  << A >>
Uwe Bonnes wrote:
> for trying to get a head start with embedded CPUs and Gigabit Ethernet, the 
> Spartan-3A DSP Starter Platform seems a good deal. I tried hard, but didn't
> find the specification of the JX1 and JX2 expansion connector specification.
> 
> Has anybody the part number of the connectors and the mating parts at hand?
> 
> Thanks

Spartan-3A DSP Starter Platform User Guide, UG454 (v1.0) October 3, 
2007. page 21:

EXP Interfaces
The EXP specification defines a 132-pin connector, with 24 power I/Os, 
24 grounds I/Os,
and 84 user I/Os. The standard EXP configuration implemented on the 
Spartan-3A DSP
Starter Platform uses two connectors (Samtec part number 
QTE-060-09-F-D-A) in a dual
slot EXP configuration, for a total of 168 user I/Os.

--------------

http://samtec.com/technical_specifications/overview.aspx?series=QTE

Digikey has stock on board heights 5, 8, 11, and 16 mm.

The mating connector is the QSE-060-01-L-D-A where Digikey also has stock.

I don't find the "SO" series of standoffs in Digikey's parts off hand.


- John_H

Article: 129861
Subject: Re: Spartan-3A DSP Starter: JX Connector Part number
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Fri, 7 Mar 2008 14:25:40 +0000 (UTC)
Links: << >>  << T >>  << A >>
John_H <newsgroup@johnhandwork.com> wrote:
...
> The mating connector is the QSE-060-01-L-D-A where Digikey also has stock.

Thanks,

seems I had tomatoes on my eyes...
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 129862
Subject: Re: Fixing design, leaving BRAMS variable
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 7 Mar 2008 15:21:49 -0000
Links: << >>  << T >>  << A >>

"Jürgen Böhm" <jboehm@gmx.net> wrote in message 
news:fqrgt3$o93$01$1@news.t-online.com...
>
> Hi,
>
>  currently I am about to finish a design for a Spartan 3 chip. The
> design uses nearly all slices (98%, 5 slices left) and so PAR times are
> very long.
>   When the design is finished I just want to make changes to the
> contents of the Block-Rams, leaving everything else untouched. What is
> the best way to do this? >
> Jürgen
>
>
Google data2mem
HTH., Syms. 



Article: 129863
Subject: Re: loading unisim in modelsim problem while testin xilinx ipcore
From: kian.zarrin@gmail.com
Date: Fri, 7 Mar 2008 08:28:14 -0800 (PST)
Links: << >>  << T >>  << A >>
On 11 Feb, 08:52, bvkrock <bvkr...@gmail.com> wrote:
> On Feb 10, 10:50 pm, Mike Treseler <mike_trese...@comcast.net> wrote:
>
> > kian.zar...@gmail.com wrote:
> > > # ** Error: fftk4.vhd(37): Library unisim not found.
> > > # ** Error: fftk4.vhd(38): (vcom-1136) Unknown identifier "unisim".
> > > what should i do?
>
> >http://groups.google.com/groups/search?q=3Dmodelsim+unisim+library
>
> I think you have not compiled libraries in xilinx keeping target
> browser as modelsim. you can do this by selecting the project's fpga
> package in (on left top browser), in properties u can assign target
> browser. After u do this when u highlight the package =A0in browser u'll
> see compile hdl libraries in the window below. compile it and
> libraries will be compiled in installed XILINX folder(search tht)
> change the the pref .tcl if ur confident about procedure to add
> libraries with path or in modelsim u can add libraries just mention
> the path. after u do this u shld see all the sim libraries (unisim,
> primsim and coresim) in the modelsim library window(below work library)

Dear bvkrock
Thank you for your help and sorry for this late response. i was trying
to follow your procedure for several month and i just got what i
should do. i compiled the libraries in the xilinx ISE program as you
said. i didn't di any furthur steps and just run modelsim and got no
errors. i didn't understood how and what libraries should i add in
modelsim but i think i since it is working, it is fine. i hope i
encounter no further issiues.
with thanks
kian
PS: just let me explain these stuff again in other words for other
people use:
to get the unisim library to wrok, you should compile libraries of the
fpga you are using. to do this:
1-open the xinlix program.
2-on the source browser window (on the top left) click on the FPGA
package.
3-right-click and choose properties and select modelsim PE as
simulator if you haven't(if you are using modelsim pe version)
4-when you select the fgpa package in the source browser window,
several options apear on the process window (window below source
browser). open design utilities and run compile hdl simulation
libraries. (if u get error regarding folder is cant be removed,
restart your computer and make sure only xilinx prgram is open).
5-now libraries are compiled. if you want to know where are they
compiled, see the console window.

Article: 129864
Subject: Re: XC3S50-4VQ100C fpga chip
From: Dave Pollum <vze24h5m@verizon.net>
Date: Fri, 7 Mar 2008 11:18:25 -0800 (PST)
Links: << >>  << T >>  << A >>
On Mar 6, 9:36 pm, Fei Liu <fei....@gmail.com> wrote:
> Hello,
>
>   Not knowing better, I purchased a couple of these chips and now
> realize they are 'not simulation ready'. Is there a way for me to use
> these chips through breadboard or wiring? Or they are only supposed to
> be part of a PCB board? In which case, can I order PCB boards using
> chips? How do I do it?
>
>   Also it seems to me it's way too expensive to build special purpose
> IC device such as a door bell etc with fpga boards. FPGA boards are
> general purpose device, like computers in a sense.
>
> Fei

SparkFun has a simple board that has a Spartan-3 (3e?) mounted along
with voltage regulators.  Also check out Digilent's starter boards
from ~$100 to ~$150 (digilentinc.com).  Also Enterpoint
(enterpoint.co.uk) has Spartan-3 and 3E boards.
HTH
-Dave Pollum

Article: 129865
Subject: Altera Quartus II v7.2 SP2 under openSUSE 10.3 (i686)
From: n08W10+mgk25@cl.cam.ac.uk (Markus Kuhn)
Date: 7 Mar 2008 19:36:11 GMT
Links: << >>  << T >>  << A >>
Did someone here have any luck with using Altera Quartus II v7.2 SP2
under openSUSE Linux 10.3.

It seems to work fine under openSUSE 10.2 and Fedora Core 6.

But when I try to start quartus (the main GUI) under
openSUSE 10.3 (i686), it either simply exits after a
few seconds or it sometimes just blocks, without any
error message and before even showing the spash screen.

Using strace suggests that things go wrong soon after
some font-related activity, i.e. soon after the system call

  writev(20, [{"-\0\24\0_\0 \1B\0\0\0-adobe-helvetica-bol"..., 92}], 1) = 92

whereas under openSUSE 10.2 it calls instead

  write(19, "-\0\24\0x\0 \1B\0\0\0-adobe-helvetica-bol"..., 92) = 92

at the same location, suggestion that there have been
some changes in libraries.

Any clues or suggestions?

Markus

-- 
Markus Kuhn, Computer Laboratory, University of Cambridge
http://www.cl.cam.ac.uk/~mgk25/ || CB3 0FD, Great Britain

Article: 129866
Subject: ML523 power module schematics
From: "Roger" <enquiries@rwconcepts.co.uk>
Date: Fri, 7 Mar 2008 20:41:10 -0000
Links: << >>  << T >>  << A >>
Does anyone know how I'm supposed to get hold of the ML523 power module 
schematics? The link on the web site doesn't work.

TIA,

Rog. 


Article: 129867
Subject: SiliconBlue enters the FPGA fray
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Sat, 08 Mar 2008 10:01:24 +1300
Links: << >>  << T >>  << A >>
  Talk of devices from 1,792 to 15,260 logic blocks, and currents
a little under Altera'a MAX IIZ (on a Logic Block basis).

  Not stellar Static ICc values, but reasonable - considering they
have to fight 65-nm process leakages.

  So the logic sounds generic - what about the memory ?
Does anyone know the details of the memory technology ?

  They seem VERY cagey on the exact memory technology, and do not use the
words Reprogramable - but there is mention of
"The architecture is said to be scalable to 40-nm and the family is 
being offered in both volatile and non-volatile memory versions"

and this comment is a little ominous
"In our business it is critical to have fast, accurate simulation 
technology in order to ensure first-pass working devices,"


So it looks like OTP memory loading a SRAM FPGA ?, and the volatile
models could either be the largest ones, or ones that failed the OTP 
tests ?.

OTP is tolerable for config memory, if you can bypass that
for development - some CPLDs offer this dual-path already.

Even uC are revisiting OTP (after some claims FLASH was the only path)
so there must be price benefits.

If it is OTP, that raises the question of programming yields, and flows.

The FPGA market is not showing strong growth, in fact they vacuum R&D 
dollars, whilst under-performing the fabless industry averages.
Can SiliconBlue hit critical mass ?

-jg


Article: 129868
Subject: Re: ML523 power module schematics
From: austin <austin@xilinx.com>
Date: Fri, 07 Mar 2008 13:07:37 -0800
Links: << >>  << T >>  << A >>
Roger,

Have you filed a webcase?

Austin

Article: 129869
Subject: Re: SiliconBlue enters the FPGA fray
From: austin <austin@xilinx.com>
Date: Fri, 07 Mar 2008 13:12:05 -0800
Links: << >>  << T >>  << A >>
Jim,

http://www.siliconbluetech.com/technology.html

details their "technology" which is licensed from Kilopass.

http://www.kilopass.com/product.html

Austin

Article: 129870
Subject: Re: SiliconBlue enters the FPGA fray
From: austin <austin@xilinx.com>
Date: Fri, 07 Mar 2008 13:14:29 -0800
Links: << >>  << T >>  << A >>
Jim,

It is an anti-fuse array technology.

Austin

Article: 129871
Subject: Re: SiliconBlue enters the FPGA fray
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Sat, 08 Mar 2008 10:57:51 +1300
Links: << >>  << T >>  << A >>
austin wrote:
> Jim,
> 
> It is an anti-fuse array technology.

Thanks. Any comments on programming Speed, and Yields ? :)

-jg


Article: 129872
Subject: Re: Anyone to open "FPGA museum" ? Here is first item :)
From: Derek Palmer <d.e.r.e.k.p.a.l.m.e.r@x.i.l.i.n.x.c.o.m>
Date: Fri, 07 Mar 2008 14:14:51 -0800
Links: << >>  << T >>  << A >>
Antti wrote:
> On 5 Mrz., 22:15, sky46...@trline5.org wrote:
>   
>> Antti <Antti.Luk...@googlemail.com> wrote:
>>     
>>> Hi
>>> some things are cute to trash, so if anyone cares for an item that
>>> could have its honor place in "FPGA museum", here it is:
>>> http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&rd=1&item=190204160335
>>> A Xilinx XC3030 based device manufactured by GRU (== russian CIA).
>>> I found it in the cellar.
>>> And no, I did not get it directly from the source ;)
>>>       
>> What did the chips & software cost at the time..?
>>     
>
> :) nothing / as not in shops...
>
> pretty much ALL electronic components sales at that time was black-
> market only.
> And almost all of them was stolen from the military fabs.
> There was very little in the official shops, the real component market
> was openly-hidden somewhere close by in big cities Moscow/St.
> Petersburg. In other places there was possible some "guy" coming each
> few weeks with "stuff" so you could "pre-order" things from him. Or
> you could go yourself to the cities where the fabs where and deal
> there yourself. Funny times.
>
> But when you ask the prices, actually I do recall the pricing, think
> not much
> different than now XC2064 around 15 USD I think. I recall it because
> in one design
> I used 13 GAL's what was not much more then price of cheapest Xilinx
> chip
> and the GAL's where around 1 USD
>
> Antti
>   

Somewhere in my attic I still have a copy of Altera's Sam+Plus and 
A+Plus SW and manuals.  It was so much easier in the DOS days.  If 
synthesis wouldn't get it right, you could go in and set the bits in the 
JEDEC file and make it work.  You could do some really cool stuff that 
way.  I once put a 33 macrocell design in a 32 macrocell part!  The 
Cypress FAE never figured out how I made it work! :-) Ah! the good old days.

Derek Palmer
9 years @ Altera
2 years @ Synopsys (FPGA express)
3 years @ Chameleon Systems (FPGA+Processor)
3 years @ Tensilca (Real configurable processors)
3 years @ Xilinx (doing processor stuff)
I'm very FPGA biased.
>
>   

Article: 129873
Subject: Re: SiliconBlue enters the FPGA fray
From: austin <austin@xilinx.com>
Date: Fri, 07 Mar 2008 14:30:52 -0800
Links: << >>  << T >>  << A >>
Jim,

Nope.  It also has a shadow SRAM array, so you can program it over and
over for debug and test.

Then when you are happy with it, you may program the NVM anti-fuse
array, and then set a "can't do anything with SRAM anymore bit" so the
device is now like our Coolrunner CPLD's:  reads the (eflash) NVM into
SRAM on power up.

Not strange to me at all why they chose this set of features.

But, the FPGA business is not just silicon, it is also software
development tools, IP, applications, customer service, design service, ....

Without a portfolio of hard IP (MAC, PCIe, USB, SerDes, uP, MMU ...)
they are also immediately at a disadvantage.

Austin

Article: 129874
Subject: Re: Spartan-3E + SPI EEPROM
From: Gabor <gabor@alacron.com>
Date: Fri, 7 Mar 2008 14:32:23 -0800 (PST)
Links: << >>  << T >>  << A >>
On Mar 7, 9:03 am, Antti <Antti.Luk...@googlemail.com> wrote:
> On Mar 7, 2:50 pm, Gabor <ga...@alacron.com> wrote:
>
>
>
> > On Mar 6, 8:39 pm, sky46...@trline5.org wrote:
>
> > > Antti <Antti.Luk...@googlemail.com> wrote:
> > > >On 5 Mrz., 17:30, sky46...@trline5.org wrote:
> > > >> Would this eeprom work as a configuration boot eeprom for Xilinx XC3S500E ..?
> > > >>  http://ww1.microchip.com/downloads/en/DeviceDoc/22065A.pdf
> > > >generic answer: RTFM
> > > >25xxx chips are what is normally described "standard SPI", and have
> > > >0x03 READ command, so i would say its ok. But to be sure please verify
> > > >that it is OK, dont take my word (or anyone elses)
>
> > > When designing for Spartan-3E I stumbled on a post regarding Sp3E+SPI+SDcard
> > > and it got my thinking due that the the XCFxxS chips is harder to source than
> > > any "standard spi" eeprom. The price seems to be lower, and the wiring mess
> > > less. The only catch is the lack of Jtag port then.
>
> > Lack of JTAG is made up for by the programming software.  It bit-
> > wiggles
> > the FPGA pins to program the SPI PROM indirectly.
>
> > > However I was a bit unsure as to what the Spartan-3E required for a spi eeprom.
> > > At the distributor there are several "3-wire serial eeprom" chips. So the
> > > confusion was to make the correct match.
>
> > It's important to make sure the PROM supports the commands used by the
> > FPGA.  I ran into a problem with a smaller SPI PROM that didn't
> > support
> > a fast-mode read, usd by the Lattice ispVM software for verification.
> > It
> > worked OK for the FPGA's self-programming, however.  Eventually the
> > ispVM software was updated to work with the part.
>
> > HTH,
> > Gabor
>
> well, I think the OP meant that cant use JTAG to program the SPI flash
> at the moment this needs either custom application (what I use myself)
> or ISE 10.1 should support SPI indirect for S3E
>
> Antti

I wasn't aware of this.  I currently only use SPI parts with Lattice.
Their ispVM software handles it OK.

Regards,
Gabor



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