Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Take a look at the "light 8080" at open cores.
The author made it very small. For fun I moved the registers into block
RAM (M4K)and nearly halved the size down to 230 LE on Cyclone 2.
There is enough documentation with the project to get you started.
+------------------------------------------------------------------------------+
; Fitter Summary
;
+------------------------------------+-----------------------------------------+
; Family ; Cyclone II
;
; Device ; EP2C20F484C7
;
; Timing Models ; Final
;
; Total logic elements ; 230 / 18,752 ( 1 % )
;
; Total combinational functions ; 227 / 18,752 ( 1 % )
;
; Dedicated logic registers ; 99 / 18,752 ( < 1 % )
;
; Total registers ; 99
;
; Total pins ; 74 / 315 ( 23 % )
;
; Total virtual pins ; 0
;
; Total memory bits ; 16,000 / 239,616 ( 7 % )
;
; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % )
;
; Total PLLs ; 0 / 4 ( 0 % )
;
+------------------------------------+-----------------------------------------+
climber.tim@gmail.com wrote:
> Hi.
> It's probably not very good place for asking such, but there're should
> be at least those who knows starting points.
> We need to design our own CPU which can be very slow. It can execute
> each instruction, let's say, up to 50 cycles. We don't care about
> speed, and we are also don't care about memory size for microcode, but
> we're really care about CPU unit size.
> Where to read about CPU designing techniques, which are about shifting
> all possible to microcode from CPU unit? Extreme case will be probably
> Turing machine, but it's not practical. CPU registers and instructions
> in our case should be looks like ARM9 processor, maybe.
Article: 130151>Why and how has xilinx managed to create software that triggers virus >on alert on task "HDL parse" ??? Those virus checkers tend to shoot from the hip.Article: 130152
On 17 Mrz., 11:16, sky46...@trline4.org wrote: > >Why and how has xilinx managed to create software that triggers virus > >on alert on task "HDL parse" ??? > > Those virus checkers tend to shoot from the hip. If Xilinx would do REAL BETA testing, it could still be possible to prevent that SP3->SP4 update causes the anti-virus alerts come!! AnttiArticle: 130153
On 17 Mrz., 10:20, sky46...@trline4.org wrote: > climber....@gmail.com wrote: > Instructions that you ought to have: > Shift left/right You do not need a left shift (add suffices) but the right shift is actually a necessary operation. To the OP: Read fpgacpu.org (outdated but good) Also see this: http://eis.eit.uni-kl.de/eis/teaching/practical/files/KapE.pdf http://eis.eit.uni-kl.de/~kolja/assembler.html Kolja SulimmaArticle: 130154
climber.tim@gmail.com wrote: > Hi. > It's probably not very good place for asking such, but there're should > be at least those who knows starting points. > We need to design our own CPU which can be very slow. It can execute > each instruction, let's say, up to 50 cycles. We don't care about > speed, and we are also don't care about memory size for microcode, but > we're really care about CPU unit size. > Where to read about CPU designing techniques, which are about shifting > all possible to microcode from CPU unit? Extreme case will be probably > Turing machine, but it's not practical. CPU registers and instructions > in our case should be looks like ARM9 processor, maybe. Sounds like homework ?. If you want simple, search for MC14500, which will give you a very small opcode set, to start from. If this is targeting FPGA, then better might be Mico8, PicoBlaze, or similar 8 bit variants. Also, if size matters more than speed, you could look at a core optimised to execute from SPI Serial memory, and you could map spare, non-hardcoded opcodes, into a jump table - that allows you to make up more opcodes in firmware. -jgArticle: 130155
Me too. I need to stream 60 Bits at 833MHz in our next project to a large RAM, so depending on controller overhead something like 64 bit at 500MHz DDR would be a good thing to have. Kolja Sulimma On 17 Mrz., 10:10, "Morten Leikvoll" <mleik...@yajoo.nospam> wrote: > Austin, > For > Xilinx, I have no idea how wide bus they can do. I've only seen 64bit > designs at much lower rate for now. I am hoping they(you?) can show me > something better. > > Because of this, I need to see a working design before aiming at any number. > "austin" <aus...@xilinx.com> wrote in message > > We have DDR3 designs that are also working at 533 MHz.Article: 130156
<climber.tim@gmail.com> wrote in message news:97c32a9f-aec1-4862-97dc-1fe6455f407c@m3g2000hsc.googlegroups.com... > Hi. > It's probably not very good place for asking such, but there're should > be at least those who knows starting points. > We need to design our own CPU which can be very slow. It can execute > each instruction, let's say, up to 50 cycles. We don't care about > speed, and we are also don't care about memory size for microcode, but > we're really care about CPU unit size. > Where to read about CPU designing techniques, which are about shifting > all possible to microcode from CPU unit? Extreme case will be probably > Turing machine, but it's not practical. CPU registers and instructions > in our case should be looks like ARM9 processor, maybe. I would suggest you check out the 16C54 from Microchip, very simple instruction set and you can find a number of free implementations on the web in both Verilog/VHDL. I my experience writing the software tools take far more time than writing a simply processor so try to use an existing instruction set. Good luck, Hans www.ht-lab.comArticle: 130157
On 17 Mrz., 13:58, David Brown <da...@westcontrol.removethisbit.com> wrote: > Antti wrote: > > On 17 Mrz., 11:16, sky46...@trline4.org wrote: > >>> Why and how has xilinx managed to create software that triggers virus > >>> on alert on task "HDL parse" ??? > >> Those virus checkers tend to shoot from the hip. > > > If Xilinx would do REAL BETA testing, it could still be possible to > > prevent that SP3->SP4 update causes the anti-virus alerts come!! > > Should Xilinx check all their software with all the virus checkers > available? False alarms like that are the fault of the virus checkers, > and are a good example of how useless most windows "security" software > really is (hint - if your desktop anti-virus software finds something > during on-access scanning, you've done something badly wrong). there are not so many virus scanners actually, and yes this test could be done. and yes, maybe i need another anti-virus thing ;) AnttiArticle: 130158
We want to use FPGA for the research in robotics in our university. We have some experience with FPGA spartan II board but now we feel we need a board where we can put soft core processor and has large size. We want to buy Xilinx Virtex II pro FPGA board that could be used for variety of researches in digital system. Now xilinx states that the price for the board is $299 under the university program. If we spend this much money, can we start using the board, as I've known that most of the softwares needed would be provided by xilinx for free. Still, I'm not sure this includes all the software required to start building our applications. Furthermore, what about the softcore processor,. Can we use processor, say, microblaze in that board without paying extra money. In short, I'm trying to know the total cost before we can use this board. One reason I've posted this here, is also to get some idea of how difficult would it be to start making some small systems in this board for student like me, I've experience with microcontrollers like 8051, and PIC. and have used VHDL to design hardware in Spartan II FPGA. Waiting for the answers!!!Article: 130159
Ok, the existing IP uses a lot of clocks and my logic must be very simple. Anyway I'd like to ask what is the difference between IBUFG and BUFG. If the input to the DCM is: bufg_syncclk: bufg port map ( i=>sync_clk, o=>sync_clk_dcm); I get the error, but if the input is: bufg_syncclk: ibufg port map ( i=>sync_clk, o=>sync_clk_dcm); I don't. Why happens that?. Should I LOC the clock buffers?. Thanks, Daniel. On Mar 14, 11:09 pm, "jtw" <wrightjt @hotmail.invalid> wrote: > The simple rule is "use a BUFG." If you have a [very] small fanout, you may > be able to get away without it, but you may need to place all your FFs > appropriately; otherwise, you have a high probably of lousy clock skew and > lousy routing. > > Ideally, pre-pin-selection planning lets you assign all your potential > clocks to appropriate pins; a select number of pins have 'favored' > connections to the BUFGs. > > If you don't have such luxury (and I would guess you don't), you need to > carefully control the routing of your input clock to control its phase > relative to the input/output data at the IOBs. If you can control the > routing (i.e., make the delay predictable), then you can use a DCM to > produce a phase-corrected clock (2x, /N, ...), and use normal clock routing > resources. (And face the Primary/Secondary restrictions in each quadrant, > which gets to be quite a pain when you exceed 8 clocks and want matched > BUFGs... but that is another story.) > > There are lots of good app notes on Xilnx' web site. Enjoy reading. > > JTW > > "Daniel" <dte...@gmail.com> wrote in message > > news:dab9fdbc-46a6-4d02-bd4e-fc8386f2ad77@q78g2000hsh.googlegroups.com... > > > Hi, > > I'm adding new logic to an existing IP. This IP uses a DCM to manage > > it's sys_clk. > > My logic is using another (external) clock which is an input port to > > the top level. > > My logic works fine if I don't use DCM nor bufg (a global clock), but > > it doesn't pass routing stage. I get this message error: > > > ERROR:Place:249 - Automatic clock placement failed. Please attempt to > > analyze the Global clocking required for this > > design and either lock the clock placement or area locate the logic > > driven by the clocks so that that the clocks may > > be placed in such a way that all logic driven by them may be > > routed. The main restriction on clock placement is that > > only one clock output signal for any Primary / Secondary pair of > > clocks may enter any region. For further > > information see the "Using Global Clock Networks" section in the V- > > II User Guide (Chapter 2: Design Considerations) > > Phase 5.30 (Checksum:2faf07b) REAL time: 2 mins 11 secs > > > Where to start?. I guess the problem are two clocks BUFGMUX#P and > > BUFGMUX#S acessing the same quadrant but what to do?. How can I be > > sure of what's realy happening?. > > > Please help me!!!. > > > Thanks, > > Daniel.Article: 130160
On Mar 14, 9:59 pm, p...@coho.org wrote: > Can you separate the register from the tri-state? > > I have always coded this (in Verilog) as > > input pin; > ... > reg pin_en; > reg pin_out; > > assign pin = pin_en ? pin_out : 1'bz; > > Then I assign to pin_en and pin_out however I want, although usually > with an always @(posedge clk). > > The flip-flop will map into the IOB if the resource is available, > otherwise into the array. Active high enables often don't push into the IOB. I would suggest rather: assign pin = pin_en ? 1'bz : pin_out; But in the end I've found that duplicate register removal also prevents pushing tristate registers into the IOB's (if more than one pin has the same tristate function). Also providing the registered function in a lower level module, but the tristate function at the top level will prevent the push. i.e. the assign pin ... statement in the top level module, but the clocked always blocks for pin_en in a lower level module. Regards, GaborArticle: 130161
Antti wrote: > On 17 Mrz., 11:16, sky46...@trline4.org wrote: >>> Why and how has xilinx managed to create software that triggers virus >>> on alert on task "HDL parse" ??? >> Those virus checkers tend to shoot from the hip. > > If Xilinx would do REAL BETA testing, it could still be possible to > prevent that SP3->SP4 update causes the anti-virus alerts come!! > Should Xilinx check all their software with all the virus checkers available? False alarms like that are the fault of the virus checkers, and are a good example of how useless most windows "security" software really is (hint - if your desktop anti-virus software finds something during on-access scanning, you've done something badly wrong).Article: 130162
On 17 Mrz., 13:16, "HT-Lab" <han...@ht-lab.com> wrote: > <climber....@gmail.com> wrote in message > > news:97c32a9f-aec1-4862-97dc-1fe6455f407c@m3g2000hsc.googlegroups.com... > > > Hi. > > It's probably not very good place for asking such, but there're should > > be at least those who knows starting points. > > We need to design our own CPU which can be very slow. It can execute > > each instruction, let's say, up to 50 cycles. We don't care about > > speed, and we are also don't care about memory size for microcode, but > > we're really care about CPU unit size. > > Where to read about CPU designing techniques, which are about shifting > > all possible to microcode from CPU unit? Extreme case will be probably > > Turing machine, but it's not practical. CPU registers and instructions > > in our case should be looks like ARM9 processor, maybe. > > I would suggest you check out the 16C54 from Microchip, very simple > instruction set and you can find a number of free implementations on the web > in both Verilog/VHDL. I my experience writing the software tools take far > more time than writing a simply processor so try to use an existing > instruction set. > > Good luck, > > Hanswww.ht-lab.com well, there are well-known candidates for SMALL FPGA CPU, but for the following spec * 32 bit registers, say block of 16 (use 32 LUTRAM == 16 LUT/LC) * serialized can run from spi flash up to 320MBit with http://www.winbond.com/NR/rdonlyres/4C63AD62-967C-4B72-AF85-1F5984E8B199/0/W25Q80.pdf * can address large code space * can run at high fabric clocks (due to lack of parallel buses and parallel ALUs) now a bit-serialized CPU to the above spec can be done. it would use less than 100 slices. if anyone is willing to desing this CPU, I may have funds for it, really please... hm at 320MB/sec spi streaming, we get byte reads at 40Mhz from serial flash! so this serialized pico-cpu with less than 100 slices would outperform many 8 bit microcontrollers and 8 bit microprocessors of the past. And as the same flash could be used for FPGA config this 10 MIPS engine comes virtually free. pls do not suggest that picoblaze, or pic12 or i8080 can do this for this low fabric utilization AnttisArticle: 130163
Antti wrote:
> and yes, maybe i need another anti-virus thing ;)
My favorite is linux ;)
-- Mike Treseler
Article: 130164Antti <Antti.Lukats@googlemail.com> wrote: > On 17 Mrz., 01:21, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> > wrote: ... > > The software deployment doesn't deploy the license. You can > > however download it seperate, by trying to download > > again and mark the license agreement box and save it to a > > local file. Apendix C, Top 2 however talks about the > > possibility to redistribute changed code free, in the > > sense of open source. > > > > What counts? > > > please read Lattice main License, Appendix C > it clearly says ALL FILES GENERATED by Mico32 tools are subject to the > open-source licensing, so it over-rides whatever is prefixed into the > hdl source code. > you can distribute those files under open-source license, also if > modfied > and you can distribute you own addons under any license you want > and there is no vendor locking to Lattice, the stuff under lattice > opensource license can be implemented for ANY FPGA or ASIC > this is how i read it, > Antti > PS there is DDR2 IP Core mico32 so you can use it on Spartan3A starter > board :) If you look at ttp://www.latticesemi.com/products/intellectualproperty/ipcores\ /mico32/mico32peripherals.cfm you will see the DDR1/DDR2/Tri-Speed MAC/PCI Target 33HHz marked with a star, meaning a seperate license. The verilog directories for these peripherals deployed by the installation also seems to contain only wrappers around EDK specific modules not provided and probably contain a lot of lattice part specific code. Anyways, looking at the other directories, there only contain few Lattice specific primitives, like IO Buffer, BRAM and FIFO, where it should be not to hard to write wrappers that resolve into other vendors primitives.However Icarus verilog still has some problems withe the present Lattice code. Hopefully stephen, cary and Larry wil care. Didn't run XST on some directory neither... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 130165
On 17 Mrz., 15:16, Mike Treseler <mike_trese...@comcast.net> wrote: > Antti wrote: > > and yes, maybe i need another anti-virus thing ;) > > My favorite is linux ;) > > -- Mike Treseler when the day comes, when *) ALL FPGA vendors see Linux as PRIMARY O/S *) ALL JTAG and ISP cable vendors support linux as PRIMARY O/S I would say it too. but I have to wait :( AnttiArticle: 130166
On 17 Mrz., 15:17, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> wrote: > Antti <Antti.Luk...@googlemail.com> wrote: > > On 17 Mrz., 01:21, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> > > wrote: > ... > > > The software deployment doesn't deploy the license. You can > > > however download it seperate, by trying to download > > > again and mark the license agreement box and save it to a > > > local file. Apendix C, Top 2 however talks about the > > > possibility to redistribute changed code free, in the > > > sense of open source. > > > > What counts? > > > please read Lattice main License, Appendix C > > it clearly says ALL FILES GENERATED by Mico32 tools are subject to the > > open-source licensing, so it over-rides whatever is prefixed into the > > hdl source code. > > you can distribute those files under open-source license, also if > > modfied > > and you can distribute you own addons under any license you want > > and there is no vendor locking to Lattice, the stuff under lattice > > opensource license can be implemented for ANY FPGA or ASIC > > this is how i read it, > > Antti > > PS there is DDR2 IP Core mico32 so you can use it on Spartan3A starter > > board :) > > If you look at > ttp://www.latticesemi.com/products/intellectualproperty/ipcores\/mico32/mico32peripherals.cfm > > you will see the DDR1/DDR2/Tri-Speed MAC/PCI Target 33HHz marked with a > star, meaning a seperate license. The verilog directories for these > peripherals deployed by the installation also seems to contain only wrappers > around EDK specific modules not provided and probably contain a lot of > lattice part specific code. > > Anyways, looking at the other directories, there only contain few Lattice > specific primitives, like IO Buffer, BRAM and FIFO, where it should be not > to hard to write wrappers that resolve into other vendors primitives.However > Icarus verilog still has some problems withe the present Lattice > code. Hopefully stephen, cary and Larry wil care. > > Didn't run XST on some directory neither... > > -- > Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- i did not notice the * but a) if you are student you can use the time limited version b) for commercial use you just need pay license and that it work well so or so ah, if you want mico32 with DDR2 on Xilinx? well, you dont expect Lattice to offer that? as of mico32 with XST, I did that LOOOOONG ago it did take maybe some hour of tweaking. XST doesnt support verilog good enough to synthesize mico32 code AnttiArticle: 130167
"Jonathan Bromley" <jonathan.bromley@MYCOMPANY.com> wrote in message news:e0est356k8ji6osq2hhkmelcdkfebnhmtr@4ax.com... > On Mon, 17 Mar 2008 01:37:43 -0700 (PDT), climber.tim@gmail.com wrote: > > Do you *need* 32-bit? What are you proposing to do with this > slow CPU?. His homework. ;)Article: 130168
bish <bisheshkh@gmail.com> wrote: > We want to use FPGA for the research in robotics in our university. We > have some experience with FPGA spartan II board but now we feel we > need a board where we can put soft core processor and has large size. > We want to buy Xilinx Virtex II pro FPGA board that could be used for > variety of researches in digital system. Now xilinx states that the > price for the board is $299 under the university program. For new designs, VII seems kind of outdated and overpriced. Spartan3, and especially 3E/3A/3AN/3ADSP contrains a lot of VII features and gives you more bang for the buck (Logic Cells/$) > If we spend this much money, can we start using the board, as I've > known that most of the softwares needed would be provided by xilinx > for free. Still, I'm not sure this includes all the software required > to start building our applications. Furthermore, what about the > softcore processor,. Can we use processor, say, microblaze in that > board without paying extra money. > In short, I'm trying to know the total cost before we can use this > board. Some eval boards come with a Softcore license, the pure processor license will also not be that expensive if bought for university teaching. There are also some free core, where you can trade buying costs for your time getting everything up and debugged. > One reason I've posted this here, is also to get some idea of how > difficult would it be to start making some small systems in this board > for student like me, I've experience with microcontrollers like 8051, > and PIC. and have used VHDL to design hardware in Spartan II FPGA. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 130169
Hi Antti, Last week I gave a training on programmable logic and Xilinx's tools with ISE9.2i. It was a bit frustrating the time I lost helping students to solve this kind of upsets in the tools. I was so happy with 7.1.04 where everything seems stable. Now I have to use the 9.2 because the training and found several issues. Before naming them the solution for the right-button menu is simple: click with mouse at any place in the white background of the chain window. This will redraw the screen and then you can select a device in the chain and have the right-button menu working. The other glitches I found was problems downloading a design with USB cable (iMPACT must run outside ISE) and automatic file update/ assignment when the Assign Package Pins is kept open (inside ISE). Some times it works inside the tools. Seems to be directly realted to the lucky of the user. I had 12 students, 6 computers. Some did run inside ISE, others must run outside ISE in order to have the design downloaded. You can imagine the difficulty to explain to students (all engineers with discrete digital design experience and using X tools for the first time) those glitches does not mean the tools are bad... If I had enough time I would change the class manuals to "Using command line to solve GUI interface problems". The iMPACT also has a strange behavior whe using USB. If it does detect the USB cable has an old firmware version it gives no choice but update it. So, this update may take several hours (depending the computer) and, as far as I can imagine as a designer, the old version should be able to handle USB-JTAG interfacing or it would never be released. The update would help new features (or solve bugs in special cases) but the user should have the option not do it. Plain FLASH or FPGA configuration should take place no matter the USB cable version... Hope ISE10 will be better but as far as I was told it will demand more system memory and this alone mean more surprises... Best regards, AugustoArticle: 130170
"Antti" <Antti.Lukats@googlemail.com> wrote in message news:564d1032-a4bf-4615-b56e-8ec1ed31c7a8@f63g2000hsf.googlegroups.com... > > well, there are well-known candidates for SMALL FPGA CPU, but for the > following spec > > * 32 bit registers, say block of 16 (use 32 LUTRAM == 16 LUT/LC) > * serialized can run from spi flash up to 320MBit with > > http://www.winbond.com/NR/rdonlyres/4C63AD62-967C-4B72-AF85-1F5984E8B199/0/W25Q80.pdf > * can address large code space > * can run at high fabric clocks (due to lack of parallel buses and > parallel ALUs) > > now a bit-serialized CPU to the above spec can be done. > it would use less than 100 slices. > > if anyone is willing to desing this CPU, I may have funds for it, > really please... > > hm at 320MB/sec spi streaming, we get byte reads at 40Mhz from serial > flash! > > so this serialized pico-cpu with less than 100 slices would outperform > many > 8 bit microcontrollers and 8 bit microprocessors of the past. > > And as the same flash could be used for FPGA config this 10 MIPS > engine > comes virtually free. > > pls do not suggest that picoblaze, or pic12 or i8080 can do this for > this low fabric utilization > > Anttis > Hi Antti, How many LUTs in a slice? In other words, what is your target usage in terms of 4-LUTs? Thanks, Syms.Article: 130171
Austin, Peter, whoever: If someone dealing with a webcase finds that he is not the right person to deal with the case they usually suggest that I start a new case with an additional keyword to have it (hopefully) routed to the right expert. I think that is a strange strategy. The engineer dealing with the case is in a perfect position to find the right expert for me and forward the case accordingly. Everything else is just a waste of time for all parties involved. KoljaArticle: 130172
Morten, Like I advised, you need to get your local FAE in to see you. We have demo boards for memory, networking, PCI Express, etc. so it is not hard to see what we actually sell as a "realization" of our claims. http://www.xilinx.com/products/devkits/HW-V5-ML561-UNI-G.htm (memory pcb for V5) http://www.xilinx.com/products/devkits/HW-V5-ML555-G.htm (PCIe pcb for V5) ... Can you do better than we do on our own demo pcb's? Yes, you can, but that does require more work. The memory interface generator (MIG) is designed to "solve" the problems (not create new ones), so it is, by its very nature, conservative. What is more important: specifying your memory and pressing a button and generating a working design, or starting from scratch and squeezing the best performance possible out of the interface? Your choice, we will support you. Since our solution in V5 is still general (no hardened features for DDR3), the bus width is whatever you wish. I know of customers who use 288 bit wide bus, as that is 4 X 72, and 72 is the width needed to take advantage of the ECC block which can be used with your external memory (for error check and correct). I won't waste your time talking about Altera. Having their FAE visit you, and show you their solutions, is another necessary part of the work ahead of you. Then, you decide. I may be having fun right now due to Altera's 65nm misfortune, but I am a realist, too, and I know they will "be baaack!" AustinArticle: 130173
On 17 Mrz., 16:18, Kolja Sulimma <ksuli...@googlemail.com> wrote: > Austin, Peter, whoever: > > If someone dealing with a webcase finds that he is not the right > person to deal with the case they usually suggest that I start a new > case with an additional keyword to have it (hopefully) routed to the > right expert. > > I think that is a strange strategy. > > The engineer dealing with the case is in a perfect position to find > the right expert for me and forward the case accordingly. Everything > else is just a waste of time for all parties involved. > > Kolja Hi Kolja in virtually ALL OPENED webcases the person who gets the case assigned is not the right person. in virtually ALL cases where you need solution you need the "case acceleration" to next level(s) but think that is Xilinx strategy, they offer "platinum services" where they guarantee 24hrs response time. you need to pay for this service take a look at the webcase-per-week numbers, think this number may reach 2k/week... AnttiArticle: 130174
Bish, Have your professor contact the Xilinx University Program. http://www.xilinx.com/univ/ We provide the software tools you will require. Many of our partners also supply their tools also to universities and schools under their programs (Mentor, Synopsys, Cadence). The V2 Pro Digilent University board is supported, and as a XUP member, you send a coupon to "redeem" your FPGA (which then makes the board complete). Commercial users need to pay the full price of the FPGA to have one on the same pcb. There are newer (V5) boards for universities in the process, so your professor needs to contact the XUP program, and ask there. Nothing wrong with the V2 Pro board, however. The next versions of the Mars rovers will "upgrade" from Virtex 2, to Virtex 2 Pro, and in the process, go from less than 1 MPH, to as fast as you can run (from what I have heard). As far as soft processors go, a Spartan 3 board, with one of the largest S3 parts, would also be an excellent choice (and low cost). Again, the Digilent site is a good place to look. http://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD&Nav1=Products&Nav2=Programmable (with 3S1000, for example) http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-HB3&Nav1=Products&Nav2=Peripheral h-bridge for motor controls (many other pcb's available, too) Austin
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z