Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 130025

Article: 130025
Subject: ALTERA SOPC : ptf-sopc files
From: Charles Wagner <charles.wagner@irisa.fr>
Date: Thu, 13 Mar 2008 14:47:47 +0100
Links: << >>  << T >>  << A >>
Hi all,


SOPC version 7.1 and later  use a new XML file format .sopc for storing 
system design data instead  PTF format
For PTF format  a "SOPC Builder PTF File" reference manual (december 
2003) was available.
I don't find  an reference manual for .sopc.

In "Avalon Memory-Mapped Interface Specification" readdata, writedata 
and data signals are 1-1024 bits width.
In "SOPC Builder PTF File" reference manual" Data_Width assignment 
allowed values are 8,16,32 (slaves) and 16,32 (masters).
What about data signals greater than 32 ?

Thanks for your help,

Charles

Article: 130026
Subject: Re: microblaze to blockram - Byte-Writes
From: Andreas Hofmann <ahnews@gmx.net>
Date: Thu, 13 Mar 2008 14:56:22 +0100
Links: << >>  << T >>  << A >>
kislo schrieb:
> I am trying to interface a 32 bit blockram to microblaze (spartan 3E),
> using the User-Address ip support in the "Create and import
> peripheral". I have instantiated a black box blockram 32x256 and it
> works fine with read and write operations of 32bit datawidth. But how
> can i perform 8bit write and read operations? i know there are the BE
> (byte_enable) bus, but i cant see how this can work with a single
> block ram .. i would need 4 block ramīs inorder to perform byte write
> and reads or what? i can see that in the never FPGA`s (according to
> Block Memory Generator 2.6 .pdf) that block ram supports Byte-Writes,
> which is EXACTLY what i need .. but im using the spartan 3E which
> dosent support this feature .. are there any work around so i dont
> need 4 block ramīs of 8x256 instead of a single 32x256 ? ... is there
> a way to create more than one block ram instance that only uses one
> block-ram in hardware?

No, if you need byte-wise write-access to the memory and can't afford
using 4 BlockRAMs you have to design a BlockRAM controller that does a
read-modify-write access. This should be simple but of course will
result in a multiple clock-cycle delay for each 8-bit/16-bit access.

Regards,
Andreas

Article: 130027
Subject: Re: microblaze to blockram - Byte-Writes
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 13 Mar 2008 09:03:48 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 12, 6:17=A0pm, kislo <kisl...@student.sdu.dk> wrote:
> I am trying to interface a 32 bit blockram to microblaze (spartan 3E),
> using the User-Address ip support in the "Create and import
> peripheral". I have instantiated a black box blockram 32x256 and it
> works fine with read and write operations of 32bit datawidth. But how
> can i perform 8bit write and read operations? i know there are the BE
> (byte_enable) bus, but i cant see how this can work with a single
> block ram .. i would need 4 block ram=B4s inorder to perform byte write
> and reads or what? i can see that in the never FPGA`s (according to
> Block Memory Generator 2.6 .pdf) that block ram supports Byte-Writes,
> which is EXACTLY what i need .. but im using the spartan 3E which
> dosent support this feature .. are there any work around so i dont
> need 4 block ram=B4s of 8x256 instead of a single 32x256 ? ... is there
> a way to create more than one block ram instance that only uses one
> block-ram in hardware?
>
> Regards
> Kim

Kim, remember that the BlockRAM is dual-ported, so it has two
independent addressing mechanisms. That means you can write and read
byte-wide on one port, and write and read 32-bit wide on the other
port, with both ports accessing the same information.
Peter Alfke, Xilinx Applications

Article: 130028
Subject: Re: Matlab, RS-232, Ethernet
From: jkljljklk <maricic@gmail.com>
Date: Thu, 13 Mar 2008 09:23:03 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 11, 9:49 am, satyam <satyam.dwiv...@gmail.com> wrote:
> Hi,
>
> I want to interface matlab with the Xilinx Virtex-II pro board. Intent
> is to give input from matlab to the FPGA and to read the ouput of FPGA
> in matlab.
>
> Problem is in interfacing speed. I need high speed interface, of the
> order of 2 mega bits per second (Mbps). Seems RS-232 will be
> inadequate for my purpose. From Documents interface through ethernet
> seems to be a viable option but I am not sure. To summarize I want
> answers and suggestions on following:
>
> 1). FPGA to PC communication by ethernet ?
> 2). What can be the maximum speed ?
> 3). How to transfer data on ethernet by matlab ?
> 4). Is it possible to write inputs (60 Mega bits) to some memory on
> FPGA board and then read it from there to do the computation ?

60Mbits is not a problem for Xilinx Virtex 4, I am using it do acquire
data synchronously at that rate, 8 inputs in parallel, do some
computation on them and write to the memory at the same clock cycle.

I do not need real time download from this memory, I use VGA to see
the real time data from the memory. For downloading the FPGA's memory
content I use ChipScope.

Dan


>
> Please let me know if you have any suggestion for me.
>
> Thank You.
>
> StYm


Article: 130029
Subject: Re: Almost offtopic about HDL optimizing.
From: "MM" <mbmsv@yahoo.com>
Date: Thu, 13 Mar 2008 11:24:24 -0500
Links: << >>  << T >>  << A >>
All that you could save would be object or executable file size. And who 
cares about the file size these days... If you are interested to find out 
which parts of your software code will never get executed, there are tools 
for that available...

/Mikhail



"sdf" <drop669@gmail.com> wrote in message 
news:52f45619-6f30-4c3c-8000-7acd4edf0b49@e10g2000prf.googlegroups.com...
> Hi.
> I see how Quartus synthesizer removes unused parts of algorithm
> implemented in HDL, optimizes it and so on.
> Other synthesizers probably do the same.
> My question is almost offtopic: is there any method to do the same in
> software code?
> Is the starting point is in compiler theory or there're also another
> topics? 



Article: 130030
Subject: Re: Design complexity in Logic cells - Virtex-5 FPGA
From: Mike Treseler <mike_treseler@comcast.net>
Date: Thu, 13 Mar 2008 09:51:13 -0700
Links: << >>  << T >>  << A >>
muthusnv@gmail.com wrote:
> Some IP vendors gives the complexity of the device in terms of "LCs
> (Logic Cells)".
> How can I calcuate Logic cells from information available in Map
> report?

Ask the vendor for LUTs and Flops stats for your device.
If they can't tell you, find another vendor.

          -- Mike Treseler

Article: 130031
Subject: Re: ALTERA SOPC : ptf-sopc files
From: KJ <kkjennings@sbcglobal.net>
Date: Thu, 13 Mar 2008 10:16:59 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 13, 9:47=A0am, Charles Wagner <charles.wag...@irisa.fr> wrote:
> Hi all,
>
> SOPC version 7.1 and later =A0use a new XML file format .sopc for storing
> system design data instead =A0PTF format
> For PTF format =A0a "SOPC Builder PTF File" reference manual (december
> 2003) was available.
> I don't find =A0an reference manual for .sopc.
>

I doubt that you will find such a manual either, although you could
post a question to Altera about it.  Even the "SOPC Builder PTF File
reference manual" disappeared off of their web site several years
back, long before their even was a new file format and .PTF files were
the only file format used by SOPC.  That manual was incredibly useful
when you're developing SOPC components, and difficult to develop
sophisticated components without it.  For whatever reason Altera chose
to remove useful info from developers.  I chose to stop using SOPC
Builder (for various reasons in addition to this action).

> In "Avalon Memory-Mapped Interface Specification" readdata, writedata
> and data signals are 1-1024 bits width.
> In "SOPC Builder PTF File" reference manual" Data_Width assignment
> allowed values are 8,16,32 (slaves) and 16,32 (masters).
> What about data signals greater than 32 ?
>
Data widths greater than 32 weren't supported back then.

Kevin Jennings

From webmaster@nillakaes.de Thu Mar 13 10:22:16 2008
Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin2!goblin.stu.neva.ru!newsfeed.utanet.at!feeder06.uucp-net.de!news.uucp.at!feed.cnntp.org!news.cnntp.org!not-for-mail
Message-Id: <47d962a7$0$580$6e1ede2f@read.cnntp.org>
From: Thorsten Kiefer <webmaster@nillakaes.de>
Subject: Problem with Spartan 3 StarterKit
Newsgroups: comp.arch.fpga
Date: Thu, 13 Mar 2008 18:22:16 +0100
User-Agent: KNode/0.10.4
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7Bit
Lines: 12
Organization: CNNTP
NNTP-Posting-Host: 31789c3c.read.cnntp.org
X-Trace: DXC=nVakcUA6>bbMWC5:2mK0foWoT\PAgXa?af7hk0B9Y_he1P5d:S1^>6cdlT:^LKmYjj?Zc58STOR;oSR5>dB75[io
X-Complaints-To: abuse@cnntp.org
Xref: prodigy.net comp.arch.fpga:142373

Hello,
ich have the Spartan3 StarterKit from Digilent.
When I start the programming process in impact,
all LEDs on the board go red, and on the screen
an progress dialog appears. When the progress is at
about 98%, it stalls for 8 seconds, and then the message
appears : "'1' : Programming terminated. DONE did not go high"
Can you help me ?

Regards
Thorsten


Article: 130032
Subject: Re: Matlab, RS-232, Ethernet
From: sky465nm@trline4.org
Date: Thu, 13 Mar 2008 19:30:06 +0100 (CET)
Links: << >>  << T >>  << A >>
>Ethernet is a complex and expensive protocol (in terms of time) to
>implement.  How about the opencores  USB 1.1 PHY/IP and using libusb
>on the PC side?  It seems to me this would be much less time consuming
>than ethernet.

What do you base your statement that ethernet is hard to deal with..?


Article: 130033
Subject: Re: Cyclone III FPGA Starter Kit: As USB device? Using JTAG terminal
From: ghelbig@lycos.com
Date: Thu, 13 Mar 2008 11:34:23 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 12, 8:53 pm, "Xilinx User" <anonym...@net.com> wrote:
> I thought Altera uses one of FTDI 's USB/RS-232 bridge-chips in their
> programming solution.
>

Nope.  The Altera USB dongle is a FT245BL -> EPM3128ATC100.  (The EPM
does the FIFO to JTAG translation.)

The USB port the OP "found" is literally the Altera USB dongle without
the plastic case.

G.

Article: 130034
Subject: Re: Problem with Spartan 3 StarterKit
From: ghelbig@lycos.com
Date: Thu, 13 Mar 2008 11:37:44 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 13, 10:22 am, Thorsten Kiefer <webmas...@nillakaes.de> wrote:
> Hello,
> ich have the Spartan3 StarterKit from Digilent.
> When I start the programming process in impact,
> all LEDs on the board go red, and on the screen
> an progress dialog appears. When the progress is at
> about 98%, it stalls for 8 seconds, and then the message
> appears : "'1' : Programming terminated. DONE did not go high"
> Can you help me ?
>
> Regards
> Thorsten

More data please:
* Which starter kit?
* What file are you trying to load?
* What are you trying to load it with?

Are you confident that the file you are trying to load is correct for
the device you are trying to load?  It may be that you're trying to
load a file for the "next smaller" FPGA.

G.

From webmaster@nillakaes.de Thu Mar 13 11:45:50 2008
Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin1!goblin.stu.neva.ru!news.albasani.net!feed.cnntp.org!news.cnntp.org!not-for-mail
Message-Id: <47d9763e$0$583$6e1ede2f@read.cnntp.org>
From: Thorsten Kiefer <webmaster@nillakaes.de>
Subject: Re: Problem with Spartan 3 StarterKit
Newsgroups: comp.arch.fpga
Date: Thu, 13 Mar 2008 19:45:50 +0100
References: <47d962a7$0$580$6e1ede2f@read.cnntp.org> <0f531b0d-fd29-4b35-b5c0-afaec90d3e1e@e10g2000prf.googlegroups.com>
User-Agent: KNode/0.10.4
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7Bit
Lines: 22
Organization: CNNTP
NNTP-Posting-Host: 9e0538b5.read.cnntp.org
X-Trace: DXC=B`Yd6fZi_KUS03?DM:TjdRWoT\PAgXa?QaW[_@WQ]BhS1P5d:S1^>6SdlT:^LKmYjZ::7_\<TBMCQl8iEgG6o>dP
X-Complaints-To: abuse@cnntp.org
Xref: prodigy.net comp.arch.fpga:142377

ghelbig@lycos.com wrote:

> More data please:
> * Which starter kit?
The one with the Xilinx XC3S200

> * What file are you trying to load?
eq2.bit
(A 2 bit comparator.  4 switches are input, and 1 led is ouput.)

> * What are you trying to load it with?
impact

> 
> Are you confident that the file you are trying to load is correct for
> the device you are trying to load?  It may be that you're trying to
> load a file for the "next smaller" FPGA.
i created the project for exactly that device

> 
> G.
TK

Article: 130035
Subject: Re: Problem with Spartan 3 StarterKit
From: Paul Urbanus <urbpublic@hotmail.com>
Date: Thu, 13 Mar 2008 14:06:26 -0500
Links: << >>  << T >>  << A >>
Thorsten Kiefer wrote:
> Hello,
> ich have the Spartan3 StarterKit from Digilent.
> When I start the programming process in impact,
> all LEDs on the board go red, and on the screen
> an progress dialog appears. When the progress is at
> about 98%, it stalls for 8 seconds, and then the message
> appears : "'1' : Programming terminated. DONE did not go high"
> Can you help me ?
> 
> Regards
> Thorsten
> 

Can you successfully load the example project, s3demo.bit?

If so, then there must some problem with your generated .bit file.

From webmaster@nillakaes.de Thu Mar 13 12:23:08 2008
Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin2!goblin.stu.neva.ru!newsfeed.utanet.at!feeder06.uucp-net.de!news.uucp.at!feed.cnntp.org!news.cnntp.org!not-for-mail
Message-Id: <47d97efc$0$584$6e1ede2f@read.cnntp.org>
From: Thorsten Kiefer <webmaster@nillakaes.de>
Subject: Re: Problem with Spartan 3 StarterKit
Newsgroups: comp.arch.fpga
Date: Thu, 13 Mar 2008 20:23:08 +0100
References: <47d962a7$0$580$6e1ede2f@read.cnntp.org> <RNqdnb8h3uuu5kTanZ2dnUVZ_gKdnZ2d@speakeasy.net>
User-Agent: KNode/0.10.4
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7Bit
Lines: 4
Organization: CNNTP
NNTP-Posting-Host: 02b8c972.read.cnntp.org
X-Trace: DXC=j:2PCf13ZS=DORJ_DidWk<WoT\PAgXa?1Y70?_8WM9W=1P5d:S1^>63dlT:^LKmYj:gM=c9nZ3K35SR5>dB75[i?
X-Complaints-To: abuse@cnntp.org
Xref: prodigy.net comp.arch.fpga:142379

> Can you successfully load the example project, s3demo.bit?
Is it shipped with WebPack ?
I cannot find it in my ISE WebPack installation.


Article: 130036
Subject: SDC of NCF?
From: robquigley@gmail.com
Date: Thu, 13 Mar 2008 12:44:29 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hey everyone,

I recently started using Mentor Graphics Precision Synthesis for
fpga's after Leonardo Spectrum stopped supporting fpga's.

Now Precision is outputting constraints in an sdc file (Synopsys
Design Constraints i think) but then when i go to place and route
ngdbuild is looking for an ncf file?

I think Leonardo may have been outputting the ncf file (Netlist
Constraints File - right?) but I can't seem to find a way to convert
sdc files to ncf. Am i thinking about this the wrong way or what?

I dont think ngdbuild accepts sdc files as input so i'm stuck as to
how to get ngdbuild to apply my constraints.

Any help much appreciated! :-)


Cheers.


Rob.

From webmaster@nillakaes.de Thu Mar 13 12:47:17 2008
Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin1!goblin.stu.neva.ru!news.albasani.net!feed.cnntp.org!news.cnntp.org!not-for-mail
Message-Id: <47d984a4$0$580$6e1ede2f@read.cnntp.org>
From: Thorsten Kiefer <webmaster@nillakaes.de>
Subject: Re: Problem with Spartan 3 StarterKit
Newsgroups: comp.arch.fpga
Date: Thu, 13 Mar 2008 20:47:17 +0100
References: <47d962a7$0$580$6e1ede2f@read.cnntp.org> <RNqdnb8h3uuu5kTanZ2dnUVZ_gKdnZ2d@speakeasy.net>
User-Agent: KNode/0.10.4
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7Bit
Lines: 3
Organization: CNNTP
NNTP-Posting-Host: 02b8c972.read.cnntp.org
X-Trace: DXC=C@AUD>[3^1>iBm:2gM@Ib>WoT\PAgXa?1f7hk0B9Y_h51P5d:S1^>63dlT:^LKmYj:fHc>4b5O\32SR5>dB75[i?
X-Complaints-To: abuse@cnntp.org
Xref: prodigy.net comp.arch.fpga:142381

> Can you successfully load the example project, s3demo.bit?

No, same message

Article: 130037
Subject: Re: Problem with Spartan 3 StarterKit
From: Christian Schrader <weasel_rulez@web.de>
Date: Thu, 13 Mar 2008 20:59:08 +0100
Links: << >>  << T >>  << A >>
www.digilentinc.com





Thorsten Kiefer schrieb:
>> Can you successfully load the example project, s3demo.bit?
> Is it shipped with WebPack ?
> I cannot find it in my ISE WebPack installation.
> 

From webmaster@nillakaes.de Thu Mar 13 13:25:19 2008
Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin2!goblin.stu.neva.ru!news.visyn.net!news.code-werk.net!open-news-network.org!feed.cnntp.org!news.cnntp.org!not-for-mail
Message-Id: <47d98d8e$0$580$6e1ede2f@read.cnntp.org>
From: Thorsten Kiefer <webmaster@nillakaes.de>
Subject: Re: Problem with Spartan 3 StarterKit
Newsgroups: comp.arch.fpga
Date: Thu, 13 Mar 2008 21:25:19 +0100
References: <47d962a7$0$580$6e1ede2f@read.cnntp.org>
User-Agent: KNode/0.10.4
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7Bit
Lines: 21
Organization: CNNTP
NNTP-Posting-Host: 71d4139d.read.cnntp.org
X-Trace: DXC=JjXRK7L4DI_hm=^\mJ7;bRWoT\PAgXa?Qf7hk0B9Y_hU1P5d:S1^>6SdlT:^LKmYjZm9?6eGOVUXRSR5>dB75[i_
X-Complaints-To: abuse@cnntp.org
Xref: prodigy.net comp.arch.fpga:142384

Thorsten Kiefer wrote:

> Hello,
> ich have the Spartan3 StarterKit from Digilent.
> When I start the programming process in impact,
> all LEDs on the board go red, and on the screen
> an progress dialog appears. When the progress is at
> about 98%, it stalls for 8 seconds, and then the message
> appears : "'1' : Programming terminated. DONE did not go high"
> Can you help me ?
> 
> Regards
> Thorsten

OK I got it.
The configuration mode jumpers were set to "master serial".
I set them to "Jtag".
But the program is not persistent.
How can I make it persistent.
The JTAG chain shows a second device : xcf02s.
Is that the flash prom ?

Article: 130038
Subject: simulating Xilinx cores
From: FPGA <FPGA.unknown@gmail.com>
Date: Thu, 13 Mar 2008 13:27:42 -0700 (PDT)
Links: << >>  << T >>  << A >>
I would like to simulate some modules in Verilog along with a FIFO
generated by ISE core. I would like to know if it is possible to
simuate teh Xilinx generated cores. If so, which tools do I need to
use for that? Is there a free Xilinx simulator I could use to sereve
the purpose? I was using Modelsim till date. I dont think Modelsim
would recognize the Xilinx cores.
Your comments would be appreciated.

Article: 130039
Subject: Re: microblaze to blockram - Byte-Writes
From: kislo <kislo02@student.sdu.dk>
Date: Thu, 13 Mar 2008 14:26:50 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 13 Mar., 17:03, Peter Alfke <pe...@xilinx.com> wrote:
> On Mar 12, 6:17=A0pm, kislo <kisl...@student.sdu.dk> wrote:
>
>
>
>
>
> > I am trying to interface a 32 bit blockram to microblaze (spartan 3E),
> > using the User-Address ip support in the "Create and import
> > peripheral". I have instantiated a black box blockram 32x256 and it
> > works fine with read and write operations of 32bit datawidth. But how
> > can i perform 8bit write and read operations? i know there are the BE
> > (byte_enable) bus, but i cant see how this can work with a single
> > block ram .. i would need 4 block ram=B4s inorder to perform byte write
> > and reads or what? i can see that in the never FPGA`s (according to
> > Block Memory Generator 2.6 .pdf) that block ram supports Byte-Writes,
> > which is EXACTLY what i need .. but im using the spartan 3E which
> > dosent support this feature .. are there any work around so i dont
> > need 4 block ram=B4s of 8x256 instead of a single 32x256 ? ... is there
> > a way to create more than one block ram instance that only uses one
> > block-ram in hardware?
>
> > Regards
> > Kim
>
> Kim, remember that the BlockRAM is dual-ported, so it has two
> independent addressing mechanisms. That means you can write and read
> byte-wide on one port, and write and read 32-bit wide on the other
> port, with both ports accessing the same information.
> Peter Alfke, Xilinx Applications- Skjul tekst i anf=F8rselstegn -
>
> - Vis tekst i anf=F8rselstegn -

yes im aware of that, i just forgot to mention that the blockram i use
is configured as dualport connecting which is shared between the
microblaze and a peripheral unit. But i just have to live without
using byte writes ;) could be cool though to access bytes in the dual
port blockram using pointers ;)

Article: 130040
Subject: Re: Danger of having JTAG TAP controller always enabled in Xilinx
From: Jon Elson <elson@wustl.edu>
Date: Thu, 13 Mar 2008 15:44:51 -0600
Links: << >>  << T >>  << A >>


austin wrote:
> Non-space,
> 
> Virtually never.
> 
> More likely is noise, or uncontrolled garbage on the JTAG.  We have 
> actually seen a case where this happened (open pin, random noise, shuts 
> down system through JTAG).
Not just shut down, but fry it!  In the old days, I started with the 
XC9500 series CPLDs
(not designed by Xilinx, they bought this product) and was often lazy 
and left the JTAG pins open until I was sure I liked the program I 
loaded.  After smoking a couple CPLDs, I learned that this wasn't such a 
good idea, noise could actually reprogram the device to a pathological 
state that would fry it.  Sometimes I noticed the chip getting hot and 
killed power, and was able to reprogram and have it work again.  It 
wasn't just a latch-up, as powering off and back on resulted in the same 
non-operation and high current draw.  But, reprogramming would often fix 
it.  Finally I've gotten smart and put 3 pull-up resistors on the JTAG 
inputs so they never float.  With the FPGAs, they need a checksum to 
match to accept the configuration, so they don't burn up, at least.

Jon


Article: 130041
Subject: Re: simulating Xilinx cores
From: ghelbig@lycos.com
Date: Thu, 13 Mar 2008 14:45:55 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 13, 1:27 pm, FPGA <FPGA.unkn...@gmail.com> wrote:
> I would like to simulate some modules in Verilog along with a FIFO
> generated by ISE core. I would like to know if it is possible to
> simuate teh Xilinx generated cores. If so, which tools do I need to
> use for that? Is there a free Xilinx simulator I could use to sereve
> the purpose? I was using Modelsim till date. I dont think Modelsim
> would recognize the Xilinx cores.
> Your comments would be appreciated.

Try this:
<http://www.google.com/search?q=simulating+xilinx+cores>

Look at the 2nd result (of the about 248,000 hits).

At that site, Xilinx will teach you how to simulate Xilinx cores using
the Xilinx version of Modelsim.

Article: 130042
Subject: Re: SDC of NCF?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Thu, 13 Mar 2008 14:46:26 -0700
Links: << >>  << T >>  << A >>
robquigley@gmail.com wrote:

> Now Precision is outputting constraints in an sdc file (Synopsys
> Design Constraints i think) but then when i go to place and route
> ngdbuild is looking for an ncf file?

That's not so bad.
Constraints are simple for a synchronous design.
In any case, I have to specify and enter them manually somewhere,
and I prefer the backend where they won't be touched.

http://toolbox.xilinx.com/docsan/xilinx8/books/docs/cgd/cgd.pdf

      -- Mike Treseler

Article: 130043
Subject: Re: Problem with Spartan 3 StarterKit
From: Paul Urbanus <urbpublic@hotmail.com>
Date: Thu, 13 Mar 2008 17:04:03 -0500
Links: << >>  << T >>  << A >>
Thorsten Kiefer wrote:
> Thorsten Kiefer wrote:
> 
>> Hello,
>> ich have the Spartan3 StarterKit from Digilent.
>> When I start the programming process in impact,
>> all LEDs on the board go red, and on the screen
>> an progress dialog appears. When the progress is at
>> about 98%, it stalls for 8 seconds, and then the message
>> appears : "'1' : Programming terminated. DONE did not go high"
>> Can you help me ?
>>
>> Regards
>> Thorsten
> 
> OK I got it.
> The configuration mode jumpers were set to "master serial".
> I set them to "Jtag".
> But the program is not persistent.
> How can I make it persistent.
> The JTAG chain shows a second device : xcf02s.
> Is that the flash prom ?

You are correct - the memory in the FPGA is volatile (it's SRAM) and 
your program will vanish when power is removed.

Correct also on the second point - you must program the platform flash 
(xcf02s) with your fpga code. However, to do so you must first run the 
IMPACT tool to generate a programming file (I like to use the .mcs format).

*IMPORTANT* When you set the properties for generating your .bit file, 
make sure that you select the configuration clock as CCLK, as this is 
the clock that drives the xcf02s during configuration. There is no need 
to change this to JTAG clock while you are developing your code, as the 
IMPACT will recognize this mismatch and change the configuration clock 
from CCLK to JTAG whenever you load the .bit file directly into the FPGA.

Article: 130044
Subject: Re: Problem with Spartan 3 StarterKit
From: Paul Urbanus <urbpublic@hotmail.com>
Date: Thu, 13 Mar 2008 17:07:00 -0500
Links: << >>  << T >>  << A >>
Paul Urbanus wrote:
> Thorsten Kiefer wrote:
>> Thorsten Kiefer wrote:
>>
>>> Hello,
>>> ich have the Spartan3 StarterKit from Digilent.
>>> When I start the programming process in impact,
>>> all LEDs on the board go red, and on the screen
>>> an progress dialog appears. When the progress is at
>>> about 98%, it stalls for 8 seconds, and then the message
>>> appears : "'1' : Programming terminated. DONE did not go high"
>>> Can you help me ?
>>>
>>> Regards
>>> Thorsten
>>
>> OK I got it.
>> The configuration mode jumpers were set to "master serial".
>> I set them to "Jtag".
>> But the program is not persistent.
>> How can I make it persistent.
>> The JTAG chain shows a second device : xcf02s.
>> Is that the flash prom ?
> 
> You are correct - the memory in the FPGA is volatile (it's SRAM) and 
> your program will vanish when power is removed.
> 
> Correct also on the second point - you must program the platform flash 
> (xcf02s) with your fpga code. However, to do so you must first run the 
> IMPACT tool to generate a programming file (I like to use the .mcs format).
> 
> *IMPORTANT* When you set the properties for generating your .bit file, 
> make sure that you select the configuration clock as CCLK, as this is 
> the clock that drives the xcf02s during configuration. There is no need 
> to change this to JTAG clock while you are developing your code, as the 
> IMPACT will recognize this mismatch and change the configuration clock 
> from CCLK to JTAG whenever you load the .bit file directly into the FPGA.

Also, don't forget to change the configuration mode back to master 
serial after you have programmed the platform flash. Oh, you have to 
either cycle power or press the 'FGPA program' switch (if this is one on 
the board) before the FPGA will be loaded from the platform flash.

Article: 130045
Subject: Re: SDC of NCF?
From: "HT-Lab" <hans64@ht-lab.com>
Date: Thu, 13 Mar 2008 22:37:23 GMT
Links: << >>  << T >>  << A >>

<robquigley@gmail.com> wrote in message 
news:11b9ff67-60a0-4e85-a821-bcb522bfa49f@i29g2000prf.googlegroups.com...
> Hey everyone,
>
> I recently started using Mentor Graphics Precision Synthesis for
> fpga's after Leonardo Spectrum stopped supporting fpga's.

Hum.......? are you sure?

>
> Now Precision is outputting constraints in an sdc file (Synopsys
> Design Constraints i think) but then when i go to place and route
> ngdbuild is looking for an ncf file?

Precision will convert your SDC to UCF before invoking ISE. Just look in 
your implementation directory.

Hans
www.ht-lab.com

>
> I think Leonardo may have been outputting the ncf file (Netlist
> Constraints File - right?) but I can't seem to find a way to convert
> sdc files to ncf. Am i thinking about this the wrong way or what?
>
> I dont think ngdbuild accepts sdc files as input so i'm stuck as to
> how to get ngdbuild to apply my constraints.
>
> Any help much appreciated! :-)
>
>
> Cheers.
>
>
> Rob. 



Article: 130046
Subject: Design entries for FSM
From: Sue <sudhangi@gmail.com>
Date: Thu, 13 Mar 2008 18:10:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
Does anyone know how can  one enter FSM in Xilinx sysnthesis tool.
I have a FSM in a text format called the kiss2 format.
It looks something like this:

file input.kiss2
--------------------------------------------start of
file---------------------------
.i 2
.o 2
.p 8
.s 4
01 s0 s1 11
11 so s3 00
01 s1 s0 11
11 s1 s2 00
1- s2 s3 01
0- s2 s1 10
11 s3 s0 10
10 s3 s2 11
--------------------------------------------end of
file---------------------------------
i= # of inputs
o= # of outputs
p= # of transitions
s= # of states
01 so s1 11 = this is read as for input 01 and current state s0 the
output is 11 and next state is s1.
 '-' means don't care


Does anyone know a way in which I can convert this to a format such
that it can be entered into the Xilinx synthesis tool and I can get
the FSM synthesized for further use my implementation

Article: 130047
Subject: Re: Design entries for FSM
From: John_H <newsgroup@johnhandwork.com>
Date: Thu, 13 Mar 2008 21:12:03 -0700
Links: << >>  << T >>  << A >>
Sue wrote:
> Does anyone know how can  one enter FSM in Xilinx sysnthesis tool.
> I have a FSM in a text format called the kiss2 format.
> It looks something like this:
> 
> file input.kiss2
> --------------------------------------------start of
> file---------------------------
> .i 2
> .o 2
> .p 8
> .s 4
> 01 s0 s1 11
> 11 so s3 00
> 01 s1 s0 11
> 11 s1 s2 00
> 1- s2 s3 01
> 0- s2 s1 10
> 11 s3 s0 10
> 10 s3 s2 11
> --------------------------------------------end of
> file---------------------------------
> i= # of inputs
> o= # of outputs
> p= # of transitions
> s= # of states
> 01 so s1 11 = this is read as for input 01 and current state s0 the
> output is 11 and next state is s1.
>  '-' means don't care
> 
> 
> Does anyone know a way in which I can convert this to a format such
> that it can be entered into the Xilinx synthesis tool and I can get
> the FSM synthesized for further use my implementation

Are you a software guy?
Do you use Verilog?
Do you use VHDL?
Do you know what a state machine is?
Do you know how the HDL generally maps to hardware?
Do you understand what the file above is communicating?

Answer us [sic] and we can answer you.

Article: 130048
Subject: Actel PA3 with DirectC or SVF, anybody had any success?
From: Antti <Antti.Lukats@googlemail.com>
Date: Thu, 13 Mar 2008 23:14:41 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi

I wonder if anyone had any success using either DirectC 2.2 or SVF
files to program Actel PA3 devices. All my attempts are failing so
far.

1) DirectC 2.2 compiled with VC2005 (adapted to Xilinx Cable III), had
1 time success from 100 attempts to program the part
2) playing SVF or XSVF files with Impact fail very quick, SVF doesnt
even get as far as checking jtag IDCODE
3) custom SVF player also shows weird behaviour

Antti


Article: 130049
Subject: ICMP checksum
From: "life.is.best" <life.is.dreaming@gmail.com>
Date: Fri, 14 Mar 2008 00:23:44 -0700 (PDT)
Links: << >>  << T >>  << A >>
Does anyone know ICMP checksum calicutation by verilog HDL?



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search