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On Mar 27, 10:14=A0am, bertus <b...@joepie.org> wrote: > sarah_s wrote: > > Hi, > > > I have developed a Decoder in verilog and successfully simulated it > > on > > an FPGA. I am using Actel's ProASIC3E proto kit. Simulink has an > > instrument control toolbox which allows one to read and write to the > > pc serial port. I plan to have the encoder, modulation and > > demodulation blocks > > in simulink and want to send the demodulated data to the decoder on > > fpga through > > serial and recieve the output. How can I do this? My design is > > synchronous. It takes 2 bits at every clock cycle which get decoded > > into 1bit. Also, what's the > > output voltage/current on the pc serial port? If the connect on the > > pins directly into one of fpga's input pins on the board.. would I > > fry > > it? (I don't have a serial port on the fpga proto board). Is this > > even > > possible? > > > Thanks for the help, > > Sarah > > Hi you cannot connect the pins of a PC serial port directly to a FPGA. I u= se > a tiny selfmade board with a MAX232 chip which translates the levels to > standard digital signals (in my case an old spartan 2 protoboard). Take a > look at the schematics of spartan3A evaluation boards for other solutions.= > > For the demod data you could use some standard uart cores from internet > (opencores.org orhttp://www.oldcrows.net/~patchell/IpArchive/HdlArchive.ht= ml#Uart_Soft... > ) > Taco- Hide quoted text - > > - Show quoted text - Thanks for the reply. Actually, I have ethernet ports as well on my protoboard. Could I use those for communication? Simulink allows communcation to ethernet ports. Here's my board by the way: http://www.actel.com/products/hardware/devkits_boards/proasic3_starter.aspx SarahArticle: 130601
On Mar 27, 10:14=A0am, bertus <b...@joepie.org> wrote: > sarah_s wrote: > > Hi, > > > I have developed a Decoder in verilog and successfully simulated it > > on > > anFPGA. I am using Actel's ProASIC3E proto kit. Simulink has an > > instrument control toolbox which allows one to read and write to the > > pcserialport. I plan to have the encoder, modulation and > > demodulation blocks > > in simulink and want to send the demodulated data to the decoder on > >fpgathrough > >serialand recieve the output. How can I do this? My design is > > synchronous. It takes 2 bits at every clock cycle which get decoded > > into 1bit. Also, what's the > > output voltage/current on the pcserialport? If the connect on the > > pins directly into one offpga'sinput pins on the board.. would I > > fry > > it? (I don't have aserialporton thefpgaproto board). Is this > > even > > possible? > > > Thanks for the help, > > Sarah > > Hi you cannot connect the pins of a PCserialportdirectly to aFPGA. I use > a tiny selfmade board with a MAX232 chip which translates the levels to > standard digital signals (in my case an old spartan 2 protoboard). Take a > look at the schematics of spartan3A evaluation boards for other solutions.= > > For the demod data you could use some standard uart cores from internet > (opencores.org orhttp://www.oldcrows.net/~patchell/IpArchive/HdlArchive.ht= ml#Uart_Soft... > ) > Taco- Hide quoted text - > > - Show quoted text - Actually on my board which is here: http://www.actel.com/products/hardware/devkits_boards/proasic3_starter.aspx I have 2 ethernet ports. Could I use those to establish data communciation b/w fpga and PC? Simulink allows one to write/read to ethernet port. SarahArticle: 130602
I apologize to anyone who found my post offensive. I was, in fact, making fun of the OP for posting in the wrong newsgroup. I added a non-sequitur that was unbelievable in an attempt to be funny. I stand by my recommendation, however. I believe we must study the past to keep from making the same mistakes in the future. I have visited the Anne Frank House several times, when I have been in Amsterdam to sell video equipment that I built using FPGA's. Alan Nishioka On Mar 26, 3:32 pm, Alan Nishioka <a...@nishioka.com> wrote: > On Mar 26, 3:19 pm, "Ashok Chotai" <as...@xilinx.com> wrote: > > > Hello, > > I am planning to visit Amsterdam and Brussells in July '08 for a week. > > What places you would recommend to see for these two cities? > > Thanks > > Ashok > > In Amsterdam, I would recommend visiting the Anne Frank House, where > she hid during World War II. That is where she taught herself VHDL > and programmed her first FPGA. > > Alan NishiokaArticle: 130603
Hi, I am looking for an FPGA board with preferably a Xilinx FPGA (Spartan 3 or Virtex series) with 500k to 1 million gates capacity. The board should have any or all of the following interfaces. USB 2.0 (preferred) Serial Port Ethernet The board must have a single or dual channel ADC with sampling speed in the range of 10-20 MS/s. ADC resolution should be somwhere around 12-16 bits. In addition to all mentioned above, the board must have 32-64 MBytes of on-board memory (SSRAM is preferred). Any links............... Thanks in advance FarhanArticle: 130604
On Mar 27, 4:57 pm, sarah_s <sarah.stre...@gmail.com> wrote: > On Mar 27, 10:14 am, bertus <b...@joepie.org> wrote: > > > > > sarah_s wrote: > > > Hi, > > > > I have developed a Decoder in verilog and successfully simulated it > > > on > > > anFPGA. I am using Actel's ProASIC3E proto kit. Simulink has an > > > instrument control toolbox which allows one to read and write to the > > > pcserialport. I plan to have the encoder, modulation and > > > demodulation blocks > > > in simulink and want to send the demodulated data to the decoder on > > >fpgathrough > > >serialand recieve the output. How can I do this? My design is > > > synchronous. It takes 2 bits at every clock cycle which get decoded > > > into 1bit. Also, what's the > > > output voltage/current on the pcserialport? If the connect on the > > > pins directly into one offpga'sinput pins on the board.. would I > > > fry > > > it? (I don't have aserialporton thefpgaproto board). Is this > > > even > > > possible? > > > > Thanks for the help, > > > Sarah > > > Hi you cannot connect the pins of a PCserialportdirectly to aFPGA. I use > > a tiny selfmade board with a MAX232 chip which translates the levels to > > standard digital signals (in my case an old spartan 2 protoboard). Take a > > look at the schematics of spartan3A evaluation boards for other solutions. > > > For the demod data you could use some standard uart cores from internet > > (opencores.org orhttp://www.oldcrows.net/~patchell/IpArchive/HdlArchive.html#Uart_Soft... > > ) > > Taco- Hide quoted text - > > > - Show quoted text - > > Actually on my board which is here:http://www.actel.com/products/hardware/devkits_boards/proasic3_starte... > > I have 2 ethernet ports. Could I use those to establish data > communciation b/w fpga and PC? Simulink allows one to write/read to > ethernet port. > > Sarah The webpage says they're "Two CAT5E RJ45 connectors for high-speed LVDS communications", so they're not ethernet ports. The serial route is pretty straightforward. Read up about RS-232 and the MAX232 chip.Article: 130605
Everett M. Greene wrote: > Walter Banks <walter@bytecraft.com> writes: >> "Ron N." wrote: >> >>> What's the smallest instruction set supported by an >>> existing and available C compiler? Is there a C compiler >>> available for any of the tiniest stack machines, or even >>> for an OISC (one instruction set computer)? >> I am not sure what the smallest instruction set that a C >> compiler has been written for. We have written quite a few >> C compilers for processors with unusual instruction sets >> and limited resources. >> >> The key is, >> "Can you write code to do +,~, |,>>,conditional branch on >> z or carry" > > You need XOR for add/subtract so it can be one of the > operations at little extra cost. Some sort of CALL > and RETURN is needed for the processor to be useful. > AND is needed as well. > (a & b) == ~(~a | ~b) (a ^ b) == (a | b) & ~(a & b) Thus you don't need AND or XOR. Similarly, you subtraction. As for CALL and RETURN, you need some way to implement them, but they don't need to be fundamental operations. There are many ways to create them, especially if you have a way to directly read the current PC. Even if you don't have any way to read or store the PC at run-time, it is still possible to simulate CALL and RETURN. Imagine a machine whose only control flow instructions are a direct jump and some sort of conditional. Every time you want to use a "CALL", you are effectively making a note of the return point, doing a jump to the function, then (with the RETURN) doing a jump to the return point. So the compiler needs to collect all the return points in the program, and give each a unique number. The CALL mechanism will stack that number, and the RETURN mechanism will look up that number in a table to get the required return address. If there is no indirect jump instruction, then the RETURN will be a function full of "if (returnNo == x) goto returnX;" statements (or something faster - perhaps a binary search system). The same mechanism can be used for function pointers, and to overcome other architectural limitations such as limited hardware CALL/RETURN stack size, or paging issues.Article: 130606
Nico Coesel wrote: > "MM" <mbmsv@yahoo.com> wrote: > >> Hi all, >> >> I was wondering if there is a good VHDL document generation utility (free or >> not) out there? I stumbled across an article describing HDLDoc by DualSoft, >> which seemed promising, but it seems that that company ceased to exist... I >> am looking for something that would be more than just a comments >> extractor... > > Anyone using such a utility on my watch is fired immediately. Proper > documentation describes the idea behind an implementation. Tools like > doxygen produce nice looking documents, but the contents of the > documents are useless because the idea behind it all is missing. > When used to its full extent, doxygen allows you to produce all sorts of documents - not just syntax-highlighted source code printouts. You can have files that are used purely for documentation, and include all the usual features of technical documents (structure layout, images, graphs, cross-references, company logos, or whatever) - it's not really any different than using a tool such as LaTeX for your documentation. You can cross-link to source code as and when required, of course. If you just mean that running a typical loosely commented set of source code files through doxygen and calling it "the project's complete documentation" is a fireable offence, then your comments make much more sense.Article: 130607
Hi, I am going through a xilinx app note. The basic CAM that is shown is a 32X9 capacity. The total memory capacity used up to implement this is 16kb. I am wondering if the idea is to generate just a match or no_match then just a 512 bit single bit memory array would do the job. Where the array is accessed (both for configure and search) using the 9-bit data instead of address and if the resultant data is 1 then there is a match. Am I missing something? Maybe the application note is more suitable when the size of match data increases to 20 bits or more. Probably it is useful when just more than match or no_match is required (probably a vector output instead of just match or no_match) I am just curious. RegardsArticle: 130608
Hi We are currently looking for switch solution based on PCI express to connect several Xilinx FPGA boards together. It should have compatible connector to some current FPGA Boards (e.g Using SMA or SATA to XUPV2P Board or PCI express to other boards.) We are looking for development kit based on such a switch. Does anyone know of such a product? Thanks Best Regards shakithArticle: 130609
i need some detailed information about the Marmaduke board. JavaBotics website doesn't have enough information on some of the components. and i also wanted to know if the board is for sale, or not?Article: 130610
Ladies (if any actually read comp.lang.vhdl
or comp.arch.fpga) and gentlemen,
You may have been wondering why I have not
been posting much to Usenet and SystemC.org
since September 2007.
In January 2006 I became a Ph.D. student in
the largest University of Pisa but I quit
in September 2007 (details follow). I have
unsuccessfully tried to apply for a number
of Ph.D. scholarships and jobs to replace my
sabotaged attempt at a Ph.D. in Pisa, and I
do not have much money remaining so now I
announce my woe here in the hope that one
of you might help me.
I had the misfortune to unintentionally but
quite clearly empirically disprove a published
theory of my main tutor's. I was discouraged to
submit a paper for publication which would highlight
points similar to those below, and I was too afraid to
continue with writing the paper in my spare time
before I quit lest that could still be used as a
sufficient excuse to expell me. I was also warned
that if I would not quit, then my empty refereed
publication record would be used as a reason to
fail me in the second annual review. I quit in
September 2007.
In addition to the problems below,
Prof. Luca Fanucci forbade me from pointing out
in my presentations that high-level SystemC(R)
modeling did not prove to be competitive with
Verilog.
Please feel free to discuss these points on
Usenet for yourselves, but if you have
anything to say to me (hopefully an offer,
but even advice would be welcome) please
reply to me directly by writing to
Colin Paul Gloster,
Via Tosco Romagnola 2461,
Titignano,
56023 Cascina (PI),
Italy
or by emailing to Colin_Paul_Gloster@ACM.org
but please bear in mind that my Internet
access is currently chiefly restricted to
approximately three gratis hours in a local
library.
Yours faithfully,
Colin Paul Gloster
Table of Contents
Introduction to C++ Issues in Pisa
An example of where similar, unrelated objects should be refactored into a single
hierarchy on Sourceforge
Lack of effective inheritance on Sourceforge
Unnecessary case branches on Sourceforge
A number of bad practices on Sourceforge
Miscellaneous C++ Issues in Pisa
VHDL Issues in Pisa
Bibliography
Introduction to C++ Issues in Pisa
A non disclosure agreement between myself; my former tutor, Prof. Luca Fanucci,
and his partner, STMicroelectronics, prevents me from mentioning a number of items
for a number of years. Fortunately, I am legally at liberty to highlight many
problems which I detected in published source code which was written by
STMicroelectronics and is available for gratis on the Internet. My project in Pisa
involved using this source code. I had offered to help with that source code, but
despite the large list of flaws which I uncovered, my offer was ignored. It is
trivial to check my list (below) in which I give exact file names and line
numbers. I was not permitted to write a paper concerning these issues. What I
accidentally uncovered irrefutably contradicted published papers by my tutor of
the time (the [Fanucci] entry in the bibliography) and published papers by his
partner, STMicroelectronics (the [OCCN2] entry in the bibliography). This tragic
incident is another case highlighting that the IEEE allows untrue papers. It is
not a sin to not be the best programmer in the World, but they incorrectly claimed
in papers that they are highly competent at writing source code in C++.
An example of where similar, unrelated objects should be refactored into a single
hierarchy on Sourceforge
The reader may wish to download the file occn_lib_2.0.1.beta.tar.gz from
https://sourceforge.net/project/showfiles.php?group_id=74058
and to consult the files occn_lib_2.0.1.beta/include/utils/CQueueObject.n and
occn_lib_2.0.1.beta/include/utils/CQueuePtrObjectEv.n therein for what is
discussed here.
A constructor for a derived class (which e.g. CQueuePtrObjectEv could become in a
new version) must call a constructor for the base class (which e.g. CQueueObject
could become in a new version). Three of the four lines from a constructor of
CQueueObject are lexically copied in a constructor of CQueuePtrObjectEv, and the
counterpart to the remaining line from CQueueObject differs by simply having an
array of type T* instead of of type T (but as templates are used everywhere, a
pointer to a type is actually a type so perhaps CQueuePtrObjectEv should be
replaced by a future class which we could call "CQueueObjectEv" or even better
"CQueueEv"). Somewhat similarly, the bodies of the destructors are lexically
identical; the remove() methods contain identical semantics but differing
quantities of braces, but even worse they return an element without expelling it
from the agenda; the method add() of CQueuePtrObjectEv performs identical,
lexically copied steps as in the method add() of CQueueObject and after those
steps has some additional steps which would be more maintainably added as in "When
a base-class member function is overridden in a derived class, it is common to
have the derived-class version call the base-class version and do some additional
work" as written in a C++ book (the entry [Deitel and Deitel] in the
bibliography); the get_length() methods are lexically identical and each of them
contains two off by one errors; the methods is_not_empty() are lexically
identical; and the methods is_not_full() are lexically identical.
diff include/utils/CQueueObject.n include/utils/CQueuePtrObjectEv.n
32,33c32,33
< // File: CQueueObject.n
< // Created: Fri Jun 14 09:36:43 2002
---
> // File: CQueuePtrObjEv.n
> // Created: Tue Jul 2 14:56:24 2002
44c44
< CQueueObject<T>::CQueueObject(N_uint _size)
---
> CQueuePtrObjectEv<T>::CQueuePtrObjectEv(N_uint _size, sc_event& _ev)
48c48
< data (new (T) [size]) ,
---
> data (new (T*) [size]) ,
50,51c50,56
< tail(0)
< {}
---
> tail(0),
> wait(false),
> trig_ev(_ev),
> delay(0)
> {
>
> }
56c61
< CQueueObject<T>::~CQueueObject()
---
> CQueuePtrObjectEv<T>::~CQueuePtrObjectEv()
66c71
< void CQueueObject<T>::add(T item)
---
> void CQueuePtrObjectEv<T>::add(T* ptr)
71d75
< {
73c77
< }
---
>
75c79,85
< data[tail]=item;
---
>
> data[tail]=ptr;
> if (wait)
> {
> trig_ev.notify(delay,SC_SEC);
> wait=false;
> }
81c91
< T CQueueObject<T>::remove()
---
> T* CQueuePtrObjectEv<T>::remove()
88d97
< {
90d98
< }
97c105,106
< T CQueueObject<T>::check()
---
> inline
> N_uint CQueuePtrObjectEv<T>::get_length() const
101,106c110
< N_uint tmp_head=head+1;
< if (tmp_head==size)
< {
< tmp_head=0;
< }
< return data[tmp_head];
---
> return (tail >= head) ? tail -head : tail - head + size;
113c117
< N_uint CQueueObject<T>::get_length() const
---
> N_uint CQueuePtrObjectEv<T>::is_not_empty() const
117c121
< return (tail >= head) ? tail -head : tail - head + size;
---
> return (tail!=head);
124c128
< N_uint CQueueObject<T>::is_not_empty() const
---
> N_uint CQueuePtrObjectEv<T>::is_not_full() const
128c132,134
< return (tail!=head);
---
> const N_uint tmp= tail+1;
> return (tmp==size) ? (0!=head) : (tmp!=head);
>
135c141
< N_uint CQueueObject<T>::is_not_full() const
---
> void CQueuePtrObjectEv<T>::trigger()
139,141c145,156
< const N_uint tmp= tail+1;
< return (tmp==size) ? (0!=head) : (tmp!=head);
<
---
> wait=true;
> }
>
> // }}}
>
> template<class T>
> inline
> void CQueuePtrObjectEv<T>::set_delay(double _ref)
> // {{{
>
> {
> delay=_ref;
Lack of effective inheritance on Sourceforge
In occn_lib_2.0.1.beta/include/channels/BusBaseChannel.n from STMicroelectronics,
both MasterIf<class,class> and SlaveIf<class,class> are subclasses of
Msgbox<class,class> and their respective set_index() methods are almost identical
but were clearly implemented using lexical copying. This is in contrast to the
claim in [OCCN1]: "The On-Chip Communication Network (OCCN) proposes an efficient,
open-source research and development framework for the specification, modeling and
simulation of on-chip communication architectures. OCCN increases the productivity
of developing new models for on-chip communication architectures through the
definition of a universal Application Programming Interface (API) and an object-
oriented C++ library built on top of SystemC. [..]
This environment provides several important on-chip network modeling features.
* Object-oriented design concepts, fully exploiting advantages of this software
development paradigm.
[..]" The following claim in [OCCN2] is similarly nonsensical: "OCCN focuses on
NoC modeling by providing a flexible, state-of-the-art, C++-based framework
consisting of an open-source, GNU GPL library, built on top of SystemC. OCCN
design methodology offers unique features, such as
* object-oriented design concepts," and is reminiscent of a comparison in Embedded
Systems Conference, 1990 to teenage sex and object oriented programming similar to
"The state of the art of Software Architecture is like teenage sex: it's on every-
body's mind all the time, everyone talks about it all the time (but they don't
really know what they are talking about), everyone thinks everyone else is doing
it, the few that are doing it: 1) are doing it poorly, 2) think it will be better
next time, and 3) are not practising it safely" reproduced in e.g. [Crocker].
Conceited delusions of grandeur such as those expressed in [OCCN1,OCCN2] might be
attributed to electronic engineers having a basis for arrogance more than a decade
behind realtime embedded programmers' and justifiably not knowing enough about
software development, but one of the coauthors of [OCCN1] and [OCCN2] owns a
company which allegedly[ISD1]: "Integrated Systems Development S.A. (ISD) is a
company established in 1998, active in the domain of Integrated Systems
(IS) of Guaranteed Quality and Performance. It is an R&D organization [..]"
and allegedly[ISD2}:"The ISD software group is dedicated to efficient and retance_id < 1000000)
168 sprintf(tmp_str, "f%u_favg_", instance_id);
169 else if (instance_id >= 1000000) {
170 fprintf(stderr, "way too many filenames \n");
171 OCCN_error_exit("error in stats");
172 }
173 strcat(string_gen_tbl[BaseStat::F_FREQ_STAT_AVG], tmp_str);
174
175 ptr = string_gen_tbl[BaseStat::F_FREQ_STAT_AVG];
176 break;
177
178 case BaseStat::FREQ_STAT_CURR:
179 string_gen_tbl[BaseStat::F_FREQ_STAT_CURR] = new
char[max_string_size];
180 if (string_gen_tbl == NULL)
181 {
182 fprintf(stderr, "Statistics Error: new string_gen_tbl (in
BaseStat::activate_stats) failed: retry with smaller max_string_size\n");
183 OCCN_error_exit("error in stats");
184 }
185 strcpy(string_gen_tbl[BaseStat::F_FREQ_STAT_CURR],
"./stat/");
186 //strcpy(string_gen_tbl[BaseStat::F_FREQ_STAT_CURR]+7,
"fn_fcur_");
187 if (instance_id < 10)
188 sprintf(tmp_str, "f00000%u_fcur_", instance_id);
189 else if (instance_id < 100)
190 sprintf(tmp_str, "f0000%u_fcur_", instance_id);
191 else if (instance_id < 1000)
192 sprintf(tmp_str, "f000%u_fcur_", instance_id);
193 else if (instance_id < 10000)
194 sprintf(tmp_str, "f00%u_fcur_", instance_id);
195 else if (instance_id < 100000)
196 sprintf(tmp_str, "f0%u_fcur_", instance_id);
197 else if (instance_id < 1000000)
198 sprintf(tmp_str, "f%u_fcur_", instance_id);
199 else if (instance_id >= 1000000) {
200 fprintf(stderr, "way too many filenames \n");
201 OCCN_error_exit("error in stats");
202 }
203 strcat(string_gen_tbl[BaseStat::F_FREQ_STAT_CURR], tmp_str);
204
205 ptr = string_gen_tbl[BaseStat::F_FREQ_STAT_CURR];
206 break;
A number of bad practices on Sourceforge
>From occn_lib_2.0.1.beta/include/interfaces/Pdu.n:
137 template <typename H, typename BU, int size>
138 int Pdu<H,BU,size>::operator==(const Pdu<H,BU,size>& right) const
139 // {{{
140
141 {
142 e_last_addr<slave_first_addr)
143 {
144 OCCN_error_exit("Address ranges isn't correct (end address <
start address");
145 }
146 return true;
147 }
148
149 // }}}
In occn_lib_2.0.1.beta.tar.gz from
HTTPS://SourceForge.net/project/showfiles.php?group_id=74058, in the file
include/interfaces/Port.n, the following is inexcusable:
template<class WPdu, class RPdu>
RPdu* SlavePort<WPdu,RPdu>::receive(sc_time& time_out, bool& received)
// {{{
{
if ( (*this)->wait_read_authorization(time_out)==1 )
{
received = true;
}
else
{
received = false;
(*this)->cancel_receiving();
}
return (RPdu*)((*this)->get_read_pdu_ptr());
// maybe not valid but need to send back something !
}
// }}}
VHDL Issues in Pisa
I had applied to Pisa in September 2005 when I was living in Ireland, having just
returned from my Swedish internship in the Netherlands. I was in contact by
telephone and email with Prof. Luca Fanucci who was in Italy. At home, in a
different country from university, I had a subscription to the ACM Digital
Library, but instead Prof. Fanucci's publications tend to be on IEEEXplore for
which I did not have a subscription. He did email me a publication and I was able
to download an abstract of his from an old MAPLD conference. We established that
VHDL would be something I would want to be seriously involved in if I was to
secure a scholarship in Pisa. After I secured the scholarship and moved to Italy,
he mentioned C++ to me for the first time and he revealed his agenda against VHDL.
However, in time it became clear that he was very good at neither VHDL nor C++.
For example in his book of lecture notes entitled "Digital Sistems Design Using
VHDL" (he blamed the misspelling of Systems on the publisher) published by
Servizio Editoriale Universitario di Pisa,
Via Curtatone e Montanara 6,
56126 Pisa,
Italy,
telephone/fax +39 050 540120
dated May 2002, he went against best practice which was standardised in the 1990's
by using a clock edge synchronization coding style which is well-known by experts
to result in mismatches between simulation and synthesis. He did this on Slides
3.19; 4.12; 4.24 and 4.27. You can check with
http://groups.google.com
that I already knew how to do this in a less error-prone manner before I moved to
Italy. He has mistakes on Slides 2.14; 4.5; 4.16 and 4.20 (and also misspellings
on other slides).
I do not know everything concerning VHDL. I have entirely through my own fault
unintentionally overlooked things. I admit that. I am not perfect. One prominent
example is that though I had looked at the relevant part of the VHDL standards
concerning implicit initializations, I had not noticed this feature of VHDL so
when I discovered that one of our VHDL tools performs implicit initializations I
was very displeased with it and I deplored this feature to Prof. Luca Fanucci. He
ignored me, as usual, so I eventually proposed as part of the VHDL standardization
process to have implicit initializations illegal. Someone unaffiliated with the largest
University of Pisa explained the legality and rationale to me on the newsgroup
news:comp.lang.vhdl and I retracted my proposal. I felt like a fool and it became
clear that no one in the University of Pisa except for myself was interested
enough in VHDL (our most important language (we never even had a C++ compiler and
almost everyone else in the group in Pisa used only VHDL for the project)) to
monitor the standardization process and that no one in the University of Pisa was
an expert of VHDL and that no one in the University of Pisa cared enough about me
to support me. This inaction of Prof. Luca Fanucci's was extremely inappropiate.
Please see my proposal and its retraction on
https://bugzilla.mentor.com/show_bug.cgi?id=120
Luca Fanucci is fit to be a professor of none of VHDL; C++; C; and SystemC(R)
intellectual properties.
Also, when I was applying to Pisa, Luca Fanucci showed me a public webpage of
STMicroelectronics's concerning the project which he initially assigned me to.
After I arrived in Italy and saw the true algorithm, I learnt that the webpage was
misleading.
Bibliography
[Crocker] Will Tracz, Quote of the Day attributed to Ron Crocker, International
Conference on Software Engineering 1995 "Window On the World", Volume 1, Number 1
[Deitel and Deitel] Deitel and Deitel; "C++: How to Program", third edition,
Prentice Hall, 2001, Section 9.6 Overriding Base-Class Members in a Derived Class
and 9.9 Using Constructors and Destructors in Derived Classes
[Fanucci] Armaroli; Coppola; Diaz Nava; Fanucci, "High Level Modeling and
Simulation of a VDSL Modem in SystemC 2.0 - IPsim", "Proceedings of The 3rd IEEE
International Workshop on System-on-Chip for Real-Time Applications", 2003
[Grammatikakis] WWW.CS.TEICrete.Gr/english/showdetails.asp?id=12
[ISD1] WWW.ISD.Gr/index.htm#top11
[ISD2] WWW.ISD.Gr/index.htm#top23
[OCCN1] Grammatikakis, HTTP://OCCN.Sourceforge.net/coverpg.html, February 2005
[OCCN2] Marcello Coppola, Stephane Curaba, Miltos D. Grammatikakis, Giuseppe
Maruccia and Francesco Papariello, "OCCN: A Network-On-Chip Modeling and
Simulation Framework", Design for Automation and Test in Europe 2004 conference
[structured programming] Leonard H. Weiner, "The Roots of Structured Programming",
"ACM SIGCSE Bulletin", February 1978
Article: 130611Student discovers that real world code isn't quite as perfect as they were taught it would be in university. Shocker!Article: 130612
Colin, TLDR, sorry. However, could I make the comment that if you're trying to court offers of employment or a placement, slagging off your previous employer on a public forum might not be the best way attract future ones? Good luck, Syms.Article: 130613
Hi,
I 'm learning to use microblaze (microblaze, EDK 9.1 sp2).
I try to use the Send function of uartlite.
Please, find below my c code.
the result of this code (with hyperterminal) is :
-- Entering main() --
nXUartLite_Send
-- status true--
-- status true--
-- XUartLite_SendByte --
e
-- Exiting main() --
I never received the 'D' char (byte_buf = 0x44), and val.
Is someone could hep me.
thanks in advance
bhb.
----------------------------------------------------------------------------
-----------------------------------
#include "xparameters.h"
#include "stdio.h"
#include "xuartlite_l.h"
#include "xuartlite.h"
#include "xstatus.h"
//====================================================
void STATUS_CHECK(Status) \
{ \
if (Status != XST_SUCCESS) \
{
print("\r\n -- status bad--\r\n");
return Status; \
}
else
{
print("\r\n -- status true--\r\n");
return Status; \
}
}
//====================================================
int main (void) {
Xuint8 byte_buf = 0x44;
XUartLite UartLite;
XStatus Status;
unsigned int val;
print("\r\n -- Entering main() --\r\n");
print("\r\nXUartLite_Send \r\n");
Status = XUartLite_Initialize(&UartLite, XPAR_RS232_UART_1_BASEADDR);
STATUS_CHECK(Status);
Status = XUartLite_SelfTest(&UartLite);
STATUS_CHECK(Status);
XUartLite_ResetFifos(&UartLite);
val = XUartLite_Send(&UartLite, &byte_buf, 1);
print(val);
print("\r\n -- XUartLite_SendByte --\r\n");
XUartLite_SendByte(XPAR_RS232_UART_1_BASEADDR, 'e');
print("\r\n -- Exiting main() --\r\n");
return 0;
}
Article: 130614Hi, I installed ISE 10.1 the other day and just tried it out for the first time this morning. I run my synthesis jobs on a Linux x86_64 machine and use home-made make scripts to manage the build process. I noticed that my make process completed too quickly, but that XST (the first part of the build pipeline) was still running in the background. Is there some reason that XST pushes itself into the background now? Whatever the reason for this, it appears that I'll have to update my Makefiles to stop and wait for XST before proceeding with the rest of the build pipeline. Nuisance. Thanks for any insight into this. EricArticle: 130615
On Mar 28, 9:08 am, emeb <ebromba...@gmail.com> wrote: > Hi, > > I installed ISE 10.1 the other day and just tried it out for the first > time this morning. I run my synthesis jobs on a Linux x86_64 machine > and use home-made make scripts to manage the build process. I noticed > that my make process completed too quickly, but that XST (the first > part of the build pipeline) was still running in the background. Is > there some reason that XST pushes itself into the background now? > > Whatever the reason for this, it appears that I'll have to update my > Makefiles to stop and wait for XST before proceeding with the rest of > the build pipeline. Nuisance. > > Thanks for any insight into this. BZZT - ignore this. I was running the Make job in a different shell and everything seems to be working fine. Eric (hangs head in shame, shuffles back into shadows)Article: 130616
On Fri, 28 Mar 2008 02:23:43 -0700 (PDT), Sharan <sharan.basappa@gmail.com> wrote: >Hi, > >I am going through a xilinx app note. The basic CAM that is shown is a >32X9 capacity. The total memory capacity used up to implement this is >16kb. OK, that makes sense. 9-bit data means 512 different data values. For each of those data values you store a 32-bit word, with each bit of the word specifying whether that data word is to be found in one of the 32 locations. Expensive, but *very* fast. >I am wondering if the idea is to generate just a match or >no_match then just a 512 bit single bit memory array would do the job. OK. Let's suppose you do that, and (say) write the value 0 to some location in the CAM. At the same time you write 1 to "match" entry 0, to say that a 0 value is present somewhere. Now let's write 0 to a *second* location. What do we do now? Oh yes, write '1' to match entry 0. Now let's change the second location's data from 0 to something else. We read the location first, discover its old contents were 0, so we go to match location 0 and .... oops, we clear it to show that there's no longer a match.... but we're wrong, because there *is* still a match, at the first location that had 0 written to it. I don't think there is any way to fix this if you have only one match bit per data value - unless you somehow have a guarantee that data values in the CAM are unique. You could get away with each match location containing a COUNT of the number of entries holding that data value; in that case you would need only 6 bits per location, not 32. But that would still leave you with a different problem: if you discover that there is a match, you still don't know *where* that match is. In all applications of CAM that I've come across, that where-is-it information is an essential part of what you're trying to do. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 130617
Mike Treseler <mike_treseler@comcast.net> wrote: >Nico Coesel wrote: > >> Anyone using such a utility on my watch is fired immediately. Proper >> documentation describes the idea behind an implementation. Tools like >> doxygen produce nice looking documents, but the contents of the >> documents are useless because the idea behind it all is missing. > >I like to demonstrate this "idea behind it all" in >working and well-commented testbench procedures. >It is a rare exception when anyone other than the >developers care about this level of detail. The idea behind a design is where it all starts. Why is the design the way it is? Answers to these questions are required to make meaningfull extensions to a design which don't break other parts. In practise a simple block diagram which shows how the information flows through the different blocks (something you'll never ever get out of doxygen et al) says way more than a doxygen print-out. Anyone can pull a piece of source through doxygen but a good IDE (like Eclipse) provides the same information real-time. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 130618
"Ashok Chotai" <ashok@xilinx.com> wrote: >Hello, >I am planning to visit Amsterdam and Brussells in July '08 for a week. >What places you would recommend to see for these two cities? Well, in Amsterdam you have the red-light district which is a must-see. You won't find anything like it anywhere in the world. Before it is evening you can go to the Van Gogh Museum, the Rijksmuseum (which has the 'Nachtwacht' by Rembrandt on display), take a boat tour through the canals, visit the Anne Frank house if you want to lose your appetite, shop around, have dinner in an Italian restaurant near the 'Leidseplein', look at the street artists. Stay away from restaurants near the Dam square / Damrak. You could also visit Marken or Voldendam for more souvenirs and fish. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 130619
what does the following code do output <= input[x*(y)-1 -: y]; I dont understand -: . What is this. I have seen [x:y], never came across[x -: y] Please helpArticle: 130620
Andy Botterill <andy@plymouth2.demon.co.uk> writes: > Everett M. Greene wrote: > > Walter Banks <walter@bytecraft.com> writes: > > >>be done. A surprising number of the processors 20 years > >>ago missed some of the logic operators and > >>shifts limited to rotates. > > > > ^^^^^^^^^^^^^^^^^^^^^^^^^ > > as with ARM?T > The ARM can do logical, arithmetic abd rorates. Andy I was just taking a shot at the silly rotation of one of the operands that can be done with (nearly) every instruction.Article: 130621
David Brown <david@westcontrol.removethisbit.com> writes: > Everett M. Greene wrote: > > Walter Banks <walter@bytecraft.com> writes: > >> "Ron N." wrote: > >> > >>> What's the smallest instruction set supported by an > >>> existing and available C compiler? Is there a C compiler > >>> available for any of the tiniest stack machines, or even > >>> for an OISC (one instruction set computer)? > >> I am not sure what the smallest instruction set that a C > >> compiler has been written for. We have written quite a few > >> C compilers for processors with unusual instruction sets > >> and limited resources. > >> > >> The key is, > >> "Can you write code to do +,~, |,>>,conditional branch on > >> z or carry" > > > > You need XOR for add/subtract so it can be one of the > > operations at little extra cost. Some sort of CALL > > and RETURN is needed for the processor to be useful. > > AND is needed as well. > > > > (a & b) == ~(~a | ~b) > (a ^ b) == (a | b) & ~(a & b) > > Thus you don't need AND or XOR. Similarly, you subtraction. But you haven't produced addition/subtraction yet. The first term of adders/subtractors is a ^ b. If you gate that output to rest of the world, you have XOR with no further fuss. NOT is available via a ^ 1s. > As for CALL and RETURN, you need some way to implement them, but they > don't need to be fundamental operations. There are many ways to create > them, especially if you have a way to directly read the current PC. > Even if you don't have any way to read or store the PC at run-time, it > is still possible to simulate CALL and RETURN. Imagine a machine whose > only control flow instructions are a direct jump and some sort of > conditional. Every time you want to use a "CALL", you are effectively > making a note of the return point, doing a jump to the function, then > (with the RETURN) doing a jump to the return point. So the compiler > needs to collect all the return points in the program, and give each a > unique number. The CALL mechanism will stack that number, and the > RETURN mechanism will look up that number in a table to get the required > return address. If there is no indirect jump instruction, then the > RETURN will be a function full of "if (returnNo == x) goto returnX;" > statements (or something faster - perhaps a binary search system). The > same mechanism can be used for function pointers, and to overcome other > architectural limitations such as limited hardware CALL/RETURN stack > size, or paging issues. CALL/RETURN can be done in some very crude ways. The method used is a matter of practicality and usefulness. Anything computable can be done with a Turing machine but it isn't very practical.Article: 130622
On Fri, 28 Mar 2008 11:14:23 -0700 (PDT), FPGA <FPGA.unknown@gmail.com> wrote: >what does the following code do >output <= input[x*(y)-1 -: y]; That's called an indexed part select. The first expression signifies base and the second expression signifies width. It the sign is + it's an ascending select if it's negative it's a descending select. Your example is equivalent to input[x*(y)-1: x*(y)-y] ie you need to subtract (y-1) from the base to get the lower index.Article: 130623
Congrats to Xilinx on the recent release of ISE 10.1, and thanks for simultaneously releasing WebPack along with ISE Foundation. But... it appears the hoops necessary to get the 32-bit webpack working under 64-bit linux (in this case, 64-bit ubuntu 7.10) have changed... I wanted to share what I found so that others might have similar success: The real challenge is, once you've untarred the webpack tar, you need to run bin/lin/setup Now, for me this just returned me to the command line, but running strace bin/lin/setup showed that it was searching for, and failing to find, a libuuid.so. Now, ubuntu packages this lib (but not a 32-bit version of this lib) so I had to download a 32-bit deb of libuuid (http://ubuntuforums.org/ showthread.php?t=203459 following these directions somewhat), extract the archive with "ar x debname", untar the resulting data file, find the libuuid.* files, and -then- copy them into the webpack lib/lin directory. After this, the gui and everything else ran smoothly (still waiting for the install to complete to make sure xst and all that works). (I understand that xilinx appears to be using the 64-bit capability to price discriminate, but at the same time if you can afford the $$$ xilinx toolchain you can probably also afford a $800 32-bit computer to run it on, whereas a lab like ours (with only 64-bit machines) really relies on the free webpack). Again, I hope this helps people in a similar situation to me. Now to see if ISE 10.1 can help me shrink my design by the needed 2% to get it to fit!Article: 130624
I also had to finally copy the libuuid.so* files to my $XILINX/ISE/lib/ lin/ directory, but now xst appears to be working fine (knock on wood!)
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