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On Apr 3, 8:29=A0pm, Pablo <pbantu...@gmail.com> wrote: > OK, i have just used the secondary ports from the opb_mdm to connect > the icon core. Now I am trying to debug with the Chipscope Analyzers, > but I get only one value. That is, I have included a clock port, so it > sould appears as 101010101 and so on. The real value is 1111111111. It > seems like system only does a unique sample but it shows 512 samples. > Does anyone have the same result?. What must I configure to show a > clock signal up and down? > > Again, my best regards You are sampling a signal with the same signal as a clock, Isn't it ? /MHArticle: 130876
On Apr 4, 9:20 am, Moazzam <moazzamhuss...@gmail.com> wrote: > On Apr 3, 8:29 pm, Pablo <pbantu...@gmail.com> wrote: > > > OK, i have just used the secondary ports from the opb_mdm to connect > > the icon core. Now I am trying to debug with the Chipscope Analyzers, > > but I get only one value. That is, I have included a clock port, so it > > sould appears as 101010101 and so on. The real value is 1111111111. It > > seems like system only does a unique sample but it shows 512 samples. > > Does anyone have the same result?. What must I configure to show a > > clock signal up and down? > > > Again, my best regards > > You are sampling a signal with the same signal as a clock, Isn't it ? > /MH Yes, it is. I have already solved it. Sorry for this stupid question.Article: 130877
I hade to use the -skip_syncword_check option on xspi so it could download the bitfile to the spi flash. But is is safe?Article: 130878
On 3 Kwi, 16:05, Jens Hagemeyer <je...@hni.upb.de> wrote: > On 3 Apr., 15:02, g.drozdzow...@gmail.com wrote: > > Hi g.d. > > looks like you're triggering a "SelectMap abort sequence" when > switching from read to write. Consult the User Guide on how to avoid > this, i guess your CS handling is not correct. > Thanks guys, I think, I got it under control. The thing was the Virtex-5 is bit swaped within the byte, and another thing was misleadding drawing in Xilinx user "guide" (i.e. Figure 7-2: SelectMAP Status Register Read - UG191 Virtex-5 FPGA Configuration User Guide available at Xilinx site), while I was deperate enough to double cclk rate per single data word. Now it responds, and the story begins ;-) -- Cheers, [g.d.]Article: 130879
Maybe you should give us some information on how to proceed if we are stuck with exeed devices with significant value, and want to sell them.Article: 130880
On Apr 4, 3:41=A0am, "MM" <mb...@yahoo.com> wrote: > "John McCaskill" <jhmccask...@gmail.com> wrote in message > > news:c4d146c4-2719-4817-b11c-750da7e80640@s50g2000hsb.googlegroups.com... > > >Since you mention that you are loading the bitfile over the PCI bus, I > >am assuming that the FPGA is on the PCI card, as opposed to a daugher > >card. Is this correct? > > >If so, you could use the PCI configuration space to tell the cards > >appart. If you also know what board the bitfile is for, then the drive > >could check to make sure that the board and bitfile versions match, > >and refuse to load the bit file if it does not. > > I was just about to suggest the same solution. PCI spec requires every typ= e > of board to have unique Vendor, and device IDs, as well as there are > SubSystem IDs. Now, this is all great unless the OP is implementing the PC= I > bridge in the same FPGA... Ooops... > > /Mikhail Thanks everyone for your replies. I think I need to add some more info here. Infact, I am not trying to secure my FPGA design or bitstream here. I am trying to prohibit generation of multiple copies of the same system. For example, assume that I have developed a system which comprises of a PC and a PCI based FPGA board which is mounted on the PCI slot of the same PC. The PCI based FPGA board is commercially availble from a vendor. The host application that runs on the PC programs the FPGA on application startup. If I deliver this system to a customer, it is quite possible that the Hard Disk image of the actual system is created, the same PCI based FPGA board is purchased from the same vendor and exactly the same PC is purchased. When all these things are hooked up in the PC...........bingo..........we have another system ready. In this scenario, I dont see the device ID or vendor ID stuff is of any use because these IDs would be the same for the same FPGA board. I dont have any non-volatile memory on the FPGA board where I can write my own sequnce which can be read out and verified by the application at startup. Any thoughts............. FarhanArticle: 130881
On 4 Apr., 12:05, maverick <sheikh.m.far...@gmail.com> wrote: > On Apr 4, 3:41 am, "MM" <mb...@yahoo.com> wrote: > > > > > "John McCaskill" <jhmccask...@gmail.com> wrote in message > > >news:c4d146c4-2719-4817-b11c-750da7e80640@s50g2000hsb.googlegroups.com... > > > >Since you mention that you are loading the bitfile over the PCI bus, I > > >am assuming that the FPGA is on the PCI card, as opposed to a daugher > > >card. Is this correct? > > > >If so, you could use the PCI configuration space to tell the cards > > >appart. If you also know what board the bitfile is for, then the drive > > >could check to make sure that the board and bitfile versions match, > > >and refuse to load the bit file if it does not. > > > I was just about to suggest the same solution. PCI spec requires every type > > of board to have unique Vendor, and device IDs, as well as there are > > SubSystem IDs. Now, this is all great unless the OP is implementing the PCI > > bridge in the same FPGA... Ooops... > > > /Mikhail > > Thanks everyone for your replies. I think I need to add some more info > here. Infact, I am not trying to secure my FPGA design or bitstream > here. I am trying to prohibit generation of multiple copies of the > same system. For example, assume that I have developed a system which > comprises of a PC and a PCI based FPGA board which is mounted on the > PCI slot of the same PC. The PCI based FPGA board is commercially > availble from a vendor. The host application that runs on the PC > programs the FPGA on application startup. If I deliver this system to > a customer, it is quite possible that the Hard Disk image of the > actual system is created, the same PCI based FPGA board is purchased > from the same vendor and exactly the same PC is purchased. When all > these things are hooked up in the PC...........bingo..........we have > another system ready. In this scenario, I dont see the device ID or > vendor ID stuff is of any use because these IDs would be the same for > the same FPGA board. I dont have any non-volatile memory on the FPGA > board where I can write my own sequnce which can be read out and > verified by the application at startup. > > Any thoughts............. > > Farhan NO. if you look at your spec, you see yourself there is no option. if you CAN NOT customize (nonvolatile setting!) anything on your PCI board then you can not use it as software dongle . some FPGA's have serial numbers, but yours does not. so you need to add something to your system that is used to protect it AnttiArticle: 130882
On 4 Apr., 12:15, Antti <Antti.Luk...@googlemail.com> wrote: > On 4 Apr., 12:05, maverick <sheikh.m.far...@gmail.com> wrote: > > > > > On Apr 4, 3:41 am, "MM" <mb...@yahoo.com> wrote: > > > > "John McCaskill" <jhmccask...@gmail.com> wrote in message > > > >news:c4d146c4-2719-4817-b11c-750da7e80640@s50g2000hsb.googlegroups.com... > > > > >Since you mention that you are loading the bitfile over the PCI bus, I > > > >am assuming that the FPGA is on the PCI card, as opposed to a daugher > > > >card. Is this correct? > > > > >If so, you could use the PCI configuration space to tell the cards > > > >appart. If you also know what board the bitfile is for, then the drive > > > >could check to make sure that the board and bitfile versions match, > > > >and refuse to load the bit file if it does not. > > > > I was just about to suggest the same solution. PCI spec requires every type > > > of board to have unique Vendor, and device IDs, as well as there are > > > SubSystem IDs. Now, this is all great unless the OP is implementing the PCI > > > bridge in the same FPGA... Ooops... > > > > /Mikhail > > > Thanks everyone for your replies. I think I need to add some more info > > here. Infact, I am not trying to secure my FPGA design or bitstream > > here. I am trying to prohibit generation of multiple copies of the > > same system. For example, assume that I have developed a system which > > comprises of a PC and a PCI based FPGA board which is mounted on the > > PCI slot of the same PC. The PCI based FPGA board is commercially > > availble from a vendor. The host application that runs on the PC > > programs the FPGA on application startup. If I deliver this system to > > a customer, it is quite possible that the Hard Disk image of the > > actual system is created, the same PCI based FPGA board is purchased > > from the same vendor and exactly the same PC is purchased. When all > > these things are hooked up in the PC...........bingo..........we have > > another system ready. In this scenario, I dont see the device ID or > > vendor ID stuff is of any use because these IDs would be the same for > > the same FPGA board. I dont have any non-volatile memory on the FPGA > > board where I can write my own sequnce which can be read out and > > verified by the application at startup. > > > Any thoughts............. > > > Farhan > > NO. > > if you look at your spec, you see yourself there is no option. > if you CAN NOT customize (nonvolatile setting!) anything on your PCI > board > then you can not use it as software dongle > > . > > some FPGA's have serial numbers, but yours does not. > so you need to add something to your system that is used to protect it > > Antti :) I must correct myself - there is a way without using any extra silicon devices, but its kinda weird, and needs lots of special work to be done FPGA I/Os can be used to "sense" external capacitance, so if you find some unused traces on the PCB that connect to the FPGA, you can put a small paper label with hidden piece of metal foil onto the PCB, and compare the relative capacitance on that IO to some other unused IO that is AS IS. The PCB without that lable will sense different relative capacitances but the amount of time to make this kind of system reliable for real products doesnt make sense. if it is doable, i have used FPGA to sense human finger, plastic FPGA can even sense via package so it can be possible to say what egde of FPGA your finger is touching, but as said, it makes no sense for you to try use this trick. just buy a usb dongle, or add some other thing to your board, for the chip-id that you need AnttiArticle: 130883
referringto@googlemail.com wrote: >>>Years ago I thought about using a serial design to implement a CPU in >>>a GAL 16V8 or 20V8. >>>My idea was to map all registers to memory and to use a 64kbit DRAM as >>>a 256x8 memory >>>that is accessed bit wise. Refresh would have been automatically >>>provided by cycling through the registers. >>>Unfortunately that design never got anywhere. The main issues where >>>that all the flipflops were eaten up >>>by state counters and the design got horribly complex. The ALU design >>>itself was of course negligible. >> >>You would need a few 20V8's to make soemthing useful! > > > Obviously the point was specifically to do something useful with a > single 20V8 :) I did code a MC14500 into a CPLD, and it took 14 product terms and 7 Macrocells, so that IS in 20V8 territory. Whether that is 'something useful' is open to debate, as the MC14500 does not include PC handling :) Where the MC14500 morphs into something interesting, is the IEC61131 language branch Instruction List systax, is quite similar to the MC14500 opcodes (but IL supports a wider choice of data types), so I had thought that a CPLD/FPGA IL execution CPU could be small, and IL is smarter than Assembler (but not as widely known as C ). > It was the next challenge after maxing out on CPLDs (see > http://www.opencores.org/projects.cgi/web/mcpu/overview). Interesting. (I could not see fitter report files ? ) As an exercise a while ago, I did respin the MPROZ into a 128 MC device. > >>You could revisit that in CPLDs - but a 64kb DRAM might be hard to >>find tho! :) > > > 4164s are still easy to come by as NOS - actually I have several tubes > of them. > Of course this is nothing for a new design, but GALs are of similar > vintage so > nothing seems wrong with marrying them to an antique DRAM. > > Actually a better challenge may be to design a CPU with a minimum > number standard logic chips. Even though it is highly anachronistic in > the age of programmable logic, a hard wired sea-of-gates still has > something gratifying to it. Only to a masochist ;) -jgArticle: 130884
Dan K wrote: > I'm getting a fatal error when I try and simulate a Virtex 5 VHDL project > with a block memory core built with coregen. > The Virtex 5 Coregen is only allowing Block Memory Generator V2.6 to be > used. I see these files in the > $XILINX\vhdl\src\XilinxCoreLib directory, but they do not show up in the > ModelSim workspace under xilinxcorelib which only goes up to > blk_mem_gen_v2_4. Does anyone know what I need to do to get ModelSim to > start using these (newer) block mem gen files? Have you recompiled the libraries after the last IP update and/or SP installation? Maybe the Block Memory Generator V2.6 was added in the latest IP update and it will not show up in ModelSim unless you recompile the files in $XILINX\vhdl\src\XilinxCoreLib. You can do that with "compxlib" on a command line, but I think there's a wizard for this in the ISE-GUI somewhere now. HTH, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 130885
Hi all, I have a marvell switched based system with two ports. I want to loop back packets that i send on this switch. Could anyone suggest me how to do this. thanksArticle: 130886
"ni" <nbg2006@gmail.com> wrote in message
news:5f6e1999-3ce9-43c2-bb4a-f9336b3b3edd@s50g2000hsb.googlegroups.com...
> What I dont understand is SRL16 is a simple shift reister and the
> output of SRL16 is just like any other flipflop output with no
> combinational logic at the output.
Wrong.
An SRL16 *functions* just like a simple shift register, but physically it is
a special configuration of a LUT primitive. The setup time and clock-to-out
time is very different from a FF primitive in the fabric. When you are doing
a high-speed design, you should always try to make the last stage of your
shift register pipeline use a dedicated FF. Most synthesis tools will do
this for your automatically if you just write a straightforward shift
register in RTL. No need to go instantiating things.
-Ben-
Article: 130887mdschulte@gmail.com wrote: > > I can tell you exactly why they don't use bittorrent, because they > want to keep track of who has downloaded their software. They don't > want it out there being used by anonymous people that they can't send > their sales weasels calling on. No, you still need to register to get a key. Syms.Article: 130888
mdschulte@gmail.com wrote:
> On Mar 28, 2:34 pm, dalai lamah <antonio12...@hotmail.com> wrote:
>> Un bel giorno Antti digiṭ:
>>
>>> I can not imagine that the server overload is such a real problem that
>>> Xilinx hasnt been able to solve it during the many years of repeated
>>> webserver problems.
>> Yes, and now they are trying to fix it with some stupid Java applets
>> (probably they are hosting the file somewhere else but don't want the user
>> to see the direct link).
>>
>> I don't understand why the big companies don't distribute their software
>> with BitTorrent. It would be so nice, fast and easy for everyone. It would
>> especially make sense for Xilinx, that offers a 2 GB software for free, and
>> poses as the friendly neighborhood multinational. ,-)
>>
>> --
>> emboliaschizoide.splinder.com
>
> I can tell you exactly why they don't use bittorrent, because they
> want to keep track of who has downloaded their software. They don't
> want it out there being used by anonymous people that they can't send
> their sales weasels calling on.
Why would you download Xilinx software if you were not at least thinking
about using Xilinx parts? It's not exactly unreasonable for Xilinx to
be interested in who is using their software, and share this information
with their sales and marketing people and their distributors - unless
their sales people are doing a spectacularly bad job, it is in the
customers' interests that they have this information. It is not as if
they are cold calling - by using their software, you've already shown
your interest in their products.
And anyway, as Symon says, it is the licensing that registers you as a
user. If you have several users at the same site, I'm sure Xilinx is
happy for you to download a single copy of the software to share.
The reason (I presume) they don't use bittorrent is basically because it
would not work for this sort of software. Only a small proportion of
users would be interested in using bittorrent downloads in a
professional setting, and only a few of these would be allowed by their
IT department, and even fewer would leave the torrents running with fast
enough upload capacity for other downloaders to see decent download
speeds. Add to that the common misunderstandings of bittorrent ("How do
we know we are getting the proper software - maybe the file is corrupt,
or it's picked up a virus from some sharer's PC?" and "Isn't bittorrent
only for (sic) pirated files?") and some ISP's brain-dead
anti-bittorrent schemes to cheat users out of their bandwidth, and you
get a very poor choice of distribution method for this kind of software.
Article: 130889"Antti" <Antti.Lukats@googlemail.com> wrote in message news:07b8a5e0-ed65-4f91-9bd9-da045e18f497@t54g2000hsg.googlegroups.com... > On 4 Apr., 12:05, maverick <sheikh.m.far...@gmail.com> wrote: >> On Apr 4, 3:41 am, "MM" <mb...@yahoo.com> wrote: >> >> Farhan > > NO. > > if you look at your spec, you see yourself there is no option. > if you CAN NOT customize (nonvolatile setting!) anything on your PCI > board > then you can not use it as software dongle > > . > > some FPGA's have serial numbers, but yours does not. > so you need to add something to your system that is used to protect it > > Antti > When FPGA serial no. functionality is not available Physically Unclonable Functions (PUFs) can do the job. In few words it is a challenge-response mechanism where the response is unique thanks to FPGA fabrication variance, thus (in theory) unclonable. Compulsory lecture refs below. Regards, Krzysztof Lee, J. W.; Lim, D.; Gassend, B.; Suh, G. E.; van Dijk, M. & Devadas, S. A technique to build a secret key in integrated circuits for identification and authentication application Proceedings of the Symposium on VLSI Circuits, 2004, 176-159 Abstract This paper describes a technique that exploits the statistical delay variations of wires and transistors across ICs to build a secret key unique to each IC. To explore its feasibility, we fabricated a candidate circuit to generate a response based on its delay characteristics. We show that there exists enough delay variation across ICs implementing the proposed circuit to identify individual ICs. Further, the circuit functions reliably over a practical range of environmental variation such as temperature and voltage. Suh, G. E. & Devadas, S. Physical unclonable functions for device authentication and secret key generation Design Automation Conference, ACM Press, 2007, 9-14 Abstract Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.Article: 130890
One more question. For example, I have no WebPACK distributive but I have ISE Foundation distributive. May I use ISE Foundation distributive but enter WebPACK key at installation? Do I have to download exactly WebPACK distributive if I want to install WebPACK?Article: 130891
On Apr 4, 9:05 am, zlyh <zly...@gmail.com> wrote: > One more question. > For example, I have no WebPACK distributive but I have ISE Foundation > distributive. May I use ISE Foundation distributive but enter > WebPACK key at installation? > Do I have to download exactly WebPACK distributive if I want to > install WebPACK? You need an ISE key for ISE, and a WebPack key with WebPack. -aArticle: 130892
Is there any known pitfalls or problems with driving xilinx fpga (spartan) with smps (buck) ..?Article: 130893
I posted the following on Mon, 31 Mar 2008 15:28:24 +0200 but it did not seem to reach Usenet... On Fri, 28 Mar 2008, Symon wrote: |-------------------------------------------------------------------------| |"TLDR, sorry. However, could I make the comment that if you're trying to | |court offers of employment or a placement, slagging off your previous | |employer on a public forum might not be the best way attract future ones?| |Good luck, Syms." | |-------------------------------------------------------------------------| Hello Symon, I do not know what TLDR stands for. Thank you for your advice and for wishing me well, but please believe me, I did not take the decision to post about this to Usenet lightly. I uncovered the fraud approximately 17 months ago and I have been trying to find another way to make a living for most of the time after then. I quit almost seven months ago and so my finances are now very low. I am not looking forward to becoming homeless before the end of the Summer. I applied to a different university's electronic engineering department in August 2007, on March 13th, 2008 (and possibly still) no one has been offered any of the scholarships but I was told earlier this month that I was rejected largely because it was not clear why I quit the University of Pisa (I had said that I was not allowed to conduct the research which I wanted, which is true). Being too nice to the University of Pisa has not helped me to secure a new way to sustain my life, so I have resorted to providing more details. Perhaps this will also not work, but at least it could be said that neither approach worked. Yours sincerely, Colin PaulArticle: 130894
I posted the following at Mon, 31 Mar 2008 15:36:23 +0200 but it did not seem to penetrate a newsserver into Usenet... On Fri, 28 Mar 2008, Jon Beniston wrote: |----------------------------------------------------------------------| |"Student discovers that real world code isn't quite as perfect as they| |were taught it would be in university. Shocker!" | |----------------------------------------------------------------------| If you would care to check the references which I complained about, you would note that they were written by research institutes which had been funded (and actually still are being funded) by the European Commission for research. Furthermore, if you would care to check, you would note that the papers I complained about are fraudulent, and I was forced to leave because I exposed that they did not know how to do what they were being paid to do. Yours sincerely, Colin Paul GlosterArticle: 130895
sky465nm@trline4.org wrote: > Is there any known pitfalls or problems with driving xilinx fpga > (spartan) with smps (buck) ..? Yes, not reading the "Troubleshooting hints" section of AN19 first. Particularly hint 12. Google :- AN19 site:linear.com HTH., Syms.Article: 130896
On Apr 4, 7:28 am, "Ben Jones" <ben.jo...@xilinx.com> wrote:
> "ni" <nbg2...@gmail.com> wrote in message
>
> news:5f6e1999-3ce9-43c2-bb4a-f9336b3b3edd@s50g2000hsb.googlegroups.com...
>
> > What I dont understand is SRL16 is a simple shift reister and the
> > output of SRL16 is just like any other flipflop output with no
> > combinational logic at the output.
>
> Wrong.
>
> An SRL16 *functions* just like a simple shift register, but physically it is
> a special configuration of a LUT primitive. The setup time and clock-to-out
> time is very different from a FF primitive in the fabric. When you are doing
> a high-speed design, you should always try to make the last stage of your
> shift register pipeline use a dedicated FF. Most synthesis tools will do
> this for your automatically if you just write a straightforward shift
> register in RTL. No need to go instantiating things.
>
> -Ben-
So what your are implying is that its advisable to write the code in
the following way
---------------------------------------------------------------------------------------------------------------------------------------------
PROCESS(clock,reset)
begin
if reset = '1' then
en4 <= '0';
elsif clock'event and clock ='1' then
en4 <= en3;
end if;
end process;
SR : SRL16 generic map
(INIT => x"0000")
port map (Q => en3,
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CLK => clock,
D => input);
---------------------------------------------------------------------------------------------
instead of
SR : SRL16 generic map
(INIT => x"0000")
port map (Q => en4,
A0 => '1',
A1 => '1',
A2 => '0',
A3 => '0',
CLK => clock,
D => input);
Is that right?
Article: 130897Morten Leikvoll wrote: > Maybe you should give us some information on how to proceed if we are > stuck with exeed devices with significant value, and want to sell > them. eBay. From webmaster@nillakaes.de Fri Apr 04 10:28:30 2008 Path: newssvr29.news.prodigy.net!newsdbm05.news.prodigy.net!newsdbm04.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin2!goblin.stu.neva.ru!feed.cnntp.org!news.cnntp.org!not-for-mail Message-Id: <47f6653f$0$581$6e1ede2f@read.cnntp.org> From: Thorsten Kiefer <webmaster@nillakaes.de> Subject: Examples for Spartan3 StarterKit Newsgroups: comp.arch.fpga Date: Fri, 04 Apr 2008 19:28:30 +0200 User-Agent: KNode/0.10.4 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Lines: 12 Organization: CNNTP NNTP-Posting-Host: 333b8e57.read.cnntp.org X-Trace: DXC=PX]V\<A`E?j[:`?W2<9:HiWoT\PAgXa?aO>f1biSlT6g1P5d:S1^>6cdlT:^LKmYjjTmW9KhcVAObl8iEgG6o>d` X-Complaints-To: abuse@cnntp.org Xref: prodigy.net comp.arch.fpga:143321 Hi, I'm currently developing some examples for the Spartan3 StarterKit from digilent. Maybe this is interesting for newbies. I know that they are not spectacular at the moment. You can leave me a comment if you want. http://tokisworld.org/spartan3/ Regards ThorstenArticle: 130898
On Mar 31, 9:00 pm, jo...@mit.edu wrote: > On Mar 31, 2:08 pm, "pillar2...@gmail.com" <pillar2...@gmail.com> > wrote: > > > > When you say "start up webpack", do you mean the ISE gui? > > > Yes > > > > I've not > > > used it, but I did note that the settings.sh is now settings32.sh and > > > is located under the ISE/ directory. > > > I am already aware of those files. These files do not invoke the > > gui. In version 9.2i there was an executable called ise which would > > invoke the program/gui. I still have not figured out where this file > > (I have even looked for anything that would be renamed etc) is. > > > Newell > > For me > /opt/xilinx10.1/ISE/bin/lin/ise, which is placed on my path (so you > can invoke it with "ise") when you source the above files. Does it not > exist in your install? No, it does not exist there. I downloaded twice as well just to make sure that it downloaded properly. I will try downloading again but this time I will get the .tar instead of doing the web install.....maybe that will help.Article: 130899
Go here: http://www.xilinx.com/products/design_resources/power_central/ Then scroll down to the manufacturers. Pick the one you like, and go to their Xilinx FPGA power supply pages. All choices are "approved" for use with ALL Xilinx product. We (I personally) spend a lot of time with these folks, to ensure a smooth (pun intended) powering experience. Not sure why the other negative posts...perhaps these are the folks who ignore our hard work, and decide to see if a power solution works all on their own. Austin
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