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Messages from 134100

Article: 134100
Subject: Re: SD Card Controller
From: John_H <newsgroup@johnhandwork.com>
Date: Fri, 25 Jul 2008 06:03:24 -0700
Links: << >>  << T >>  << A >>
Here's a shot in the dark:

Are you certain the clock edge is where you want it relative to the data 
setup and hold time requirements?

Article: 134101
Subject: Re: Xilinx FPGA editor tips?
From: Kevin Neilson <kevin_neilson@removethiscomcast.net>
Date: Fri, 25 Jul 2008 11:39:14 -0600
Links: << >>  << T >>  << A >>
Michael Brown wrote:
> 
> "Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message 
> news:g633bv$4452@cnn.xsj.xilinx.com...
> [...]
>> If there is any possible way to fix the source (pipelining, Shannon 
>> expansion, etc.) then fix it there.
> 
> The problem is that it's in an async part of the design (I know, I know, 
> asynchronous designs are evil[*]) - actually the part that takes an 
> async external signal and gets it to something more friendly. I have a 
> number of clocks, each with a slight phase shift, each latching the wire 
> I'm having trouble with. The amount of skew in the line basically 
> determines the number of flipflops that will be metastable. I have logic 
> in there to handle this, but unfortunately it essentially grows 
> exponentially with the amount of skew.
> 
> Ideally, I'd like to tell the placer/router to sort things out so that 
> the skew goes in the opposite direction to the clock delays. 
> Unfortunately this doesn't seem to be possible? Hence why I resorted to 
> hand-routing it. Additionally, once I get this bit sorted out, it's very 
> unlikely to change.
> 
> [*] Actually, this design uses pretty much every evil technique in the 
> book. Asynchronous regions, combinatorial loops, and logic-generated 
> clocks. A -4 Spartan 3E really takes a lot of coersion to handle 1-ns 
> pulses ...
> 
I don't quite understand what you're doing but if you want to have a 
tapped-delay line or a controllable delay, you might try using an adder 
  carry chain.  A carry chain column uses dedicated routing, so you 
don't have to worry about routing (or even placement, since the carry 
chain elements automatically get placed adjacent to each other).  You 
can tap from any point in the line to get the amount of skew you want, 
and the resolution is pretty small.  -Kevin

Article: 134102
Subject: Re: Prevent synthesis optimizations/simplifications in Xilinx-ISE
From: "blakaxe@gmail.com" <blakaxe@gmail.com>
Date: Fri, 25 Jul 2008 12:13:55 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 25, 8:23=A0am, Gabor <ga...@alacron.com> wrote:
> On Jul 25, 6:12 am, giorgos.puik...@gmail.com wrote:
>
>
>
>
>
> > Hello,
>
> > I want to implement a VHDL design in a Spartan3 device. Some
> > components of the design use cascaded inverters to produce one-shots
> > (short pulses). Upon synthesis, Xilinx-ISE simplifies the cascaded
> > inverters (e.g. if 6 inverters are cascaded it simply removes them
> > all). This alters the functionality of the design.
>
> > How can I configure ISE so that it does not perform such
> > simplifications (preferably per block, but if this is not possible for
> > the whole design)?
>
> > Thank you in advance guys!
>
> > Regards,
> > George
>
> Unfortunately simple logic elements like inverters and gates will
> always be mapped into LUT's regardless of any KEEP attributes on
> the intermediate nets. =A0You can however create such delay elements
> by instantiating primitives like LUT's with the appropriate INIT
> attributes to generate the functions you want. =A0Look at the
> Libraries guide to see your options for LUT instantiation.
>
> I should add that this sort of design practice is generally frowned
> upon in FPGA's, especially since there is a very wide variance in
> delay due to process and temperature, and a possibly even wider
> variance from build to build due to routing if you don't hand
> place your delay elements. =A0Usually you can use synchronous
> techniques to create pulses and with a sufficiently fast clock
> rate you can often ignore the discrete timing effects of the
> synchronous pulse generator.
>
> Regards,
> Gabor- Hide quoted text -
>
> - Show quoted text -

I know exactly what you need
use the attribute KEEP to prevent the wires between the inverters from
getting optimized away

(* keep =3D "true" *) wire [length-1:0] connect;

Additionally you can use LUT instantion primitives for anot gates as
shown

generate
genvar k;
for (k=3D0; k<length-1; k=3Dk+1)
begin : not
LUT1 #(
=2EINIT(2'b01) // Specify LUT Contents
) LUT1k (
=2EO(connect[k+1]), // LUT general output
=2EI0(connect[k]) // LUT input
);
end
endgenerate

ENJOY!

Article: 134103
Subject: chipscope pro
From: irfan.mohammed@gmail.com
Date: Fri, 25 Jul 2008 12:14:24 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello friends,

i have written uart module in vhdl,i have verified using xilinx
simulator,but now when i have generated the core of icon,ila and vio,i
am unable to get  correct output in vio console.

i have inputs as
clk
rst
write
read
din(7 downto 0)

output as dout(7 downto 0)

i have given in xilinx simulator like this

clk connected to C9 on kit
rst--------------------------------------
 
------------------------------------------

write---------------------------------------------------
 
----------------------------------------

 
----------------------------------------
read -------------------------------------------------

din 10101010
dout 10101010

when i give 10101010 as input i should get 10101010 as output but i
get 11111111 as output

u can see the above wave form when write is high then read is low and
when read is high write is low,how can i specify in vio console.

i am using toggle button to write and read signals.i am not using any
clock divider,is it required?

what ever i do i just get 11111111.

Thanks in advace
Irfan



Article: 134104
Subject: Re: SD Card Controller
From: "devices" <me@home>
Date: Fri, 25 Jul 2008 21:52:11 +0200
Links: << >>  << T >>  << A >>

"John_H" <newsgroup@johnhandwork.com> ha scritto nel messaggio 
news:MM6dnaCHurSKUhTVnZ2dnUVZ_oPinZ2d@comcast.com...
> Here's a shot in the dark:
>
> Are you certain the clock edge is where you want it relative to the data 
> setup and hold time requirements?

The spi driver runs concurrently with the card controller
logic, in its own state machine. So it has the chance to
drive clock and data with the right phase according to
cpol = 0, cpha = 0. Simulation shows a 90 degree
phase shift between sck and mosi.



Article: 134105
Subject: Re: Xilinx FPGA editor tips?
From: Gabor <gabor@alacron.com>
Date: Fri, 25 Jul 2008 14:57:36 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 25, 1:39 pm, Kevin Neilson
<kevin_neil...@removethiscomcast.net> wrote:
[snip]
> I don't quite understand what you're doing but if you want to have a
> tapped-delay line or a controllable delay, you might try using an adder
>   carry chain.  A carry chain column uses dedicated routing, so you
> don't have to worry about routing (or even placement, since the carry
> chain elements automatically get placed adjacent to each other).  You
> can tap from any point in the line to get the amount of skew you want,
> and the resolution is pretty small.  -Kevin

I tried this approach and made an interesting discovery.  The time it
takes a signal to propagate up a carry chain is almost the same as
the routing delay between the carry chain inputs.  I was trying to
make a tapped delay line, but because my signal source entered the
chain from the LSB end, changing the tap made almost zero difference
in the output delay.  I thought I had a simulation bug, but the
hardware confirmed the same timing.  At the time I didn't know how to
manually route the signal to bring it in from the other end of
the carry chain and theoretically get 2x time per tap rather than 0x
time.  So I threw the whole mess out and went back to LUT's as
delay elements :(

Regards,
Gabor

Article: 134106
Subject: Creating new operators
From: rickman <gnuarm@gmail.com>
Date: Fri, 25 Jul 2008 22:46:26 -0700 (PDT)
Links: << >>  << T >>  << A >>
In VHDL an operator can be overloaded.  But can a new operator be
created?  There is more than once I would like to use the very concise
notation available in Verilog such as the select operator.  Is there a
way to create the selection operator in VHDL?  Looking at the
structure, I guess it just doesn't fit the mold for VHDL with three
operands.

I know I can create a function for this such as select(sel,a,b), but I
like the form of the notation sel ? a : b, very clear and concise.  I
guess I could always switch to Verilog... :^)

Rick

Article: 134107
Subject: Re: Xilinx FFT core's IFFT function not working? Dun Xilinx TEST
From: chrisdekoh@gmail.com
Date: Fri, 25 Jul 2008 23:41:47 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,
   I have checked. the first input sample is fed in when index for xn
is 3. I have followed the timing.
   But i found something further. The problem is due to the FFT
result.

 Did you do this the last time?
1) generate 24 bit number
2) feed into the FFT
3) the 34 bit result which you obtain in VHDL testbench is piped into
a text file. afterward, you IFFT the result in matlab

the waveform you get  in (3) is generated  against the initial
generated waveform fed into FFT described in step (1). in addition, i
found the waveform generated here is also as described in the previous
email with the leading 7 sampes roughly the same value.
also, the final waveform for both real and complex portions is one
time sample delayed to the original input sample.

possibly that this is due to quantization errors?

thanks again.
Chris


On Jul 25, 11:53=A0am, Tom <tom.der...@gmail.com> wrote:
> On Jul 25, 9:49=A0am, chrisde...@gmail.com wrote:
>
> > 2) I run my testbench in modelsim (simulation). the testbench reads in
> > the text file of complex waveforms generated in (1). It is then fed
> > through the xilinx core generated FFT. This generates an FFT result.
> > (I have verified this output in matlab. It seems to be working fine.)
>
> Are you sure that you have got the correct timing between the first
> input data word and the other FFT core control inputs?
> For example, you have to assert the Start input a few cycles before
> you put the first data word on the input data bus of the core. Have a
> careful look at the timing diagram for pipelined streaming mode in the
> Xilinx FFT data sheet to make sure you have the timing correct in your
> simulation.
> I have used this core in almost the same configuration you describe
> with no problems.
>
> -T


Article: 134108
Subject: Re: Creating new operators
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Sat, 26 Jul 2008 10:31:32 +0100
Links: << >>  << T >>  << A >>
On Fri, 25 Jul 2008 22:46:26 -0700 (PDT), rickman wrote:

>In VHDL an operator can be overloaded.  But can a new operator be
>created?  There is more than once I would like to use the very concise
>notation available in Verilog such as the select operator.  Is there a
>way to create the selection operator in VHDL?  Looking at the
>structure, I guess it just doesn't fit the mold for VHDL with three
>operands.

No, you can't create new VHDL operators.  Apart from 
introducing new pseudo-keywords into the language, this would
also raise the nasty difficulty that operators have many other
hidden properties apart from their function signature. 
Operators have precedence and associativity.  And of course,
as you say, VHDL has no notion of 3-ary operators like ?:
in any case.

Algol-68 tried to make it possible to create arbitrary 
user-defined operators, and it was VERY complicated...

>I know I can create a function for this such as select(sel,a,b), but I
>like the form of the notation sel ? a : b, very clear and concise.  I
>guess I could always switch to Verilog... :^)

If that's sufficient reason for you to ditch VHDL in favour
of Verilog, I put it to you that your priorities are in need
of some readjustment :-)
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 134109
Subject: Re: Creating new operators
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Sat, 26 Jul 2008 12:56:27 +0100
Links: << >>  << T >>  << A >>
On Sat, 26 Jul 2008 10:31:32 +0100, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:

>On Fri, 25 Jul 2008 22:46:26 -0700 (PDT), rickman wrote:
>
>>In VHDL an operator can be overloaded.  But can a new operator be
>>created?  There is more than once I would like to use the very concise
>>notation available in Verilog such as the select operator.  Is there a
>>way to create the selection operator in VHDL?  Looking at the
>>structure, I guess it just doesn't fit the mold for VHDL with three
>>operands.
>
>No, you can't create new VHDL operators.  Apart from 
>introducing new pseudo-keywords into the language, this would
>also raise the nasty difficulty that operators have many other
>hidden properties apart from their function signature. 
>Operators have precedence and associativity.  And of course,
>as you say, VHDL has no notion of 3-ary operators like ?:
>in any case.
>
>Algol-68 tried to make it possible to create arbitrary 
>user-defined operators, and it was VERY complicated...

More dynamic OO languages support arbitrary operator creation; Smalltalk
would be an example, or the old Linn Lingo.

It's not VERY complicated _in_that_environment_ where static typing is
almost non-existent (strong typing can be rigorous, but implemented at
runtime) BUT ...
(1) you are limited to the creation of binary operators; so ?: is still
tricky, to put it mildly, and
(2) operator precedence is usually predetermined and deeply embedded in
the parser. The above languages solved this problem by allocating
precisely one precedence level to all operators - in other words, use
brackets.

I suspect extensible operator precedence was the main complexity in
ALGOL-68. 

But anyway I suspect you'd have to destroy VHDL to add extensible
operators...

>>I know I can create a function for this such as select(sel,a,b), but I
>>like the form of the notation sel ? a : b, very clear and concise.  I
>>guess I could always switch to Verilog... :^)

It may be personal preference, but I find if-then-else MUCH easier to
read in somebody else's code.

?: does save a few of those precious characters though.

- Brian


Article: 134110
Subject: Re: Quartus2 pin assignment
From: Paul Urbanus <urbpublic@hotmail.com>
Date: Sat, 26 Jul 2008 07:18:43 -0500
Links: << >>  << T >>  << A >>
KJ wrote:
> On Jul 24, 10:54 am, ghelbig <ghel...@lycos.com> wrote:
>> On Jul 23, 11:44 am, Mike Treseler <mtrese...@gmail.com> wrote:
>>
>>> ghelbig wrote:
>>>> I haven't entered pin numbers manually in years.  Too easy to make
>>>> mistakes, especially with pin counts in the K range.
>>>> I have one PERL script that parses a wirelist into a spreadsheet, and
>>>> another that turns the spreadsheet into a constraint file.
>>>> And Quartus supports Tcl scripts for pin number entry, that method
>>>> works "just fine" too.
>>> That makes good sense for pin numbers.
>>> But direction should be inferred from the code,
>>> and IO type and timing is a separate problem.
>>>        -- Mike Treseler
>> That's why I run it through the spread sheet; I set the I/O type
>> there.  Getting direction from the top level would be a good addition.
>>
>> Timing is always a problem... :)
>>
> 
> I use the spreadsheet as basically the 'master' data set and put all I/
> O information there.  I have columns in there for...
> 1. The basics: signal name, direction, pin number, setup, hold, clock-
> to-output, propogation delay requirements.
> 2. Device specific options: I/O drive strength, slew rate,
> termination, I/O voltage standard, fast input/output registers (and
> any other properties that belong with a signal I/O).
> 
> Each of the things in #1 and #2 get a column in the spreadsheet.  Each
> signal gets a row.
> 
> Various pages in that spreadsheet workbook produce the following
> design artifacts that are then simply copy/pasted into the appropriate
> tool.  The formulas on those pages produce text in the format required
> by the tool (i.e. valid VHDL or TCL).
> 
> - Design top level port map (can be pasted into the VHDL file).
> - Port map with the connections to the testbench instantiation of the
> design.
> - TCL script to load into the synthesis tool to set all of the
> properties.
> 
> Since it's in a spreadsheet I can use formulas so that changes in one
> area get reflected in all of the appropriate places.  Particularly
> when it comes to calculating timing requirements this is useful
> because you can have a completely different workbook page that defines
> the clocks involved, DLL/PLL clock multiplier/divider values, setup/
> hold requirements of the devices that the design will be talking to.
> Deriving the timing requirements for the new design in this manner,
> makes it a lot clearer to follow (and find calculation errors) than if
> the calculations are done 'somewhere else' and only the end result
> value is pasted into the tool.
> 
> In effect the spreadsheet is the master source of the information and
> also directly produces design artifacts that are then copied into
> other tools...and I suppose if there is a way to output the values in
> the pages of a spreadsheet into separate files then the manual copy/
> paste operation could be eliminated.
> 
> KJ

I also use excel in a similar fashion, where each pin/signal gets a 
separate row and all of the various attributes of that pin are in columns.

One of the problems with having the tool take pin assignments and 
generate a top-level entity is the order of the signals. With an excel 
file, the top-level entity ports are ordered the same way as the in the 
excel file. The excel file also allows comments to be added to the 
top-level port signals for documentation purposes. I like to add a 
comment to each signal and also add comments before each logical signal 
group. Finally, the style/formatting of the top level entity to match 
the user's preferences is easily controlled by excel formulas.

The same concepts for formatting and comments also apply to the FPGA pin 
definition file. For me, that would primarily be a xilinx .ucf file. 
Some ancillary columns which I include in my excel pin list the 
schematic net name to which the port/pin is connected and any 
connector(s) to which the pin is attached. This information can then be 
included in either the top-level VHDL/verilog entity or the .ucf file.

I typically use cut/paste transfer the formulated text to the 
appropriate text file.

Urb

Article: 134111
Subject: Spartan-3A DSP 1800A Dev Board JTAG Cable and Programming Software
From: no.spam@gte.net (Scott Gravenhorst)
Date: Sat, 26 Jul 2008 12:37:57 GMT
Links: << >>  << T >>  << A >>
I have a Spartan-3A DSP 1800A development board which comes with no
cable.  I understand that Xilinx makes a cable for $150 that works
with iMPACT.  There is also a 6 pin JTAG conntector on the board.  

I already know that the Digilent JTAG-USB cable will NOT work with
either iMPACT nor Adept.  Communication with Digilent indicates that
they may support this FPGA in the future, but it is currently not
supported.  I've also tried xilprg which does not yet support this
FPGA.

I would like to find a more cost effective method than the Xilinx
cable.  I've read comments here and elsewhere that the Digilent
Parallel III cable is a clone of the Xilinx cable.  Does anyone know
if Will this cable (Digilent Parallel III) works with this board and
iMPACT or any other Windows based FPGA programmer software?  Or is
there a better solution?

Many thanks.

-- ScottG

Article: 134112
Subject: Re: Creating new operators
From: rickman <gnuarm@gmail.com>
Date: Sat, 26 Jul 2008 06:04:01 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 26, 7:56 am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Sat, 26 Jul 2008 10:31:32 +0100, Jonathan Bromley
>
>
>
> <jonathan.brom...@MYCOMPANY.com> wrote:
> >On Fri, 25 Jul 2008 22:46:26 -0700 (PDT), rickman wrote:
>
> >>In VHDL an operator can be overloaded.  But can a new operator be
> >>created?  There is more than once I would like to use the very concise
> >>notation available in Verilog such as the select operator.  Is there a
> >>way to create the selection operator in VHDL?  Looking at the
> >>structure, I guess it just doesn't fit the mold for VHDL with three
> >>operands.
>
> >No, you can't create new VHDL operators.  Apart from
> >introducing new pseudo-keywords into the language, this would
> >also raise the nasty difficulty that operators have many other
> >hidden properties apart from their function signature.
> >Operators have precedence and associativity.  And of course,
> >as you say, VHDL has no notion of 3-ary operators like ?:
> >in any case.
>
> >Algol-68 tried to make it possible to create arbitrary
> >user-defined operators, and it was VERY complicated...
>
> More dynamic OO languages support arbitrary operator creation; Smalltalk
> would be an example, or the old Linn Lingo.
>
> It's not VERY complicated _in_that_environment_ where static typing is
> almost non-existent (strong typing can be rigorous, but implemented at
> runtime) BUT ...
> (1) you are limited to the creation of binary operators; so ?: is still
> tricky, to put it mildly, and
> (2) operator precedence is usually predetermined and deeply embedded in
> the parser. The above languages solved this problem by allocating
> precisely one precedence level to all operators - in other words, use
> brackets.
>
> I suspect extensible operator precedence was the main complexity in
> ALGOL-68.
>
> But anyway I suspect you'd have to destroy VHDL to add extensible
> operators...
>
> >>I know I can create a function for this such as select(sel,a,b), but I
> >>like the form of the notation sel ? a : b, very clear and concise.  I
> >>guess I could always switch to Verilog... :^)
>
> It may be personal preference, but I find if-then-else MUCH easier to
> read in somebody else's code.
>
> ?: does save a few of those precious characters though.
>
> - Brian

The problem is not so much reading the code, but is writing.  I think
in the terms of the logic, usually a schematic/block diagram.  Then I
try to express that logic in the language.  It is not uncommon that it
is simply impossible to express the logic in the form I have drawn
it.  Then I have to convolute it to come up with something that is
what I have drawn, or at least I hope so.

Example: A data mux controlled by the output of an AND of a signal and
the output of a mux.  This is four control signals gated together to
drive the control on the data mux.  Here is what I ended up with.

  BERTEn <=	'0' when BERTSel = '0' else
		not SyncPOSSel when GenEn = '0' else
		not GenPOSSel;

I don't think that the diagram I drew comes to mind when you see this
code.  Maybe a process with an IF statement would be slightly more
clear, but the verbosity presents an obfuscation of its own from the
"clutter" created.

process (  BERTSel, SyncPOSSel, GenEn, GenPOSSel) begin
  if (BERTSel = '0') then
    BERTEn <=	'0';
  elsif (GenEn = '0') then
    BERTEn <=	not SyncPOSSel
  else
    BERTEn <=	not GenPOSSel;
  end if;
end process;

The clutter is from the sheer size of the code.  The first three line
example is a bit obtuse, the 9 line example is large enough to make it
hard to see the rest of the code and so to see how it fits into the
big picture.  Compare the two examples to this code...

  BERTEn <=	BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel;

This is what I expect a concurrent statement to look like, not to
mention that it represents exactly the image I had in my head and on
the whiteboard, making it much easier to write.

I am sure there are those who disagree and much prefer the verbose
process.  Maybe I'm just not cut out for the regimen of VHDL.

Rick

Article: 134113
Subject: Re: Creating new operators
From: Mike Treseler <mtreseler@gmail.com>
Date: Sat, 26 Jul 2008 06:38:17 -0700
Links: << >>  << T >>  << A >>
rickman wrote:

>   BERTEn <=	BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel;

     if BERTSel and GenEn then
        BERTEn <= not SyncPOSSel;
     else
        BERTEn <= not GenPOSSel;
     end if;

Article: 134114
Subject: Re: Creating new operators
From: "KJ" <kkjennings@sbcglobal.net>
Date: Sat, 26 Jul 2008 10:00:38 -0400
Links: << >>  << T >>  << A >>

"rickman" <gnuarm@gmail.com> wrote in message 
news:62e47371-9d8d-43d1-a97b-4759ecc35fc6@56g2000hsm.googlegroups.com...
.
>
> I know I can create a function for this such as select(sel,a,b), but I
> like the form of the notation sel ? a : b, very clear and concise.

This is nearly as concise and what I use.

x<= sel(Condition, a, b);

You would have to overload 'sel' to handle all the data types that you deal 
with (std_(u)logic(_vector), integer, real, time, etc).  These could be 
written once and then put into a common package that you use with wild 
abandon.  More specialized types that are application specific like records 
would then need similar overrides (if needed).

> I
> guess I could always switch to Verilog... :^)
>

If that's the best reason you got, then you cna have it.

KJ 



Article: 134115
Subject: Re: Creating new operators
From: Frank Buss <fb@frank-buss.de>
Date: Sat, 26 Jul 2008 16:12:40 +0200
Links: << >>  << T >>  << A >>
rickman wrote:

>   BERTEn <=	BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel;

This is not the same logic as you described with your initial example.

> This is what I expect a concurrent statement to look like, not to
> mention that it represents exactly the image I had in my head and on
> the whiteboard, making it much easier to write.

What about this one:

BERTEn <= (not SyncPOSSel) when (BERTSel='1' and GenEn='1')
            else (not GenPOSSel);

The parantheses are not necessary, but helps reading it.

I don't like elsif and I would write your initial example like this:

	process (BERTSel, SyncPOSSel, GenEn, GenPOSSel) begin
		if BERTSel = '0' then
			BERTEn <= '0';
		else
			if GenEn = '0' then
				BERTEn <= not SyncPOSSel;
			else
				BERTEn <= not GenPOSSel;
			end if;
		end if;
	end process;

Some more code, but you don't have to think about when reading it, because
it shows the hierarchically structure, which is only implicit in your code.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 134116
Subject: Re: Creating new operators
From: rickman <gnuarm@gmail.com>
Date: Sat, 26 Jul 2008 08:03:43 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 26, 9:38 am, Mike Treseler <mtrese...@gmail.com> wrote:
> rickman wrote:
> >   BERTEn <=     BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel;
>
>      if BERTSel and GenEn then
>         BERTEn <= not SyncPOSSel;
>      else
>         BERTEn <= not GenPOSSel;
>      end if;

One of us doesn't understand the precedence (I'm not sure which
one...).  That is always a good reason for not allowing precedence
defaults to define an expression...

   BERTEn <=     BERTSel and (GenEn ? not SyncPOSSel : not GenPOSSel);

Is that more clear?

Rick

Article: 134117
Subject: Re: Creating new operators
From: rickman <gnuarm@gmail.com>
Date: Sat, 26 Jul 2008 08:22:18 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 26, 10:12 am, Frank Buss <f...@frank-buss.de> wrote:
> rickman wrote:
> >   BERTEn <=     BERTSel and GenEn ? not SyncPOSSel : not GenPOSSel;
>
> This is not the same logic as you described with your initial example.
>
> > This is what I expect a concurrent statement to look like, not to
> > mention that it represents exactly the image I had in my head and on
> > the whiteboard, making it much easier to write.
>
> What about this one:
>
> BERTEn <= (not SyncPOSSel) when (BERTSel='1' and GenEn='1')
>             else (not GenPOSSel);
>
> The parantheses are not necessary, but helps reading it.
>
> I don't like elsif and I would write your initial example like this:
>
>         process (BERTSel, SyncPOSSel, GenEn, GenPOSSel) begin
>                 if BERTSel = '0' then
>                         BERTEn <= '0';
>                 else
>                         if GenEn = '0' then
>                                 BERTEn <= not SyncPOSSel;
>                         else
>                                 BERTEn <= not GenPOSSel;
>                         end if;
>                 end if;
>         end process;
>
> Some more code, but you don't have to think about when reading it, because
> it shows the hierarchically structure, which is only implicit in your code.

You got the same result as Mike, so I assume I had the precedence
default wrong.  No, I guess there is *no* precedence since there is no
selection operator.  This is what I intended.  To make it more VHDL
like, I need to add an equivalence operator too.

   BERTEn <=     BERTSel and ((GenEn = '1') ? not GenPOSSel : not
SyncPOSSel);

The process based description is not immediately clear to me at first
glance.  I *do* have to think about it since that is not what I
picture in my mind.  I visualize a MUX controlled by GenEn feeding an
AND gate with BERTSel.  The Verilog like assignment maps exactly to
that visualization.  The others require me to mentally convert the
syntax from and IF statement to the AND gate not to mention the length
of the code.  But like I said, it is not that this is hard to
understand, it is not what I pictured in my mind and so I had to
perform a conversion from the logic to the syntax.  That takes time
and is a distraction from making my work accurate.

I have no doubt that others may find that verbose code is easier for
them to read.  But I find concise code is best (but not too!
concise).  There are any number of different logic forms to be
expressed and each is expressed best in different ways.  I think the
selection statement is an operator that has a useful place in VHDL.
I'm just sorry it wasn't included.  I guess it would have been hard to
provide for overloading since it does not fit the standard uniary or
binary format.

Rick

Article: 134118
Subject: Re: Spartan-3A DSP 1800A Dev Board JTAG Cable and Programming
From: ghelbig <ghelbig@lycos.com>
Date: Sat, 26 Jul 2008 09:38:02 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 26, 5:37 am, no.s...@gte.net (Scott Gravenhorst) wrote:
> I have a Spartan-3A DSP 1800A development board which comes with no
> cable.  I understand that Xilinx makes a cable for $150 that works
> with iMPACT.  There is also a 6 pin JTAG conntector on the board.
>
> I already know that the Digilent JTAG-USB cable will NOT work with
> either iMPACT nor Adept.  Communication with Digilent indicates that
> they may support this FPGA in the future, but it is currently not
> supported.  I've also tried xilprg which does not yet support this
> FPGA.
>
> I would like to find a more cost effective method than the Xilinx
> cable.  I've read comments here and elsewhere that the Digilent
> Parallel III cable is a clone of the Xilinx cable.  Does anyone know
> if Will this cable (Digilent Parallel III) works with this board and
> iMPACT or any other Windows based FPGA programmer software?  Or is
> there a better solution?
>
> Many thanks.
>
> -- ScottG

I started down that path; it bothered me to pay $200 for a simple USB
dongle.

The Xilinx programmer "just works".  If it doesn't, my friendly local
FAE will fix that. I figured that I would be busy enough working on
the real parts of the project that the half-week (or so) spent looking
for a lower-cost replacement was a poor use of my time.

And think about it:  The board is $1100, EDK adds $500, and the DSP
bundle is another $1000.  And if you want full ISE with simulator, add
$3500.  Even with WebPack, that's $3600, percentage-wise, the
programmer doesn't add that much.

Just my opinion,
G.


Article: 134119
Subject: Re: Creating new operators
From: "Icky Thwacket" <it@it.it>
Date: Sat, 26 Jul 2008 17:50:42 +0100
Links: << >>  << T >>  << A >>

"rickman" <gnuarm@gmail.com> wrote in message 
news:f3419e72-2cf2-4a01-8300-c5184afc38f7@34g2000hsh.googlegroups.com...
> On Jul 26, 10:12 am, Frank Buss <f...@frank-buss.de> wrote:
>> rickman wrote:

>
> The process based description is not immediately clear to me at first
> glance.  I *do* have to think about it since that is not what I
> picture in my mind.  I visualize a MUX controlled by GenEn feeding an
> AND gate with BERTSel.  The Verilog like assignment maps exactly to
> that visualization.  The others require me to mentally convert the
> syntax from and IF statement to the AND gate not to mention the length
> of the code.  But like I said, it is not that this is hard to
> understand, it is not what I pictured in my mind and so I had to
> perform a conversion from the logic to the syntax.  That takes time
> and is a distraction from making my work accurate.
>
> I have no doubt that others may find that verbose code is easier for
> them to read.  But I find concise code is best (but not too!
> concise).  There are any number of different logic forms to be
> expressed and each is expressed best in different ways.  I think the
> selection statement is an operator that has a useful place in VHDL.
> I'm just sorry it wasn't included.  I guess it would have been hard to
> provide for overloading since it does not fit the standard uniary or
> binary format.
>
> Rick

So why do you not use schematic capture tools for your designs - or is that 
too uncool?

Icky 



Article: 134120
Subject: Re: Spartan-3A DSP 1800A Dev Board JTAG Cable and Programming Software
From: no.spam@gte.net (Scott Gravenhorst)
Date: Sat, 26 Jul 2008 17:56:24 GMT
Links: << >>  << T >>  << A >>
On Sat, 26 Jul 2008 09:38:02 -0700 (PDT), ghelbig <ghelbig@lycos.com>
wrote:

>On Jul 26, 5:37 am, no.s...@gte.net (Scott Gravenhorst) wrote:
>> I have a Spartan-3A DSP 1800A development board which comes with no
>> cable.  I understand that Xilinx makes a cable for $150 that works
>> with iMPACT.  There is also a 6 pin JTAG conntector on the board.
>>
>> I already know that the Digilent JTAG-USB cable will NOT work with
>> either iMPACT nor Adept.  Communication with Digilent indicates that
>> they may support this FPGA in the future, but it is currently not
>> supported.  I've also tried xilprg which does not yet support this
>> FPGA.
>>
>> I would like to find a more cost effective method than the Xilinx
>> cable.  I've read comments here and elsewhere that the Digilent
>> Parallel III cable is a clone of the Xilinx cable.  Does anyone know
>> if Will this cable (Digilent Parallel III) works with this board and
>> iMPACT or any other Windows based FPGA programmer software?  Or is
>> there a better solution?
>>
>> Many thanks.
>>
>> -- ScottG
>
>I started down that path; it bothered me to pay $200 for a simple USB
>dongle.
>
>The Xilinx programmer "just works".  If it doesn't, my friendly local
>FAE will fix that. I figured that I would be busy enough working on
>the real parts of the project that the half-week (or so) spent looking
>for a lower-cost replacement was a poor use of my time.
>
>And think about it:  The board is $1100, 

It's now $295.  With WebPACK ISE (which _will_ work with this FPGA),
it's still $295.  If the price of the board were still $1095 (which I
saw a while back on Xilinx), I probably never would have purchased the
board.  So you see, it wasn't that expensive and another $200 for a
cable or dongle is about 66% of the price of the board!  Hence why I'm
trying to do this a bit more economically.  

Even if a parallel cable or other less expensive method is slower -
I'd be happy.  And lack of ChipScope doesn't matter to me.  I'm not
doing this for some corporate project with a big budget, this is for
me, personally, for self education and personal projects.

>EDK adds $500, and the DSP
>bundle is another $1000.  And if you want full ISE with simulator, add
>$3500.  Even with WebPack, that's $3600, percentage-wise, the
>programmer doesn't add that much.
>
>Just my opinion,
>G.



Article: 134121
Subject: Re: Creating new operators
From: rickman <gnuarm@gmail.com>
Date: Sat, 26 Jul 2008 11:48:18 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 26, 12:50 pm, "Icky Thwacket" <i...@it.it> wrote:
> "rickman" <gnu...@gmail.com> wrote in message
>
> news:f3419e72-2cf2-4a01-8300-c5184afc38f7@34g2000hsh.googlegroups.com...
>
>
>
> > On Jul 26, 10:12 am, Frank Buss <f...@frank-buss.de> wrote:
> >> rickman wrote:
>
> > The process based description is not immediately clear to me at first
> > glance.  I *do* have to think about it since that is not what I
> > picture in my mind.  I visualize a MUX controlled by GenEn feeding an
> > AND gate with BERTSel.  The Verilog like assignment maps exactly to
> > that visualization.  The others require me to mentally convert the
> > syntax from and IF statement to the AND gate not to mention the length
> > of the code.  But like I said, it is not that this is hard to
> > understand, it is not what I pictured in my mind and so I had to
> > perform a conversion from the logic to the syntax.  That takes time
> > and is a distraction from making my work accurate.
>
> > I have no doubt that others may find that verbose code is easier for
> > them to read.  But I find concise code is best (but not too!
> > concise).  There are any number of different logic forms to be
> > expressed and each is expressed best in different ways.  I think the
> > selection statement is an operator that has a useful place in VHDL.
> > I'm just sorry it wasn't included.  I guess it would have been hard to
> > provide for overloading since it does not fit the standard uniary or
> > binary format.
>
> > Rick
>
> So why do you not use schematic capture tools for your designs - or is that
> too uncool?
>
> Icky

Is this a serious question?  Or are you just playing devil's
advocate?

Probably the single biggest reason to use an HDL instead of schematics
is the portability it provides.  Schematics have always locked you
into a manufacturer unless you are willing to reenter your design for
every company's chips you wish to try.

But I was a diehard on schematics.  Just like Ray Andraka, I saw a lot
of utility in them.  He finally switched when he found that he could
instantiate primitives and achieve the same degree of control over the
design details that he got with schematics.  I switched when I found
out how handy it was to have text based designs instead of proprietary
formatted schematics.  But there are any number of other reasons.  Do
you really not understand what they are?  I don't think I ever
considered schematics "uncool".  In fact, one of the cooler things
about being an engineer is having an E sized print of a schematic
design hanging on your wall.

Rick

Article: 134122
Subject: Re: Creating new operators
From: Frank Buss <fb@frank-buss.de>
Date: Sat, 26 Jul 2008 21:16:03 +0200
Links: << >>  << T >>  << A >>
rickman wrote:

> The process based description is not immediately clear to me at first
> glance.  I *do* have to think about it since that is not what I
> picture in my mind.  I visualize a MUX controlled by GenEn feeding an
> AND gate with BERTSel.  The Verilog like assignment maps exactly to
> that visualization.  The others require me to mentally convert the
> syntax from and IF statement to the AND gate not to mention the length
> of the code.  

For me it is more like a tree: The process form with the nested if
statements forms a tree, which I can see immediatly (maybe because I'm used
to program in Java and C), where the two main branches are selected by
BERTSel and the second branch is the mux. This is more clear for me than
using an AND gate.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Article: 134123
Subject: Re: Creating new operators
From: "Icky Thwacket" <it@it.it>
Date: Sat, 26 Jul 2008 20:26:01 +0100
Links: << >>  << T >>  << A >>

"rickman" <gnuarm@gmail.com> wrote in message 
news:6aaeaa92-c512-4f6a-b134-483bd7615592@m36g2000hse.googlegroups.com...
> On Jul 26, 12:50 pm, "Icky Thwacket" <i...@it.it> wrote:
>> "rickman" <gnu...@gmail.com> wrote in message

>>
>> So why do you not use schematic capture tools for your designs - or is 
>> that
>> too uncool?
>>
>> Icky
>
> Is this a serious question?  Or are you just playing devil's
> advocate?
>
> Probably the single biggest reason to use an HDL instead of schematics
> is the portability it provides.  Schematics have always locked you
> into a manufacturer unless you are willing to reenter your design for
> every company's chips you wish to try.
>
> But I was a diehard on schematics.  Just like Ray Andraka, I saw a lot
> of utility in them.  He finally switched when he found that he could
> instantiate primitives and achieve the same degree of control over the
> design details that he got with schematics.  I switched when I found
> out how handy it was to have text based designs instead of proprietary
> formatted schematics.  But there are any number of other reasons.  Do
> you really not understand what they are?  I don't think I ever
> considered schematics "uncool".  In fact, one of the cooler things
> about being an engineer is having an E sized print of a schematic
> design hanging on your wall.
>
> Rick

Yep that is a totally serious question.

An HDL gives you portability? - Are YOU serious?

If you are making the best use of the internal FPGA resources an HDL cannot 
give you portability, as soon as you instantiate a higher level hardware 
function integrated into the device (I am specifically talking DSP/SERDES 
type integration here) you are straight away locked into an vendor.

The only way an HDL remains 'portable' is if you work at the primitive 
level, something that I certainly am not prepared to do!

Icky



Article: 134124
Subject: Re: Creating new operators
From: Frank Buss <fb@frank-buss.de>
Date: Sat, 26 Jul 2008 21:44:37 +0200
Links: << >>  << T >>  << A >>
Icky Thwacket wrote:

> If you are making the best use of the internal FPGA resources an HDL cannot 
> give you portability, as soon as you instantiate a higher level hardware 
> function integrated into the device (I am specifically talking DSP/SERDES 
> type integration here) you are straight away locked into an vendor.

You can encapsulate vendor specific hardware functions in different
entieties in VHDL. I've seen this e.g. for memory on OpenCores projects,
which works for Altera and Xilinx without needing to change the main VHDL
entities.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de



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