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Messages from 134500

Article: 134500
Subject: Real port types in VHDL
From: yaseenzaidi@netzero.com
Date: Thu, 14 Aug 2008 01:52:08 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello all,

Which VHDL simulator with waveform analyzer supports real type ports?
Both ModelSim and NCSIM allow real type computations but are shy of
the real type ports.

Yaseen


Article: 134501
Subject: Re: Real port types in VHDL
From: Alan Fitch <alan.fitch@spamtrap.com>
Date: Thu, 14 Aug 2008 10:25:07 +0100
Links: << >>  << T >>  << A >>
yaseenzaidi@netzero.com wrote:
> Hello all,
> 
> Which VHDL simulator with waveform analyzer supports real type ports?
> Both ModelSim and NCSIM allow real type computations but are shy of
> the real type ports.
> 
> Yaseen
> 

There should be no problem. In fact I just tried it in modelsim and it 
worked.

The only issue is the initial value of real which is the maximum 
negative real number. If you then do something such as multiply two 
inputs, you exceed the valid range and get a run time error.

Here's my code which works,

Alan

entity e is
   port (i1,i2 : in real;
         o : out real);
end entity e;

architecture a of e  is

begin
    o <= i1 * i2;
  end architecture a;


entity etb is
end entity etb;

architecture bench of etb is

   signal i1, i2, o : real := 0.0; -- this is important to avoid overflow

begin

     u1 : entity work.e
       port map (i1 => i1,
                 i2 => i2,
                 o => o);

     process
       begin
         i1 <= 0.0;
         i2 <= 0.0;
         wait for 10 ns;
         i1 <= 1.1;
         i2 <= 2.2;
         wait for 10 ns;
         wait;
       end process;
     end architecture bench;


-- 
Alan Fitch

Article: 134502
Subject: Re: EBAY: XC2V1000-5FG456C
From: m <martin.usenet@gmail.com>
Date: Thu, 14 Aug 2008 05:57:58 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 8, 3:12=A0pm, austin <aus...@xilinx.com> wrote:
> m,
>
> That bit about not using them anymore is pretty suspicious. =A0Clicking o=
n
> other items you have for sale, it is odd that between nail guns and
> kayaks you just happen to have some FPGAs.
>
> Austin

Sorry, I guess I haven't checked this list in a little while...didn't
realize that all sorts of conspiracy theories were being cooked-up.

There's nothing wrong with these parts.  They are exactly as we
received them from Avnet.  They've been untouched.  Our outside sales
contact at Avnet is Loreen Bakoo, out of the Woodland Hills office.
And, of course, you can send private email to my gmail account and in
response I will identify myself and my company.  Nothing shady about
any of this.

Why are they on eBay?  We are migrating a design to V5SXT parts and
are left with a pile of V2's.  We discussed turning them in for credit
with Avnet/Norcomp but the suggestion was that we might do better
through other channels.  Hence eBay.  So, I created a sellers account
--I had bought but never sold anything before-- and put up a whole
pile of stuff that's been collecting dust.  Hence the new account, no
feedback, nailgun and rowing shell (not a kayak).  So, V2 over stock
got me to become an eBay seller.

Hey Austin, what's wrong with having nailguns and kayaks?  I have lots
of model airplanes too.  I was going to put a few of those engines up
on eBay as I switched to electric motors a long time ago and never
looked back.  There's life outside of FPGA's, you know?  What's cool
about eBay is that a garage full of neat stuff that remains unused
(probably par for the course for most engineers) can be turned into
funds to buy other toys to pile-up in the garage.  When I get a chance
I am going to put up everything from my stock of development boards to
fishing lures and see what happens.

Also, if Xilinx wants to take the V2's back and give us reasonable
credit I'd be very happy.  Contact Jim Hardy at Norcomp, he'll know
who you are talking about.  Just say that you are calling about giving
Martin credit for the V2 overstock he's got.  I'm sure he'll be
surprised.  :-)

-M






Article: 134503
Subject: Re: EBAY: XC2V1000-5FG456C
From: m <martin.usenet@gmail.com>
Date: Thu, 14 Aug 2008 06:12:23 -0700 (PDT)
Links: << >>  << T >>  << A >>
>  and don't seem to be selling what got stolen
> yesterday. =A0

Be careful with your comments Austin.  You could offend legitimate
customers.

> Sure, there are a lot of "garage sales" too. =A0Odd to have a
> nail gun, a kayak, and $15K of FPGAs and EPROMS in your garage...but it
> could certainly be legitimate (they own this stuff, and are getting rid
> of it).

I started the business in my garage.  Anything wrong with that?  We've
been out of the garage for many years, but that's were we came from.

At one point I had over $50K of your parts in my garage, along with
$15K of your development tools; a cleanroom setup I bought off NASA on
eBay and probably over $200K in other tools, components and finished
product.  It was a pretty expensive garage at one point.  Made me
nervous about going on vacations (like I took any!).


Anyhow, I am not offended, but I'd suggest that you might want to
contact the party in question and do a little research before posting
as you have.

> Since companies know that reselling their inventory
> violates our conditions for sale, they just don't do that (unless they
> are going out of business and they don't care any more).

Wow!  I've never seen this ANYWHERE!  Please have someone contact me
immediately with details.  How can you tell me what to do with
something I purchased and paid for?

It sure sounds like Xilinx needs to buy these back from me on two
accounts:  First, your posting here may have dissuaded interested
parties from buying them due to the implication that the parts might
be suspicious, stolen, bad, re-packaged or re-branded.  Second, if
some fine print I haven't seen can truly prevent us from selling
excess inventory, then I want a dollar-for-dollar credit towards the
V5 SXT parts we are about to order.

> This is very serious, and it could affect our reputation

Funny, that's exactly what I was thinking.


Private email to you with my full contact information for follow-up
follows.

-M


Article: 134504
Subject: Re: Using a Spartan 3 FPGA kit with a USB/DB9
From: cs_posting@hotmail.com
Date: Thu, 14 Aug 2008 08:44:56 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 12, 10:49 pm, Eric Smith <e...@brouhaha.com> wrote:
> Jason Hsu wrote:

> Note that Digilent's JTAG/USB cable does not work with the Xilinx Impact
> program.  You'll have to use Digilent's programming software or find other
> software that supports that cable.
>
> That also means that the Digilent cable doesn't support Xilinx Chipscope,
> or the EDK debugger.

My understanding is that there's a hack to make it work with impact
via the cable server mechanism in the sourceforge project at

http://sourceforge.net/project/showfiles.php?group_id=175344

however the usb cable related source file is not part of the default
project build, so it's not exactly turn-key.

Article: 134505
Subject: 512MB DDR2 533mhz registered dimms
From: jon <jon@pyramidemail.com>
Date: Thu, 14 Aug 2008 11:04:21 -0700 (PDT)
Links: << >>  << T >>  << A >>
I have more excess, but this time on 512MB DDR2 533mhz registered
dimms. I have a total of 4100 pcs of mixed inventory of Samsung,
Micron and Qimonda in original packaging, date codes less than one
year old.

SAMSUNG: M393T6450GZ3-CD5
MICRON: M18HTF6472Y-53EB2
QIMONDA: HYS72T64001HR-3.7-A

I will be able to supply below market price.

Jon E. Hansen
(949)864-7745
jon@pyramidemail.com

Article: 134506
Subject: Question on V4 HSPICE model
From: dudesinmexico <dudesinmexico@gmail.com>
Date: Thu, 14 Aug 2008 11:10:32 -0700 (PDT)
Links: << >>  << T >>  << A >>
In the HSPICE model for Xilinx Virtex4 output driver, I see this
'board_load'
subcircuit:

.subckt board_load rx tx vterm
TI145 tx vss rx vss   z0=50 td=2n
Rrx vterm rx   r=1000000
.ends board_load

The only form of documentation that Xilinx gives with the model is a
block diagram
where this subcircuit is labeled as "I/O standard dependent; modify as
necessary"
however it's not clear how it should be modified and what's its
function...
It seems to be related to an internal terminating resistance... any
ideas?

Thanks

Article: 134507
Subject: Re: Real port types in VHDL
From: Mike Treseler <mtreseler@gmail.com>
Date: Thu, 14 Aug 2008 11:14:06 -0700
Links: << >>  << T >>  << A >>
Alan Fitch wrote:

> Here's my code which works,

It does, but why the break with local traditions?  ;)

I inserted a few of these: report (real'image(o));
and I can see it in text:

# vsim -c etb
# Loading work.etb(bench)
# Loading work.real_port(synth)
VSIM 1> run
# ** Note: -1.000000e+308
#    Time: 0 ns  Iteration: 0  Instance: /etb
# ** Note: 0.000000e+00
#    Time: 10 ns  Iteration: 0  Instance: /etb
# ** Note: 2.420000e+00
#    Time: 20 ns  Iteration: 0  Instance: /etb
VSIM 2>

Thanks for the posting.

        -- Mike Treseler

Article: 134508
Subject: Re: Question on V4 HSPICE model
From: austin <austin@xilinx.com>
Date: Thu, 14 Aug 2008 14:53:26 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 14, 11:10=A0am, dudesinmexico <dudesinmex...@gmail.com> wrote:
> In the HSPICE model for Xilinx Virtex4 output driver, I see this
> 'board_load'
> subcircuit:
>
> .subckt board_load rx tx vterm
> TI145 tx vss rx vss =A0 z0=3D50 td=3D2n
> Rrx vterm rx =A0 r=3D1000000
> .ends board_load
>
> The only form of documentation that Xilinx gives with the model is a
> block diagram
> where this subcircuit is labeled as "I/O standard dependent; modify as
> necessary"
> however it's not clear how it should be modified and what's its
> function...
> It seems to be related to an internal terminating resistance... any
> ideas?
>
> Thanks

The instruction is to replace this external termination with the one
appropriate to the standard, or your own.

For example, ages ago, a standard load was 1K to ground, with a 50 pF
capacitor across it.

For most loads now, people use a transmission line into a 50 ohm load,
and some small parasitic capacitance, like 10 pF (no resistance).

If you want to see what the part will actually do on your board, use
the load that is really there (transmission line, and actual model of
the IO pin, with whatever external resistors you put there to prevent
reflections).

Austin Lesea

Article: 134509
Subject: Re: Microblaze Projects
From: Moazzam <moazzamhussain@gmail.com>
Date: Thu, 14 Aug 2008 22:14:33 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 13, 10:23=A0pm, Bryan <bryan.fletc...@avnet.com> wrote:
> On Aug 13, 7:27=A0am, taco <b...@joepie.org> wrote:
>
>
>
>
>
> > Ghazal wrote:
> > > Hello,
> > > =A0 =A0I am an engineer (relatively new one) )designing solutions usi=
ng
> > > FPGA's ... I came across Microblaze soft core processor from Xilinx
> > > and purchased EDK v9.2i .... Though there is much detail of its
> > > architecture and "features" at Xilinx site but there are not many
> > > examples and application notes for Microblaze ... I wanted to know
> > > more about its application, use and "real" benefits in commercial
> > > market.
> > > =A0 =A0Let me know if anyone here knows how and exactly where this so=
ft
> > > core processor is used (not only market but solutions/projects) and i=
s
> > > it any good.
> > > =A0 =A0Hope there are Microblaze "users" around !
> > > Ghazal Javed
>
> > I've worked with several other embedded FPGA softprocessors. Microblaze=
 is
> > exceptionally good because of the split development cycle for software =
and
> > fpga cores. Software can be patched into the core which makes the whole
> > development cycle very efficient. Although there are not very much
> > reference designs and the documentation is lacking in many ways, especi=
ally
> > when starting (I assume they want to push you to attend an expensive
> > course...) it's not difficult to get simple applications working in a s=
hort
> > time. I had some problems to get the installation working under linux, =
but
> > also this works fine now.
> > You can buy the spartan 3A dsp 1800 board for development (there were s=
ome
> > problems with other boards). For help you can always ask here.
> > Taco
>
> Besides the Xilinx site, you can find additional examples for many of
> the Xilinx Spartan boards on the Avnet Design Resource Center
> (www.em.avnet.com/drc). =A0The 1800A board mentioned by Taco has several
> MicroBlaze designs (www.em.avnet.com/spartan3a-dsp).
>
> Bryan- Hide quoted text -
>
> - Show quoted text -




Xilinx training course would be an excellent start up. You can find
the slides of Xilinx training course from Xilinx University program
website (It requires a registration). These slides will give you a
better idea about the possible markets of embedded processor and the
lab exercises will make you comfortable with the flow of steps & avoid
reading hundreds of literature pages.

Some basic lab exercise and slides are also available from :

http://www.eece.unm.edu/xup/workshop_edk.htm

Hope this helps,

/Moazzam


Article: 134510
Subject: Re: EBAY: XC2V1000-5FG456C
From: Rob <BertyBooster@googlemail.com>
Date: Fri, 15 Aug 2008 01:57:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 14, 1:12 pm, m <martin.use...@gmail.com> wrote:
> >  and don't seem to be selling what got stolen
> > yesterday.
>
> Be careful with your comments Austin.  You could offend legitimate
> customers.
>
> > Sure, there are a lot of "garage sales" too.  Odd to have a
> > nail gun, a kayak, and $15K of FPGAs and EPROMS in your garage...but it
> > could certainly be legitimate (they own this stuff, and are getting rid
> > of it).
>
> I started the business in my garage.  Anything wrong with that?  We've
> been out of the garage for many years, but that's were we came from.
>
> At one point I had over $50K of your parts in my garage, along with
> $15K of your development tools; a cleanroom setup I bought off NASA on
> eBay and probably over $200K in other tools, components and finished
> product.  It was a pretty expensive garage at one point.  Made me
> nervous about going on vacations (like I took any!).
>
> Anyhow, I am not offended, but I'd suggest that you might want to
> contact the party in question and do a little research before posting
> as you have.
>
> > Since companies know that reselling their inventory
> > violates our conditions for sale, they just don't do that (unless they
> > are going out of business and they don't care any more).
>
> Wow!  I've never seen this ANYWHERE!  Please have someone contact me
> immediately with details.  How can you tell me what to do with
> something I purchased and paid for?
>
> It sure sounds like Xilinx needs to buy these back from me on two
> accounts:  First, your posting here may have dissuaded interested
> parties from buying them due to the implication that the parts might
> be suspicious, stolen, bad, re-packaged or re-branded.  Second, if
> some fine print I haven't seen can truly prevent us from selling
> excess inventory, then I want a dollar-for-dollar credit towards the
> V5 SXT parts we are about to order.
>
> > This is very serious, and it could affect our reputation
>
> Funny, that's exactly what I was thinking.
>
> Private email to you with my full contact information for follow-up
> follows.
>
> -M

Touche ;-)

Article: 134511
Subject: Re: Development board with SD card.
From: cs_posting@hotmail.com
Date: Fri, 15 Aug 2008 08:00:52 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 8, 4:09 pm, "Pete Fraser" <pfra...@covad.net> wrote:
> I'm looking for an FPGA (any flavor) development board
> with an SD card socket connected to the FPGA.
>
> It must have all the pins connected (not just SPI mode).

In a pinch you can solder wires directly to the SD card to get a
prototype working, though of course then you can't remove it to
preload data with a PC.  Er, well, you can and use solder braid to
clean the contacts ;-)


Article: 134512
Subject: video timing with TFP410
From: stewarma@gmail.com
Date: Fri, 15 Aug 2008 13:13:04 -0700 (PDT)
Links: << >>  << T >>  << A >>
I want to implement 1280x1024but cannot synthesize an 108MHz pixel
block for the timing.  I would prefer to use a 100 MHz (generated from
200) but can also make a 104 or 112 Mhz.

Normal 1280x1024 timing:
Horizontal
Resolution pixels: 1280
Front porch pixels: 48
Sync pulse pixels: 112
Back porch pixel: 248
Veritcle
Resolution lines: 1024
Front porch lines: 1
Sync pulse lines: 3
Back porch lines: 38

Has anyone had any experience altering the porch/sync lengths and
pixel clock to keep 60Hz that will sync to an LCD monitor?

Thanks!

Article: 134513
Subject: Re: video timing with TFP410
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 15 Aug 2008 13:32:35 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 15, 1:13=A0pm, stewa...@gmail.com wrote:
> I want to implement 1280x1024but cannot synthesize an 108MHz pixel
> block for the timing. =A0I would prefer to use a 100 MHz (generated from
> 200) but can also make a 104 or 112 Mhz.
>
> Normal 1280x1024 timing:
> Horizontal
> Resolution pixels: 1280
> Front porch pixels: 48
> Sync pulse pixels: 112
> Back porch pixel: 248
> Veritcle
> Resolution lines: 1024
> Front porch lines: 1
> Sync pulse lines: 3
> Back porch lines: 38
>
> Has anyone had any experience altering the porch/sync lengths and
> pixel clock to keep 60Hz that will sync to an LCD monitor?
>
> Thanks!

What's your real question? What's the FPGA device?
With a Virtex DCM you can generate all sorts of frequencies around 104
MHz with ~0.2 MHz granularity.
Peter Alfke

Article: 134514
Subject: Q: Demo Altera NIOS II SOPC limitations
From: MarkAren <markaren10@yahoo.com>
Date: Fri, 15 Aug 2008 13:37:25 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi All,

I have just compiled a NIOS II core into Cyclone I part (I was given
an old MJL demo board) and compiled some trivial C. Everything seems
to work as advertised.

I still haven't figured out the time limited nature of the NIOS II
SOPC builder, could someone enlighten me please. There seems to be a
60 minute limit between creating the FPGA code (Verilog) and compiling
a new FPGA image, or does that limit apply to time between compiling
an image and programming a part ?

Also, what is the difference between the web edition and the fully
paid up version of Quartus II.

All tools above are V7.2.

I am only experimenting at the moment and I need to understand the
limitations of the tool chain before I invest too much more time and
effort in this educational project,.

Many thanks,

Mark


Article: 134515
Subject: Re: video timing with TFP410
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 15 Aug 2008 14:06:46 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 15, 1:32=A0pm, Peter Alfke <pe...@xilinx.com> wrote:
> On Aug 15, 1:13=A0pm, stewa...@gmail.com wrote:
>
>
>
> > I want to implement 1280x1024but cannot synthesize an 108MHz pixel
> > block for the timing. =A0I would prefer to use a 100 MHz (generated fro=
m
> > 200) but can also make a 104 or 112 Mhz.
>
> > Normal 1280x1024 timing:
> > Horizontal
> > Resolution pixels: 1280
> > Front porch pixels: 48
> > Sync pulse pixels: 112
> > Back porch pixel: 248
> > Veritcle
> > Resolution lines: 1024
> > Front porch lines: 1
> > Sync pulse lines: 3
> > Back porch lines: 38
>
> > Has anyone had any experience altering the porch/sync lengths and
> > pixel clock to keep 60Hz that will sync to an LCD monitor?
>
> > Thanks!
>
> What's your real question? What's the FPGA device?
> With a Virtex DCM you can generate all sorts of frequencies around 104
> MHz with ~0.2 MHz granularity.
> Peter Alfke

To generate 108 MHz, you multiply 100 MHz by 27 and simultaneously
divide by 25, all in one pass through the DCM.
With Virtex DCMs you need not worry about the 2.7 GHz, because they
never get generated internally. It's all done mathematically...
Peter Alfke

Article: 134516
Subject: Re: Q: Demo Altera NIOS II SOPC limitations
From: Ben Jackson <ben@ben.com>
Date: Fri, 15 Aug 2008 21:52:50 GMT
Links: << >>  << T >>  << A >>
On 2008-08-15, MarkAren <markaren10@yahoo.com> wrote:
>
> I still haven't figured out the time limited nature of the NIOS II
> SOPC builder, could someone enlighten me please.

It's 60 minutes of runtime on the part without the JTAG cable
connected.  If you keep the JTAG connection live then you can run
forever.

> Also, what is the difference between the web edition and the fully
> paid up version of Quartus II.

I think NIOS II is sold separately from the subscription Quartus II.
I think you buy NIOS one time and you have a perpetual license for that
version.

It's neat, and I've used the tethered version, but when I built a
Cyclone II project I just threw down a microcontroller rather than use
NIOS II.  $500 will buy a lot of micros.  I think their pricing
model is a mistake -- it keeps hobbiests from doing anything serious
with NIOS II and that keeps those same people from being able to
recommend it for "serious" designs, where the license fee is a drop in
the bucket compared to part sales.

-- 
Ben Jackson AD7GD
<ben@ben.com>
http://www.ben.com/

Article: 134517
Subject: Re: Q: Demo Altera NIOS II SOPC limitations
From: ghelbig <ghelbig@lycos.com>
Date: Fri, 15 Aug 2008 14:53:12 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 15, 1:37=A0pm, MarkAren <markare...@yahoo.com> wrote:
> Hi All,
>
> I have just compiled a NIOS II core into Cyclone I part (I was given
> an old MJL demo board) and compiled some trivial C. Everything seems
> to work as advertised.
>
> I still haven't figured out the time limited nature of the NIOS II
> SOPC builder, could someone enlighten me please. There seems to be a
> 60 minute limit between creating the FPGA code (Verilog) and compiling
> a new FPGA image, or does that limit apply to time between compiling
> an image and programming a part ?
>
> Also, what is the difference between the web edition and the fully
> paid up version of Quartus II.
>
> All tools above are V7.2.
>
> I am only experimenting at the moment and I need to understand the
> limitations of the tool chain before I invest too much more time and
> effort in this educational project,.
>
> Many thanks,
>
> Mark

As I recall, the time limit starts after downloading the FPGA.

I was told that the difference between 'web' and 'full' was the number
(size) of devices supported.

I'm pretty sure that all of this is documented on the Altera web site.

G.

Article: 134518
Subject: Re: video timing with TFP410
From: Ben Jackson <ben@ben.com>
Date: Fri, 15 Aug 2008 21:54:52 GMT
Links: << >>  << T >>  << A >>
On 2008-08-15, stewarma@gmail.com <stewarma@gmail.com> wrote:
> Has anyone had any experience altering the porch/sync lengths and
> pixel clock to keep 60Hz that will sync to an LCD monitor?

Most digital devices like LCDs seem fairly insensitive to the size of
the blanking intervals.  I suspect there is at least SOME logic inside
which uses a few of those clocks for something, but 50 vs 60 lines of
blank are no big deal.

-- 
Ben Jackson AD7GD
<ben@ben.com>
http://www.ben.com/

Article: 134519
Subject: Re: EBAY: XC2V1000-5FG456C
From: rickman <gnuarm@gmail.com>
Date: Fri, 15 Aug 2008 21:15:31 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Aug 14, 9:12 am, m <martin.use...@gmail.com> wrote:
> >  and don't seem to be selling what got stolen
> > yesterday.
>
> Be careful with your comments Austin.  You could offend legitimate
> customers.
>
> > Sure, there are a lot of "garage sales" too.  Odd to have a
> > nail gun, a kayak, and $15K of FPGAs and EPROMS in your garage...but it
> > could certainly be legitimate (they own this stuff, and are getting rid
> > of it).
>
> I started the business in my garage.  Anything wrong with that?  We've
> been out of the garage for many years, but that's were we came from.
>
> At one point I had over $50K of your parts in my garage, along with
> $15K of your development tools; a cleanroom setup I bought off NASA on
> eBay and probably over $200K in other tools, components and finished
> product.  It was a pretty expensive garage at one point.  Made me
> nervous about going on vacations (like I took any!).
>
> Anyhow, I am not offended, but I'd suggest that you might want to
> contact the party in question and do a little research before posting
> as you have.
>
> > Since companies know that reselling their inventory
> > violates our conditions for sale, they just don't do that (unless they
> > are going out of business and they don't care any more).
>
> Wow!  I've never seen this ANYWHERE!  Please have someone contact me
> immediately with details.  How can you tell me what to do with
> something I purchased and paid for?
>
> It sure sounds like Xilinx needs to buy these back from me on two
> accounts:  First, your posting here may have dissuaded interested
> parties from buying them due to the implication that the parts might
> be suspicious, stolen, bad, re-packaged or re-branded.  Second, if
> some fine print I haven't seen can truly prevent us from selling
> excess inventory, then I want a dollar-for-dollar credit towards the
> V5 SXT parts we are about to order.
>
> > This is very serious, and it could affect our reputation
>
> Funny, that's exactly what I was thinking.
>
> Private email to you with my full contact information for follow-up
> follows.


It seems like Austin is ignoring this request for contact.  The OP did
not appreciate my post and we have been discussing this privately.  I
guess I have to have some sympathy for him.  My only complaint with
him was that I don't like this group being used for selling, but it
seems like this thread has turned into a discussion of valid usage of
Xilinx parts.  It also seems to be about some of the very strongly
worded comments by Austin.

I guess this does not affect everyone, but it certainly makes Xilinx
look bad to imply that a customer is trying to sell stolen merchandise
on eBay.  I would expect there would be a major effort on the part of
Xilinx to resolve this as quickly as possible.

Rick

Article: 134520
Subject: Re: Development board with SD card.
From: Antti <Antti.Lukats@googlemail.com>
Date: Sat, 16 Aug 2008 00:22:35 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 15 aug, 18:00, cs_post...@hotmail.com wrote:
> On Aug 8, 4:09 pm, "Pete Fraser" <pfra...@covad.net> wrote:
>
> > I'm looking for an FPGA (any flavor) development board
> > with an SD card socket connected to the FPGA.
>
> > It must have all the pins connected (not just SPI mode).
>
> In a pinch you can solder wires directly to the SD card to get a
> prototype working, though of course then you can't remove it to
> preload data with a PC. =A0Er, well, you can and use solder braid to
> clean the contacts ;-)

the nice trick is to use SD to miniSD adapter
so you solder to the adapter pads and you can remove the miniSD (or
microSD)

Antti

Article: 134521
Subject: Verilog modules and stimulus in same file
From: laserbeak43 <laserbeak43@gmail.com>
Date: Sat, 16 Aug 2008 01:43:19 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,
i have some verilog code that i want to keep for future use as a part
of a library.
I have created the module and am working on the stimulus. if i were to
put the
module and stimulus in the same file, would this cause problems in the
future if
i try to load the module from the file?

Article: 134522
Subject: Verilog modules and stimulus in same file: oh and one more thing...
From: laserbeak43 <laserbeak43@gmail.com>
Date: Sat, 16 Aug 2008 01:46:04 -0700 (PDT)
Links: << >>  << T >>  << A >>
oh, and for that matter, what's the verilog equivalent of the Ansi C
"static" keyword?

Thanks
Malik

Article: 134523
Subject: Re: Verilog modules and stimulus in same file: oh and one more thing...
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Sat, 16 Aug 2008 10:44:44 +0100
Links: << >>  << T >>  << A >>
On Sat, 16 Aug 2008 01:46:04 -0700 (PDT), laserbeak43 wrote:

>oh, and for that matter, what's the verilog equivalent of the Ansi C
>"static" keyword?

Which meaning of "static"?

static = lexically local variable of a function,
which therefore is in fact a global variable whose
name is visible only within the function scope:
all local variables of Verilog-95 tasks and functions
have this behaviour.  Only by declaring your Verilog
tasks or functions to be "automatic" do you get
argument and local variables created dynamically 
per call.

static = global (file-scope) declaration that is 
not published outside the file: no such thing in 
Verilog.  Everything is public and the names get 
resolved at elaboration time.  In particular, 
module names all get thrown into one common namespace
(although the library/configuration machinery of
Verilog-2001 somewhat messes with that idea); and
there are no other top-level declarations apart from
modules.

-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 134524
Subject: Re: Verilog modules and stimulus in same file
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Sat, 16 Aug 2008 10:56:11 +0100
Links: << >>  << T >>  << A >>
On Sat, 16 Aug 2008 01:43:19 -0700 (PDT), laserbeak43
<laserbeak43@gmail.com> wrote:

>Hi,
>i have some verilog code that i want to keep for future use as a part
>of a library.
>I have created the module and am working on the stimulus. if i were to
>put the
>module and stimulus in the same file, would this cause problems in the
>future if
>i try to load the module from the file?

I don't know what you mean by "load the module from the file".
If you put a design module and a testbench module in the same
file, then whenever the compiler processes that file it will
compile both modules.

For many typical Verilog tool flows, you give the compiler 
a bunch of files which it concatenates to form one big 
source stream.  All modules in that source stream get
compiled.  Some of those modules instantiate others.
Any module that is *not* so instantiated is considered
to be a top-level module, and therefore the root of an
instance hierarchy tree.  Verilog can happily simulate
more than one such instance hierarchy in a single simulation
run.  For example:

~~~~~~~~~~ file F1.v ~~~~~~~~~~~~~

module design;
  ...
endmodule

module design_tb;
  ...
  design design_instance();
  ...
endmodule


~~~~~~~~~~~~ file F2.v ~~~~~~~~~~~~~~

module the_real_top_level;
  ...
  design design_2();
  ...
endmodule

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Give these two files to the compiler and it will find
three modules: the_real_top_level, design, and
design_tb.  Two of those modules - the_real_top_level
and design_tb - are not instantiated by other modules.
Consequently the following hierarchy will be constructed:

[top of simulation]
  |
  +--- unnamed instance of the_real_top_level
  |       |
  |       +--- instance "design_2" of design
  |
  +--- unnamed instance of design_tb
          |
          +--- instance "design_instance" of design

Is that a problem for you?

Some tools allow you to compile files individually,
putting the compiled modules into a "library" in some
tool-dependent way; you can then choose which top-level
module(s) in that library you wish to simulate, and the
tool will construct the hierarchy from that.  So, for 
example, in ModelSim I might do this:

  vlog F1.v ; # compile file F1
  vlog F2.v ; # compile file F2
  vsim the_real_top_level

and that will build this hierarchy:

[top of simulation]
  |
  +--- unnamed instance of the_real_top_level
          |
          +--- instance "design_2" of design

Finally, you may be giving yourself problems with synthesis
because (I assume) at some stage you want to synthesise the
design, but not the testbench module.

The conclusion from all of this should surely be obvious:
ONE MODULE PER FILE is almost always the sensible way
to organise your Verilog source code.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.



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