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On Jan 1, 5:31=A0pm, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Wed, 31 Dec 2008 18:48:36 -0800 (PST), bish <bishes...@gmail.com> > wrote: > > On Wed, 31 Dec 2008 18:48:36 -0800 (PST), in comp.arch.fpga you wrote: > >I had a successful behavioral simulation of the design with modelsim > >invoked from xilinx's ise9.2i. > >Error:Xst:528 - Multi-source in Unit <moving_window> on signal > ><w23<4>> > >Sources are: > >Output port RAMB16BWER:DOB16 of instance <windowing1/fifo1/BU2/U0/ > >gen_as.fgas/normgen.memblk/bmem.bmg.bmg_inst/blk_mem_generator/ > >valid.cstr/ramloop[0].ram.r/v2.ram/dp36x36.ram> > >Signal <windowing1/w23<4>> in Unit <moving_window> is assigned to GND > > >I don't understand how w23 is being assigned to GND and therefore why > >multi-source here. > > Perhaps applying the Modelsim "Drivers" command to Signal > <windowing1/w23<4>> would help trace the problem. > Thanks Brian, but w23 and w13 are nowhere assigned accept in concurrent statement w23 <=3D a23 w13 <=3D a13 However, I found the problem. Technically there is no problem in the code I provided in my original post. Actually, I had tried to synthesize the design before I had reached to this final version of the code. At that time there were some other mistakes in the code which resulted ise to issue above errors. I had modified and checked with behavioral simulation and repeated the process until I got required result in behavioral simulation. Then when I tried to synthesized by double clicking synthesize in ise, I don't know why, but it did nothing and kept on having the same messages and reports it had made during the first time I tried to synthesize. Earlier I thought that these were updated messages when it tried to synthesize but it was not to be which I realized after seeing the detailed synthesis report which did not reflect several changes in my code. Finally I found it, so opened a new project, imported required files and then synthesized and hurray everything is working fine now. > - BrianArticle: 137201
On Jan 1, 7:31 am, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote: > I have tried to classify a few different ways to optimize a design > for an FPGA. I have tried to keep the categories fairly general > without going into too much details. Comments (both positive and > negative) would be appreciated. > > 1 Pipelining > * A must in almost any FPGA design. Relatively cheap to do since > flip-flops are usually abundant. This is not very FPGA specific > though, but usually an ASIC design doesn't have to be pipelined > as much as an FPGA design is. > 2 Utilizing FPGA resources efficiently > 2.1 Change the design to use as much of the FPGA LUTs as possible. > * For example, a 32-bit adder/subtracter takes up the same amount > of space as a plain 32-bit adder. Sometimes you might have to > instantiate LUTs, flip-flops, carry-chains, etc manually to > do this. > 2.2 Utilizing memories efficiently. > * For example, if your design will be more efficient by utilizing > both ports of a block RAM you should probably do so. Using > distributed memories, shift registers, etc efficiently. > 2.3 Utilizing DSP blocks efficiently > * Change the architecture of your design to be able to take > maximum advantage of the DSP blocks. For example, if you have a > DSP processor with 4 accumulation registers this will not map > very well to a Virtex-4 DSP48 block which only have one accumulation > register. (Although this can be fixed by using result forwarding and > utilizing a register file outside the DSP48 block.) > 2.4 Utilizing other embedded FPGA resources > * Embedded processors, serializers/deserializers, DLLs/PLLs, etc > 3. Manual floorplanning > * Either through RLOCs or graphical tools > 4. Manual routing > * Not very common but can be a powerful tool to meet timing in extreme > situations. > 5. Partial reconfiguration > * Not very common yet but has a potential to save a lot of area if > certain parts of a design are not needed all the time. > 6. <Insert your comment here> :) > > Have I forgotten something very important here? > > And by the way, is there any definitive book one should read to learn > more about how to optimize a design for an FPGA? I have looked at many > FPGA books but most books only seem to cover fairly introductory > material. > > I have looked at for example "Digital Signal Processing with Field > Programmable Gate Arrays (Signals and Communication Technology)" but > this book doesn't really have that much FPGA material. (Although it has > a lot of nice DSP material.) > > Another book, "Advanced FPGA Design" by Steve Kilts was a decent text for > intermediate designers but I'm not sure I would have called it "Advanced". > > At the moment I have probably had more use of some of the postings on this > newsgroup than most of the FPGA related books I have looked at however :) > > /Andreas One thing you could add is to adjust your design to fully utilize the FFs. Often more LUTs are needed than FFs and some deigns can be changed to use more FFs. The only example I can think of is the tradeoff between fanout of a signal from a single FF vs reducing the fanout by using multiple copies of the FF and putting some of the fanout before the FF. This reduces delay because the total fanout is the multiple of the individual fanouts with less total delay than the fanout if done all at once. As long as you are listing resources to be fully utilized, you should list clock distribution. Clock lines can be used for high fanout signals and the tools often do this automatically, but sometimes you need to instantiate the clock driver. Those are my suggestion, but I don't actually get your post. The entire section on using resources efficiently is just a list of the resources saying "use efficiently". That is not really a technique, it is a goal. The manual floorplanning and routing, to me, are things to be avoided since they are brand specific (or even family specific), very labor intensive and make design rework very difficult. Partial reconfiguration is not really a useful tool and is only supported by one vendor, if you can call what they are doing with it "support". I have tried to use modular reconfiguration (a subset of partial reconfiguration) for a long time and never found it to be ready for prime time, mainly because it is not supported in the affordable FPGA families. In fact, I read a paper once that talked about optimization as being "evil". Optimization is something you do only when necessary because it takes a lot more time to do, the added complexity can create bugs, it can make debugging more difficult and it makes design changes and updates more difficult. All in all, optimization increases the cost of the product life cycle significantly. Listing optimizations is of some value, but without details of how they can be useful, it is still just a list. When, where and how do you see dual port memories efficient in place of a single port memory? How can DSP blocks be used in place of other logic? When does an adder/subtracter improve on a simple adder? When do you take the leap of using manual routing and floorplanning? What type of application would efficiently utilize partial reconfiguration (or even modular reconfiguation)? My answer to that last one is a design I did that used an FPGA to interface to daughter cards (DC). There were a number of daughter cards with different hardware and different interfaces. The design in the FPGA needed to load one module for each DC. The initial module would be able to read a serial I/O pin to determine the DC type. Then the appropriate interface module could be loaded for each DC as required. Why was this important? Because there were planned around a dozen DC types and the main board had four DC slots. Do the math and you will see that the permutations are ***HUGE***. In theory, modular configuration would have reduced the design to a single module for the processor interface and a module for each DC type. Since this was not really a viable approach, instead of being able to supply a main board with variable combinations of DCs along with a generic set of software and FPGA modules, there were unique FPGA loads for each customer's DC combinations which were no fun trying to maintain. Maybe I am just sour on the promise of partial reconfiguration, but I see very little use for it, not because it can't work, but because it has never been treated like a real development tool by the vendors. In general, I think that in volume production there is little technical reason for utilizing FPGAs versus other logic. The real reason is just economic. FPGAs have gotten so cheap that many devices cost more than the FPGAs that are replacing them, especially when they are replaced several in one design. Even the issue of firmware updates (a common justification for using FPGAs vs ASICs) is mostly useful for the initial production and is often never used in a final product yet FPGAs are often used in place of ASICs. Technical issues actually are just not so important in selecting FPGAs except for a minority of designs. In the old days I would be putting on my asbestos suit to get ready for the vendor response. But that doesn't happen anymore. In some ways, I miss the old days... at least it was never boring. :^) RickArticle: 137202
Guy_FPGA wrote: > what to do? how do I create a sof file that contains both the HW and > SW? Where is your software located? Internal/extenal memory? Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 137203
On Dec 31 2008, 6:57=A0pm, "MM" <mb...@yahoo.com> wrote: > Hi Antti, > > Try disabling cache if it is enabled. > Try increasing the stack. > > Also, take a look at the old GSRD reference design using MPMC and LL_TEMA= C. > It used to work quite reliably but it was long time ago since I tried it > last time. > > /Mikhail I-Cache is enabled D-Cache is disabled, but i think the D-Cache invalidate calls are made, so its good idea to remove them (or check they are not called) AnttiArticle: 137204
On Dec 31 2008, 11:14=A0pm, ga...@allegro.com (Gavin Scott) wrote: > Antti <Antti.Luk...@googlemail.com> wrote: > > PC sends very little amount of small UDP > > packets that are responded by FPGA > > I'm wondering if greatly increasing the volume of packets going from > the PC to the FPGA would make the problem reproduce faster, etc. =A0Do > you have the flexibility to change the PC side to increase or even > flood it with status checks or some noop command? > > G. it seems to have relation yes, when demo app is running on PC the failure happens in longer time, when the real app is running failure seems to happen earlier. The real app sends more packets to FPGA I have not tried flooding yet, but i have monitored the Rx/Tx buffer descriptor list fill level, when working there is NEVER more than 1 incoming packet in the buffer chain so there is no slow overflow of the buffer descriptor chain AnttiArticle: 137205
"Andreas Ehliar" <ehliar-nospam@isy.liu.se> wrote in message news:slrnglpqn8.pk4.ehliar-nospam@sabor.isy.liu.se... >I have tried to classify a few different ways to optimize a design > for an FPGA. I have tried to keep the categories fairly general > without going into too much details. Comments (both positive and > negative) would be appreciated. > > 1 Pipelining > * A must in almost any FPGA design. Relatively cheap to do since > flip-flops are usually abundant. This is not very FPGA specific > though, but usually an ASIC design doesn't have to be pipelined > as much as an FPGA design is. 1.1 Use Multicycle path if results are not required every clockcycle, might save you some power as well. > 2 Utilizing FPGA resources efficiently > 2.1 Change the design to use as much of the FPGA LUTs as possible. > * For example, a 32-bit adder/subtracter takes up the same amount > of space as a plain 32-bit adder. Sometimes you might have to > instantiate LUTs, flip-flops, carry-chains, etc manually to > do this. > 2.2 Utilizing memories efficiently. > * For example, if your design will be more efficient by utilizing > both ports of a block RAM you should probably do so. Using > distributed memories, shift registers, etc efficiently. > 2.3 Utilizing DSP blocks efficiently > * Change the architecture of your design to be able to take > maximum advantage of the DSP blocks. For example, if you have a > DSP processor with 4 accumulation registers this will not map > very well to a Virtex-4 DSP48 block which only have one accumulation > register. (Although this can be fixed by using result forwarding and > utilizing a register file outside the DSP48 block.) > 2.4 Utilizing other embedded FPGA resources > * Embedded processors, serializers/deserializers, DLLs/PLLs, etc > 3. Manual floorplanning > * Either through RLOCs or graphical tools 3.1 Use a Physical Synthesis tool to squeeze out that last ns. > 4. Manual routing > * Not very common but can be a powerful tool to meet timing in extreme > situations. > 5. Partial reconfiguration > * Not very common yet but has a potential to save a lot of area if > certain parts of a design are not needed all the time. > 6. <Insert your comment here> :) 6. Investigate if your critical path is not a false path. 7. Use a different synthesis tool :-) Hans www.ht-lab.com > > > > Have I forgotten something very important here? > > And by the way, is there any definitive book one should read to learn > more about how to optimize a design for an FPGA? I have looked at many > FPGA books but most books only seem to cover fairly introductory > material. > > I have looked at for example "Digital Signal Processing with Field > Programmable Gate Arrays (Signals and Communication Technology)" but > this book doesn't really have that much FPGA material. (Although it has > a lot of nice DSP material.) > > Another book, "Advanced FPGA Design" by Steve Kilts was a decent text for > intermediate designers but I'm not sure I would have called it "Advanced". > > > At the moment I have probably had more use of some of the postings on this > newsgroup than most of the FPGA related books I have looked at however :) > > > /AndreasArticle: 137206
On Jan 1, 12:06=A0pm, bish <bishes...@gmail.com> wrote: [snip] > Finally I found it, so opened a new project, imported required files > and then synthesized and hurray everything is working fine now. > > > - Brian The next time you run into this sort of issue with ISE, try to "clean up project files" before you go to the trouble of creating a new project. This very often fixes this type of problem for the newer versions of ISE. Regards, GaborArticle: 137207
On Wed, 31 Dec 2008 13:07:00 -0800 (PST), Digi Suji
<digisuji@gmail.com> wrote:
>Hi,
>
>I have a chip top which has an 8-bit output "out[7:0]". I am
>implementing it on a BASYS board which uses Xilinx Spartan 3E. I would
>like to see the 8-bit output on the seven segment LED display. How can
>I do this?
>
>Do I need to add any additional Verilog code to do this? Please help.
>
>Thanks,
According to the BASYS reference manual
(http://www.digilentinc.com/Data/Products/BASYS/BASYS_C_rm.pdf) the
board has 8 individual LEDs. The ref manual shows they are connected
to GND, so setting an LED pin HI ('1') will light the LED. So in your
upper level code, connect "out[7:0]" to "leds[7:0]". You will need to
check the UCF file for the exact pin names.
The 7-segment display is multiplexed, which means that for example,
segment A of each digit is connected together, and there is a separate
control/enable pin for each digit. Chances are there is code on the
Digilent web site, or provided with the board, to drive the LED
display.
-Dave Pollum
Article: 137208On Jan 1, 6:58=A0am, Guy_FPGA <guy...@hotmail.com> wrote: > Hello there, > > I've just migrated from Xilinx to Altera. Using the NIOS IDE I've > created a system with working SW. > I would like to program the on-board EPCS flash so on power up the > FPGA is programed with the right HW and SW. > > I read that I need to convert the sof file to jic. OK, but what about > the software - as I noticed the sof only contains the HW. > > what to do? how do I create a sof file that contains both the HW and > SW? I don't know the details, but I believe there is a way to modify the bitstream with the SW. The NIOS tools should have a way to output the binary data in a file format that can be loaded into the SOF file. I don't know if there is a special tool for this or if it is part of the bitstream generation in Quartus. But the whole point of the process is that you don't have to recompile the HDL code again, just a final step in generating the bitstream. Did you nose around in the NIOS documentation a bit? I am sure they give you the info you need somewhere. RickArticle: 137209
rickman wrote: >> >> I read that I need to convert the sof file to jic. OK, but what about >> the software - as I noticed the sof only contains the HW. >> >> what to do? how do I create a sof file that contains both the HW and >> SW? > > I don't know the details, but I believe there is a way to modify the > bitstream with the SW. The NIOS tools should have a way to output the > binary data in a file format that can be loaded into the SOF file. I > don't know if there is a special tool for this or if it is part of the > bitstream generation in Quartus. But the whole point of the process > is that you don't have to recompile the HDL code again, just a final > step in generating the bitstream. Did you nose around in the NIOS > documentation a bit? I am sure they give you the info you need > somewhere. > If the software is located in internal memory, then you can use either a memory initialization file (MIF) or an Intel hex file to initialize it; you can configure that in the Megawizard or with equivalent parameter declarations. If the software lives in *external* memory, then there is no place for it in the SOF, and you have to arrange for the external memory to be programmed through some means or another -- which may involve downloading a design to the FPGA which can accept data over jtag and then program the external memory with it. -hpaArticle: 137210
On Jan 3, 2:07=A0am, Gabor <ga...@alacron.com> wrote: > On Jan 1, 12:06=A0pm, bish <bishes...@gmail.com> wrote: > > [snip] > > > Finally I found it, so opened a new project, imported required files > > and then synthesized and hurray everything is working fine now. > > > > - Brian > > The next time you run into this sort of issue with ISE, try > to "clean up project files" before you go to the trouble of > creating a new project. =A0This very often fixes this type > of problem for the newer versions of ISE. > Thanks for the tip, Gabor. > Regards, > GaborArticle: 137211
Hi All, I have having problems with a simple 15 bit counter being un-reliable - various bits in the top byte appear to change as the bottom byte crosses the 0x00 / 0xFF boundary. This sounds like a ground bounce (or similar) problem to me. Hardware is new and unproven, I have tightened up the ground planes with some copper foil to no avail. Dev environment is Quartus II 8.1 web edition and design is a mix of Verilog and schematic capture. I am now trying to switch off all of the Turbo bits in the device. The design will tolerate being clocked at 10MHz, so nothing is moving very fast. I have found the Turbo bit attribute in the assignment editor so I should be able to slow down I/O slew rate. Current pin settings are "<bit name>, Turbo Bit, Off, Yes". as well as the assignment of location and pin number. Nothing I have done so far seems to have affected overall power consumption (I am expecting about a 30% reduction when I move to power save / no Turbo mode). The data sheet for the MAX7k implies that every macro cell has a Turbo bit - is there a global setting to set the whole device into low power mode by default ? Any other places I should be poking about in Quartus to find more power saving features ? Many thanks, MarkArticle: 137212
On Jan 2, 9:41=A0pm, "H. Peter Anvin" <h...@zytor.com> wrote: > rickman wrote: > > >> I read that I need to convert the sof file to jic. OK, but what about > >> the software - as I noticed the sof only contains the HW. > > >> what to do? how do I create a sof file that contains both the HW and > >> SW? > > > I don't know the details, but I believe there is a way to modify the > > bitstream with the SW. =A0The NIOS tools should have a way to output th= e > > binary data in a file format that can be loaded into the SOF file. =A0I > > don't know if there is a special tool for this or if it is part of the > > bitstream generation in Quartus. =A0But the whole point of the process > > is that you don't have to recompile the HDL code again, just a final > > step in generating the bitstream. =A0Did you nose around in the NIOS > > documentation a bit? =A0I am sure they give you the info you need > > somewhere. > > If the software is located in internal memory, then you can use either a > memory initialization file (MIF) or an Intel hex file to initialize it; > you can configure that in the Megawizard or with equivalent parameter > declarations. =A0If the software lives in *external* memory, then there i= s > no place for it in the SOF, and you have to arrange for the external > memory to be programmed through some means or another -- which may > involve downloading a design to the FPGA which can accept data over jtag > and then program the external memory with it. I understand how this works in general, but specifically, what software is used to initialize the SOF? Is this done in the final step of bit file generation? I am thinking this is a way to take the output of an HDL compilation, which is just done once and adding the program data which can change many times as the software is debugged. Is there a separate program that does this or is is part of Quartus? RickArticle: 137213
rickman wrote: > > I understand how this works in general, but specifically, what > software is used to initialize the SOF? Is this done in the final > step of bit file generation? I am thinking this is a way to take the > output of an HDL compilation, which is just done once and adding the > program data which can change many times as the software is debugged. > Is there a separate program that does this or is is part of Quartus? > It's part of Quartus; in particular, it's the "Assembly" phase. If you have smart compilation turned on, all the previous steps will be automatically skipped. You can also run the Quartus assembler from the command line. -hpaArticle: 137214
Hello, I wrote a state machine instead of the 'example driver' Altera provides to read and write using the DDR Controller Megafunction to the 8MB SDRAM on the DE2. I hardcoded the address and write data to troubleshoot. For a read - I provide the address and the read request signal until local_ready goes high. Then I wait for rdata_valid to be asserted. Once rdata valid is asserted I copy the data that I can view in Signal Tap. For a write - I provide the address and the data continuously and assert the write_req until local_ready goes high. When controller asserts wdata_request - addr, data and byte enable (all 1s) is provided. I use signal tap to view: read request, write request, rdata_valid, wdata_req, wdata, rdata, addr. This apparently seems to work except that when I write to a location, wait write to complete and then read from the same location - The written and the read data does not match. I am hopelessly stuck since Christmas on this problem. Could anybody guess what may be wrong? I can provide the top level module if somebody is interested in reviewing it for me. I do not want to paste it here and clutter these boards. Thank you! MarsalaArticle: 137215
Hai all, Can anyone suggest which third party synthesis tool can able to generate time limited(evaluation) netlist file. for example it should generate a netlist of the design and expires say after 30 days. Pls help how this can be achieved...whether I should be entirely dependent on synthesis tool or should i create a timeout logic in the design ? .Pls provide examples or links if u know. regards, rajeshArticle: 137216
"raj" <rajesh.obli@gmail.com> wrote in message news:8de33488-e064-4394-b020-885bb9c3d1d5@s9g2000prg.googlegroups.com... > Hai all, > > Can anyone suggest which third party synthesis tool can able to > generate time limited(evaluation) netlist file. > > for example it should generate a netlist of the design and expires say > after 30 days. > > Pls help how this can be achieved...whether I should be entirely > dependent on synthesis tool or should i create a timeout logic in the > design ? > > .Pls provide examples or links if u know. > > > regards, > rajesh AFAIK no synthesis and/or P&R tool can do this, you would need an FPGA with a build-in time-out primitive to support this. I also believe there is no simple generic way to implement a time-out function. What about supplying a simulation model, custom evaluation board etc? Hans www.ht-lab.comArticle: 137217
On Sat, 3 Jan 2009 04:46:58 -0800 (PST), raj <rajesh.obli@gmail.com> wrote: >Hai all, > >Can anyone suggest which third party synthesis tool can able to >generate time limited(evaluation) netlist file. > >for example it should generate a netlist of the design and expires say >after 30 days. > >Pls help how this can be achieved...whether I should be entirely >dependent on synthesis tool or should i create a timeout logic in the >design ? > >.Pls provide examples or links if u know. If you use encrypt your netlist and use a pli function, you maybe able to generate something similar to what you want. Basically you need to embed the release time/date in your design (it just doesn't have to netlist, it could rtl, etc.) and check with the pli function which returns the current time/date to be compared and verified against the length of time allowed for simulation. You can even distribute keys (small files) which your model can read to extend the length of simulation etc. Maybe P1735 (IP Encryption) will help implement a similar feature but you don't have to wait for it. Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 137218
On Jan 3, 2:49=A0pm, Muzaffer Kal <k...@dspia.com> wrote: > On Sat, 3 Jan 2009 04:46:58 -0800 (PST), raj <rajesh.o...@gmail.com> > wrote: > > >Hai all, > > >Can anyone suggest which third party synthesis tool can able to > >generate time limited(evaluation) netlist file. > > >for example it should generate a netlist of the design and expires say > >after 30 days. > > >Pls help how this can be achieved...whether I should be entirely > >dependent on synthesis tool or should i create a timeout logic in the > >design ? > > >.Pls provide examples or links if u know. > > If you use encrypt your netlist and use a pli function, you maybe able > to generate something similar to what you want. Basically you need to > embed the release time/date in your design (it just doesn't have to > netlist, it could rtl, etc.) and check with the pli function which > returns the current time/date to be compared and verified against the > length of time allowed for simulation. You can even distribute keys > (small files) which your model can read to extend the length of > simulation etc. Maybe P1735 (IP Encryption) will help implement a > similar feature but you don't have to wait for it. > Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Serviceshttp://www.dspia.com I'm not sure that covers the original question which implies a synthesizable design. Do you want to allow the netlist to be loaded into hardware but stop working after some time? This certainly requires the timeout to be implemented within your netlist. Otherwise you can make the file unusable after some date, but existing designs would still work in the hardware. Regards, GaborArticle: 137219
rickman <gnuarm@gmail.com> writes: > I understand how this works in general, but specifically, what > software is used to initialize the SOF? Is this done in the final Usually your hex file will be compiled together with your HDL. In your software loop you can then compile your NIOS stuff and keep the hex or mif files in their same locations and then run: quartus_cdb --update_mif projectname in order to merge the hex/mif file into the sof file. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 137220
HT-Lab wrote: > > AFAIK no synthesis and/or P&R tool can do this, you would need an FPGA with > a build-in time-out primitive to support this. I also believe there is no > simple generic way to implement a time-out function. > > What about supplying a simulation model, custom evaluation board etc? > Some vendors use an encrypted netlist, which contains a "kill counter" - the design dies X seconds/minutes/hours/days after it was first loaded. That's probably the closest... -hpaArticle: 137221
>Some vendors use an encrypted netlist, which contains a "kill counter" - >the design dies X seconds/minutes/hours/days after it was first loaded. What breaks if the bad guy sets his clock back? (and disconnects the network cable) The only defense I can see is requiring some sort of confirmation over the network. Would you buy one of those? If you were a CAD tool vendor, would you sigh up to support that sort of stuff? It gets "interesting". Even if the CAD tool vendors do support it, there has to be some sort of encryption on the "can I use this" channel or the bad guy can just build a server that responds "OK". Even if the CAD tool vendors do support it, their tooks can be patched to bypass that sort of check. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 137222
Hal Murray wrote: >> Some vendors use an encrypted netlist, which contains a "kill counter" - >> the design dies X seconds/minutes/hours/days after it was first loaded. > > What breaks if the bad guy sets his clock back? (and disconnects the > network cable) > > The only defense I can see is requiring some sort of confirmation > over the network. Would you buy one of those? If you were a CAD > tool vendor, would you sigh up to support that sort of stuff? > > It gets "interesting". Even if the CAD tool vendors do support it, > there has to be some sort of encryption on the "can I use this" > channel or the bad guy can just build a server that responds "OK". > > Even if the CAD tool vendors do support it, their tooks can be > patched to bypass that sort of check. > That's why the kill counter doesn't deal with absolute time, only with X number of clock cycles after FPGA initialization. The purpose of it is to let the IP be used for long enough to be used for evaluation, but not be a reliable product for actual use. -hpaArticle: 137223
On Jan 2, 10:20=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > On Dec 31 2008, 11:14=A0pm, ga...@allegro.com (Gavin Scott) wrote: > > > Antti <Antti.Luk...@googlemail.com> wrote: > > > PC sends very little amount of small UDP > > > packets that are responded by FPGA > > > I'm wondering if greatly increasing the volume of packets going from > > the PC to the FPGA would make the problem reproduce faster, etc. =A0Do > > you have the flexibility to change the PC side to increase or even > > flood it with status checks or some noop command? > > > G. > > it seems to have relation yes, when demo app is running on PC > the failure happens in longer time, when the real app is running > failure seems to happen earlier. The real app sends more > packets to FPGA > > I have not tried flooding yet, but i have monitored the Rx/Tx > buffer descriptor list fill level, when working there is NEVER > more than 1 incoming packet in the buffer chain > so there is no slow overflow of the buffer descriptor chain > > Antti I hope I have finally found the real issue... a few days ago i had a "ISSUE LIST" in excel table where i note the possible issues, their probability, methods of testing, etc.. the table had 26 items. but one VERY important item was missing, something that should always be on the list: "stupid software bug" how could i had it missing on my list? the original software is not written by me, neither it is very good or robust or tested but.. it has been reported as working 100% in some occasions, so i assumed there is no systematic problem with it. (all assumptions are to be considered false) but, the RX BD list is initialized once!!! ONCE!! the software does not write the buflen any more after the initialization so the BD list gets dirty and is never cleaned/released. DMA will write num_received into buflen (what was previously set 2048) this buflen is after that no longer modified, neither the stats field i truly hope this is the problem. if not then next item to check on my list is DCM chaining introduced jitter making some unexplained odd behaviour for the MPMC/DMA/DDR2... i hope it is not the DCM jitter problem. Antti PS and if somebody thinks i should have seen it earlier? i compared some of the code with Xilinx example code and there was also no BD reinit, so i did not check deeper in the drivers. But the drivers cant do that part, so the code is really just missing.Article: 137224
MarkAren wrote:
> I have having problems with a simple 15 bit counter being un-reliable
> - various bits in the top byte appear to change as the bottom byte
> crosses the 0x00 / 0xFF boundary.
> This sounds like a ground bounce (or similar) problem to me.
This sounds like asynchronous logic to me.
> Hardware is new and unproven, I have tightened up the ground planes
> with some copper foil to no avail.
> Dev environment is Quartus II 8.1 web edition and design is a mix of
> Verilog and schematic capture.
Maybe there are some unregistered outputs.
> Any other places I should be poking about in Quartus to find more
> power saving features ?
I would get the design working before
worrying about milliamps.
Good luck.
-- Mike Treseler
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