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Actually I think it might be the rocket booster that might get released first. I wanted to do solar panel test in synchronous orbit. Much more of this family soon. John Adair Enterpoint Ltd. On 12 Nov, 15:13, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Tue, 11 Nov 2008 06:40:59 -0800 (PST), John Adair > > <g...@enterpoint.co.uk> wrote: > >Schematics and pin constraints files are now available from Polmaddie1 > >product page =A0http://www.enterpoint.co.uk/cpld_boards/polmaddie1.html. > > >Pricing information has also been added to the engineering webpage and > >these boards are now fully available. The product is also now in our > >shop but currently miss-spelled and miss-sectioned but is on discount > >for anyone that can find it there. Stock indication is also wrong on > >the shop currently but that should be sorted out within the next few > >hours. > > Looks good! > > I am disappointed, however, that the Polmaddie2 has neither a coin slot > nor a cup dispenser. However, I expect these are in the works. > > - BrianArticle: 136351
In comp.arch.fpga, o0o0ozd@gmail.com <o0o0ozd@gmail.com> wrote: > Hi, > I have a design which is supposed to run fine at 200mhz according to > xilinx ise, but when i load the design to the fpga and try to run it > at 200 mhz, it doesn't run correctly and generates false results. > Behavioral simulation works correctly, and also weird thing is when i > use a slower clock, fpga gives the correct results,too. Fpga is a > virtex4sx35, and 100mhz clock is generated by a programmable clock > chip and i use dcm to get a 200mhz clock. I am kind of a new fpga > programmer and this is the first time i have seen a problem like this, > usually ise gives a timing error, but this time according to ise, > everything is perfect. > this is the timing constraint i use: > NET clka period = 10 ns; > clka is fed to the dcm. This is a constraint for your 100MHz clock, but don't you need to add a constraint for the 200MHz clock as well? (clkb period = 5 ns...) ISE should also report what the maximum allowable clock is, what does it say? (multiple clocks?) -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) Always be sincere, even when you don't mean it. -Irene PeterArticle: 136352
On Nov 10, 2:01=A0am, atu...@gmail.com wrote: > I have a XST board v3.0 with a spartan XCS3100c. i want to use that > board to transfer the data from and to the PC using USB. can you > please help me with some demo program that explains the use of USB for > sending the data. I dont know what connections to make. please tell me > from scratch. > > thanks in advance > > atul Have you contacted Xess to see if they can help you? -Dave PollumArticle: 136353
On 12 Kas=FDm, 17:45, Stef <stef...@yahooI-N-V-A-L-I-D.com.invalid> wrote: > In comp.arch.fpga, > > o0o0...@gmail.com <o0o0...@gmail.com> wrote: > > Hi, > > I have a design which is supposed to run fine at 200mhz according to > > xilinx ise, but when i load the design to the fpga and try to run it > > at 200 mhz, it doesn't run correctly and generates false results. > > Behavioral simulation works correctly, and also weird thing is when i > > use a slower clock, fpga gives the correct results,too. Fpga is a > > virtex4sx35, and 100mhz clock is generated by a programmable clock > > chip and i use dcm to get a 200mhz clock. I am kind of a new fpga > > programmer and this is the first time i have seen a problem like this, > > usually ise gives a timing error, but this time according to ise, > > everything is perfect. > > this is the timing constraint i use: > > NET clka period =3D 10 ns; > > clka is fed to the dcm. > > This is a constraint for your 100MHz clock, but don't you need to add > a constraint for the 200MHz clock as well? (clkb period =3D 5 ns...) > ISE should also report what the maximum allowable clock is, what does > it say? (multiple clocks?) > > -- > Stef =A0 =A0(remove caps, dashes and .invalid from e-mail address to repl= y by mail) > > =A0 Always be sincere, even when you don't mean it. -Irene Peter Not sure either, but this is the constraint generated by ise: PERIOD analysis for net "Inst_dcm4/CLK2X_BUF" derived from NET "Inst_dcm4/CLKIN_IBUFG_OUT" PERIOD =3D 10 ns HIGH 50% and it says: Best Case Achievable is 4.999 ns. for this constraint.Article: 136354
On 12 Kas=FDm, 15:05, Sean Durkin <news_no...@tuxroot.de> wrote: > o0o0...@gmail.com wrote: > > and I will still check the IOB option but I use another clock(pci > > clock) to transfer the data. Basically, I have a tree-search algorithm > > which has to run fast(200mhz) and i have another slow algorithm which > > transfers the result through pci. I have a 2-ff synchronizers in > > between. Data is 128-bit long and i use 32-bit registers to send it. > > Design works at 100mhz, used to work at 150mhz when the logic was > > smaller. Bits in the middle change faster than the bits at the both > > ends of the 128-bit number, and these middle bits are the wrong ones. > > I have nothing so any comment,hint, reply is appreciated. > > I'd suggest using an asynchronous FIFO for this. A synchronizer with > two flipflops ist fine for single control signals (at least most of the > time, but even then there's a whole lot of things to consider), but data > busses should be handled differently. The easiest method is just using a > FIFO, you can generate one that fits your needs with CoreGen and > instantiate it in your design. > > So what I'd use is is a FIFO that you write to with 200MHz and read out > with 33MHz (or whatever your PCI clock is). You may need a little extra > logic (like a small state machine or something like that) to check the > control signals (FIFO full/empty and such), but it's not really a big > deal and a this is certainly a "clean" solution. Downside is you need a > few BRAMs, depending on how deep the FIFO needs to be. But you can just > generate one with CoreGen and how many it needs. > > HTH, > Sean > > -- > My email address is only valid until the end of the month. > Try figuring out what the address is going to be after that... I have seen a similar comment before which says dont use synchronizers for data buses. I thought what is the big deal:) we will see, i ll try the fifo tomorrow, thanks for the advice.Article: 136355
On Nov 12, 8:45=A0pm, Stef <stef...@yahooI-N-V-A-L-I-D.com.invalid> wrote: > In comp.arch.fpga, > > o0o0...@gmail.com <o0o0...@gmail.com> wrote: > > Hi, > > I have a design which is supposed to run fine at 200mhz according to > > xilinx ise, but when i load the design to the fpga and try to run it > > at 200 mhz, it doesn't run correctly and generates false results. > > Behavioral simulation works correctly, and also weird thing is when i > > use a slower clock, fpga gives the correct results,too. Fpga is a > > virtex4sx35, and 100mhz clock is generated by a programmable clock > > chip and i use dcm to get a 200mhz clock. I am kind of a new fpga > > programmer and this is the first time i have seen a problem like this, > > usually ise gives a timing error, but this time according to ise, > > everything is perfect. > > this is the timing constraint i use: > > NET clka period =3D 10 ns; > > clka is fed to the dcm. > > This is a constraint for your 100MHz clock, but don't you need to add > a constraint for the 200MHz clock as well? (clkb period =3D 5 ns...) > ISE should also report what the maximum allowable clock is, what does > it say? (multiple clocks?) > > -- > Stef =A0 =A0(remove caps, dashes and .invalid from e-mail address to repl= y by mail) > > =A0 Always be sincere, even when you don't mean it. -Irene Peter If you constrain the DCM input clock, it will automatically takes care of the DCM derived clock's constraint i.e. 200MHz. You can check this in the translate phase of design implementation. -- vasuArticle: 136356
o0o0ozd@gmail.com wrote: > I have seen a similar comment before which says dont use synchronizers > for data buses. > I thought what is the big deal:) Basically, with the two-ff-synchronizer you're never sure when exactly you'll get the result in the destination clock domain. Depending on when the data comes in, you might or might not have to wait an additional clock cycle. For single control or status signals this is usually acceptable. But if you have a data bus, it can happen that the delays for the bits in that bus are different. So you might have another clock cycle of latency on some bits but not on others, which obviously will cause problems. What you can do is put a comparator in there that compares the registered values behind the two synchronizer stages. Only if that comparator finds the values are identical you generate a "valid" flag that tells the other logic that the data is now stable and can be read. But still there's a few things to consider there... When you use a FIFO, everything's been taken care off and you don't have to worry about any of those things. The only thing you should make sure is that the inputs and outputs of the FIFO should be registered. There shouldn't be any combinatorial signals going into the data inputs and the outputs should be registered as well before using them. HTH, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 136357
Hello everybody, We have a problem with platform cable usb II (model dlc10) that came with the spartan 3a dsp embedded platform microblaze edition. We had used it initially to check if everything is ok with the board as suggested in starter guide and some user guides. Everything worked fine. Then we had a vacation for about a month and we packed the board and was not used. Well now when we connected it with the target board the led keeps on glowing with amber color but no green color. And while trying to download bitstream, error occurs like cable not detected. Hope to get answers for: i) We checked the vref from the target board which was ok. We don't have a clue of what could be wrong!! ii) Further is there any way of checking whether the board is ok downloading any bitstream to the fpga. And can we use anything other than this platform cable usb to configure the fpga in Spartan 3a 1800a dsp board. Being a student, it was with great difficulty (financially) that we acquired the board and now just when our project was going really well, we seem to be in deep trouble.Article: 136358
Dear All, I can see in the documentation on the Sparton 3A that it has a FF placed near the output pin. I would like to use this to ensure that the output from a BUS is 100% in sync so routing don't affect the timing. Is there a ATTRIBUTE to give the signal or how do I tell the router to use this last FF? I'm using ISE 10.1 Thank you in advance! Regards Jan From rgaddi@technologyhighland.com Wed Nov 12 11:17:22 2008 Path: flpi142.ffdc.sbc.com!flpi088.ffdc.sbc.com!prodigy.com!flpi089.ffdc.sbc.com!prodigy.net!bigfeed.bellsouth.net!bigfeed2.bellsouth.net!news.bellsouth.net!news.glorb.com!Xl.tags.giganews.com!border1.nntp.dca.giganews.com!nntp.giganews.com!local02.nntp.dca.giganews.com!nntp.lmi.net!news.lmi.net.POSTED!not-for-mail NNTP-Posting-Date: Wed, 12 Nov 2008 13:17:19 -0600 Date: Wed, 12 Nov 2008 11:17:22 -0800 From: Rob Gaddi <rgaddi@technologyhighland.com> Newsgroups: comp.arch.fpga Subject: Re: Using the FF @ Port pin Message-Id: <20081112111722.57f917d6.rgaddi@technologyhighland.com> References: <491b270a$0$90276$14726298@news.sunsite.dk> Organization: Highland Technology, Inc. X-Newsreader: Sylpheed 2.5.0 (GTK+ 2.10.14; i686-pc-mingw32) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Lines: 27 X-Usenet-Provider: http://www.giganews.com NNTP-Posting-Host: 66.117.134.49 X-Trace: sv3-z4sFHxk8Iz2ETYOpbyJMt28pwSwewG5qBa7TXf6hCejvcpXbXNpU1h/9B9j+lvWC8MOCDQZp4rokIVk!SxiDRjBCBUQJqY5cy2ECm8csBcqLg6IEwwxx1pNMJMYEYz1bQC6/VvhnBSR9xbbzbNYJWqi+u46q!iHRFSv9AMRK88akoX0c= X-Abuse-and-DMCA-Info: Please be sure to forward a copy of ALL headers X-Abuse-and-DMCA-Info: Otherwise we will be unable to process your complaint properly X-Postfilter: 1.3.39 Xref: prodigy.net comp.arch.fpga:149251 X-Received-Date: Wed, 12 Nov 2008 14:17:20 EST (flpi142.ffdc.sbc.com) On Wed, 12 Nov 2008 19:55:14 +0100 Jan <webpjat@future-design_DELETE.dk> wrote: > Dear All, > > I can see in the documentation on the Sparton 3A that it has a FF > placed near the output pin. I would like to use this to ensure that > the output from a BUS is 100% in sync so routing don't affect the > timing. > > Is there a ATTRIBUTE to give the signal or how do I tell the router > to use this last FF? > > I'm using ISE 10.1 > > Thank you in advance! > > Regards > Jan You're looking for the IOB attribute. That said, in my experience, the tools do a pretty aggressive job of moving things that can be pushed into the IOB flops into them just on the default AUTO setting. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 136359
1stderivative@gmail.com wrote:
> Hi - I was using this Bluespec for one of the FPGA implementations.
> Havent done the implementation yet, so no comments on that. The
> question is why people use Bluespec rather than Verilog.
Do they?
The web site lists partners, but few customer.
Last press release was June 08.
> Bluespec
> coding takes quite more time, more complex with the syntax, the rules
> and functions (though very useful). One thing I didnt like was the
> multiple firing of variables.
>
> Please comment on how better Bluespec is.
Never heard of it.
Let's see:
http://www.bluespec.com/forum/download.php?id=107
Looks sort of like system verilog.
It generates plain verilog on the backend.
Have a look at the code example on pg 65.
Looks spare, but not very clear to me.
Unfortunately, there is no simulation
at this level.
Look at the generated RTL verilog on
the following pages. That is what
I would have to debug. And if the
company goes out of business,
that is my source code.
-- Mike Treseler
Article: 136360On Nov 12, 2:17=A0pm, Rob Gaddi <rga...@technologyhighland.com> wrote: > On Wed, 12 Nov 2008 19:55:14 +0100 > > > > Jan <webpjat@future-design_DELETE.dk> wrote: > > Dear All, > > > I can see in the documentation on the Sparton 3A that it has a FF > > placed near the output pin. I would like to use this to ensure that > > the output from a BUS is 100% in sync so routing don't affect the > > timing. > > > Is there a ATTRIBUTE to give the signal or how do I tell the router > > to use this last FF? > > > I'm using ISE 10.1 > > > Thank you in advance! > > > Regards > > =A0 =A0Jan > > You're looking for the IOB attribute. =A0That said, in my experience, the > tools do a pretty aggressive job of moving things that can be pushed > into the IOB flops into them just on the default AUTO setting. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order That may be true, but if you assign "IOB =3D TRUE" you will get a warning if this doesn't happen for the flip-flop in question. A bit easier than scanning a large output bus in the FPGA editor.Article: 136361
On Nov 13, 7:55=A0am, Jan <webpjat@future-design_DELETE.dk> wrote: > I can see in the documentation on the Sparton 3A that it has a FF placed > =A0 near the output pin. I would like to use this to ensure that the > output from a BUS is 100% in sync so routing don't affect the timing. Hi Jan, In theory, you shouldn't need to force the tools to do it. You should have an "offset out" timing constraint (along with period constaints on clks) so then its up to the tools to do what is necessary to meet that timing. I.e. let the tools decide if they need to use the IOB or not. If you don't use an offset out constraint and manually force the flop into the IOB with an attribute, you can get caught out if the tools decide to silently ignore your attribute some time in the future. On the other hand, if the tools fail to meet a timing constaint the problem is obvious (I regard the timing report as a must check item before releasing a binary FPGA image.) (If its a large bus, one advantage of not having all bits change at the same time is less simultaneously switching output(SSO) noise. The FPGA datasheet has SSO guidelines...) Cheers AndrewArticle: 136362
Brian Drummond wrote: > My conclusion: it does look like incorrect synthesis from 7.1 (and > possibly other old XST versions) but it has clearly been fixed in 10.1, > so I believe any further effort on this case is a waste of time. Interesting, thanks for the follow-up! Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 136363
Andrew FPGA wrote:
> On Nov 13, 7:55 am, Jan <webpjat@future-design_DELETE.dk> wrote:
>> I can see in the documentation on the Sparton 3A that it has a FF placed
>> near the output pin. I would like to use this to ensure that the
>> output from a BUS is 100% in sync so routing don't affect the timing.
>
> Hi Jan,
> In theory, you shouldn't need to force the tools to do it. You should
> have an "offset out" timing constraint (along with period constaints
> on clks)>
> (If its a large bus, one advantage of not having all bits change at
> the same time is less simultaneously switching output(SSO) noise. The
> FPGA datasheet has SSO guidelines...)
Thank you. That is very good advices! Why didn't I think of the that?
:-) I'll try the offset constraint.
My bus is quite large, so I think I'll try to look into the SSO.
Regards
Jan
Article: 136364On Thu, 13 Nov 2008 10:40:04 +1100, Mark McDougall <markm@vl.com.au> wrote: >Brian Drummond wrote: > >> My conclusion: it does look like incorrect synthesis from 7.1 (and >> possibly other old XST versions) but it has clearly been fixed in 10.1, >> so I believe any further effort on this case is a waste of time. > >Interesting, thanks for the follow-up! Any further developments on your odd results? For example, have you had a chance to try on 10.1, even Webpack? - BrianArticle: 136365
Brian Drummond wrote: > Any further developments on your odd results? > For example, have you had a chance to try on 10.1, even Webpack? Not yet, no. I'm wholly involved in Altera development at work atm, so any Xilinx stuff is "extra curricular activities". Yet to install v10... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 136366
On 12 Kas=C4=B1m, 18:14, o0o0...@gmail.com wrote: > On 12 Kas=C3=BDm, 15:05, Sean Durkin <news_no...@tuxroot.de> wrote: > > > > > o0o0...@gmail.com wrote: > > > and I will still check the IOB option but I use another clock(pci > > > clock) to transfer the data. Basically, I have a tree-search algorith= m > > > which has to run fast(200mhz) and i have another slow algorithm which > > > transfers the result through pci. I have a 2-ff synchronizers in > > > between. Data is 128-bit long and i use 32-bit registers to send it. > > > Design works at 100mhz, used to work at 150mhz when the logic was > > > smaller. Bits in the middle change faster than the bits at the both > > > ends of the 128-bit number, and these middle bits are the wrong ones. > > > I have nothing so any comment,hint, reply is appreciated. > > > I'd suggest using an asynchronous FIFO for this. A synchronizer with > > two flipflops ist fine for single control signals (at least most of the > > time, but even then there's a whole lot of things to consider), but dat= a > > busses should be handled differently. The easiest method is just using = a > > FIFO, you can generate one that fits your needs with CoreGen and > > instantiate it in your design. > > > So what I'd use is is a FIFO that you write to with 200MHz and read out > > with 33MHz (or whatever your PCI clock is). You may need a little extra > > logic (like a small state machine or something like that) to check the > > control signals (FIFO full/empty and such), but it's not really a big > > deal and a this is certainly a "clean" solution. Downside is you need a > > few BRAMs, depending on how deep the FIFO needs to be. But you can just > > generate one with CoreGen and how many it needs. > > > HTH, > > Sean > > > -- > > My email address is only valid until the end of the month. > > Try figuring out what the address is going to be after that... > > I have seen a similar comment before which says dont use synchronizers > for data buses. > I thought what is the big deal:) > we will see, i ll try the fifo tomorrow, thanks for the advice. I spoke too early, using fifo instead of synchronizers didn't solve my problem. Although, it still returns incorrect results at 200 mhz, there is some improvement. Before it didnt work at speeds higher than 100mhz, now after adding the fifo, it works at 180mhz clock speed.Article: 136367
Uwe, Timing analysis is, by design, agnostic of the boolean values of signals. In your example, timing analysis detects two paths: z (q pin) @clk -> out (we pin) @ clk*2 -- I'm assuming z is a FF clocked by clk, to illustrate a 'short' path x_clk (q pin) @clk -> out (we pin) @ clk*2 -- through func combinational logic, to illustrate a 'long' path The path from x is the most critical, because of the combinational delay (function func). So, what is reported is legitimate and expected. Now, as the designer, you have additional information, since you understand the logic behavior of the circuit. In this case, the multiplexer will actually block the x_clk@clk -> out@clk*2 path (letting through the z@clk -> out@clk*2). Consequently, the path from x_clk is actually exercised every other edge of clk*2, and more specificaly the edges aligned with clk edges. This path is thus a pure multicycle path of 2 cycles of the destination clk*2. All you need is traditional multicycle path constraint from x_clk to out: TIMESPEC TS_x_to_out = FROM FFS(x_clk) to FFS(out) TS_CLK; -- where TS_CLK is the PERIOD constraint for the clk clock. I hope that helps, - gaelArticle: 136368
Hi, I just got an XC5VFX70T-FF1136 here on my desk, planning to put it on my self-designed board. I am just wondering what max. speed I can expect for my internal logic. The speed grade is -1 and I need to design logic running up to 582 MHz. Should I rather buy a speed grade -2 to be on the safe side or isn't that an issue? Regards SaulArticle: 136369
On 13 Nov, 11:35, "Saul Bernstein" <jiffyl...@freenet.de> wrote: > Hi, > > I just got an XC5VFX70T-FF1136 here on my desk, planning to put it on my > self-designed board. I am just wondering what max. speed I can expect for my > internal logic. The speed grade is -1 and I need to design logic running up > to 582 MHz. Should I rather buy a speed grade -2 to be on the safe side or > isn't that an issue? What is your internal logic? JonArticle: 136370
"Jon Beniston" <jon@beniston.com> wrote: > > What is your internal logic? > It is not as simple as it may seem to describe the internal structure and operation of the internal logic. There are many different ways to implement the logical functions and these surely contribute to the max. frequency. But in the end it is all about some simple control loops and simple image processing algorithms. Nothing complicated.Article: 136371
On Thu, 13 Nov 2008 01:04:08 -0800 (PST), o0o0ozd@gmail.com wrote: >> > > and I will still check the IOB option but I use another clock(pci >> > > clock) to transfer the data. Basically, I have a tree-search algorithm >> > > which has to run fast(200mhz) and i have another slow algorithm which >> > > transfers the result through pci. I have a 2-ff synchronizers in >> > > between. Data is 128-bit long and i use 32-bit registers to send it. >> > > Design works at 100mhz, used to work at 150mhz when the logic was >> > > smaller. Bits in the middle change faster than the bits at the both >> > > ends of the 128-bit number, and these middle bits are the wrong ones. >> > > I have nothing so any comment,hint, reply is appreciated. >> I have seen a similar comment before which says dont use synchronizers >> for data buses. >> I thought what is the big deal:) >> we will see, i ll try the fifo tomorrow, thanks for the advice. >I spoke too early, using fifo instead of synchronizers didn't solve my >problem. Although, it still returns incorrect results at 200 mhz, >there is some improvement. Before it didnt work at speeds higher than >100mhz, now after adding the fifo, it works at 180mhz clock speed. I'm not convinced this is a problem with FIFOs or synchronisers per se. Re: data bus; the last thing you want is a synchroniser on the data bus itself. However, synchronisers on the control logic around it are definitely worthwhile: (a) they guarantee (to a very high probability) the data transfer signals are valid and (b) because they take an additional cycle over the data latch, they guarantee the data is stable. Fifos my be an easier option. I'm guessing some blind spot in the timing constraints, which is coming out in both cases. You can run static timing analysis on unconstrained paths and see if there are any surprises (the development system reference guide has information on running TRCE aka the timing analyser in more detail than the main flow) Or add "From:To" constraints between your clock domains, and between FFs and RAMs, and check that you have added the correct signals to each time group. (From long ago, I remember some blind spots in the "period" analysis that were caught by constraints From: FFs To: BRAMS and vice versa; these may be correctly covered now) See the Constraints Guide for more info on these. - BrianArticle: 136372
Well, if your using ISIM I'm sure none of what I am about to write will be anything new. I see three main problems with ISIM. It throws exceptions It flat out will not simulate, almost like it lost the test bench It runs out of memory All these appear to be random and not tied to the project. It does appear that it has something to do with me editing the waveforms but I can't say 100%. Once one of these errors happens, the error happens every time I try to restart ISIM. Restarting ISE and rebooting the PC also have no effect. What I am finding is that if I blow away all of the temp files within the project directory, and the documents and settings area, the simulator once dead will not recover. If I blow away the entire project and restore it then just copy in my latest test bench, it starts working again. I have seen this no less than 20 times so far. Its the fastest way I can seem to keep ISIM running. I decided to go ahead and put the tools on my newer PC. Same install, all the same patches. No ISIM. I does not even show up as an option. Is anyone running ISIM on an XP Pro 64-bit SP2 machine? Maybe they don't support 64-bits with ISIM. I wish I could post some sort of test case to replicate the problem, but it all appears random at this point.Article: 136373
Hi everybody! I just want to let you know that I've succeedded (quite some time ago) in writting files to micro-SD card. I used SPI core that comes with EDK to implement low-level routines for micro-SD. Some examples of MMC/SD low-level routines can be found here: http://elm-chan.org/fsw/ff/00index_e.html (sample projects) For implementing a FAT file system I decided to use FatFs rather than DOSFS (which was a first choice and worked ok, but didn't support formatting - coming soon). To reduce size of an image (bitmap) I used software JPEG compression (IJG open source library). Thanks again!Article: 136374
Hi, I am trying to use Nios II with one Stratix II (2S60) DSP board, not the Nios board. Even to use Nios /f in the simplest hello example, the following error message is still there. What is the problem? Thanks all. BTW, Using Quartus 7.2 subscription. **** Build of configuration Debug for project hello_world_1 **** make -s all includes Linking hello_world_1.elf... /cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/ bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: region onchip_mem is full (hello_world_1.elf section .text). Region needs to be 41976 bytes larger. /cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/ bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: region onchip_mem is full (hello_world_1.elf section .rwdata). Region needs to be 3884 bytes larger. /cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/ bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: section .rodata [00002020 -> 000024ff] overlaps section .exceptions [00002020 -> 000021c7] /cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/ bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: section .rwdata [00002500 -> 00003f2b] overlaps section .text [000021c8 -> 0000d3f7] /cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/ bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/bin/ld: section .bss [00002020 -> 00002233] overlaps section .exceptions [00002020 -> 000021c7] /cygdrive/c/altera/72/nios2eds/bin/nios2-gnutools/H-i686-pc-cygwin/ bin/../lib/gcc/nios2-elf/3.4.1/../../../../nios2-elf/lib/mhw-mulx/ mcustom-fpu-cfg=60-1//libc.a(sbrkr.o)(.text+0x14): In function `_sbrk_r': /build/nios2eds-gnutools-win32-7.2/bin/nios2-gnutools/src/newlib/ newlib/libc/reent/sbrkr.c:59: Unable to reach errno (at 0x00002020) from the global pointer (at 0x0000bec0) because the offset (-40608) is out of the allowed range, -32678 to 32767. collect2: ld returned 1 exit status make: *** [hello_world_1.elf] Error 1 Build completed in 6.519 seconds
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