Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
"jleslie48" <jon@jonathanleslie.com> wrote in message news:f1446e4e-46bf-4779-9c5f-804f9ba46920@b6g2000pre.googlegroups.com... > > how do I get the FPGA to recognize that the volts are supposed > to come from the external wire and be interpreted as a 0 or a 1? > What is your job description? I am sorry but with this level of understanding of basic electricity you shouldn't be allowed close to a soldering iron. No amount of postings here will help you if you don't know what makes a current flow. You need to take a big step back and learn the basic physics first, otherwise change the job. /MikhailArticle: 140151
On Apr 30, 3:22=A0am, 1stderivat...@gmail.com wrote: > On Apr 30, 1:59=A0pm, Martin Thompson <martin.j.thomp...@trw.com> wrote: > > > > > 1stderivat...@gmail.com writes: > > > I was wondering if there is any simulator that could emulate my > > > Verilog code meant for the FPGA. The problem is that my code cant be > > > implemented on the FPGA boards available in my university lab. Hence > > > have to look out for a simulator. > > > Are you really asking if there are Verilog simulators? =A0Does your > > university not have access to one of the severeal available options? > > Google will tell you what they are! > > > Cheers, > > Martin > > > -- > > martin.j.thomp...@trw.com > > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp:/= /www.conekt.net/electronics.html > > I'm aware of the Simulators around... we use ModelSim. I would like to > know if the face recognition code could be implemented on such > simulators after proper interfacing. Is it possible for ModelSim to > simulate the code? > Thanks! Clearly, a Verilog simulator can run your Verilog logic. Are you asking if it is possible for a Verilog simulator to talk to external h/w such as a camera or LEDs? Well, it's just software, so anything is possible, especially with PLI or VPI code. But remember, a simulator will run MUCH slower than an FPGA, so it could take minutes or hours to process each facial image. John ProvidenzaArticle: 140152
Jacko wrote: > is there anyway to specify that the combinational fn is two cycle? the > register retiming options seem to remove the carry bit, and replace it > with and implicit signal. Maybe the retiming does an eval of the state > machine order and realizes?? I think my synthesis discussion confused the issue. To avoid a timing constraint, I have to treat fn() like a rom and do a read cycle with a wait counter in a synch process. count to n, set ready bit, wait for ack bit. > It seems that because the synthesis tool does not realize the data in > port remains constant, because the address bus remains constant, it > freaks a little and routes accordingly. As a latch is totally un- > necessary. Synthesis does what the code says. I need a simulator to check the code, not synthesis. > I don't have timing quest money or time. A free simulator is good enough to verify this controller. The only timing requirement inside a synch design is Fmax. Luts and flops are cheap. -- Mike TreselerArticle: 140153
On Apr 29, 8:22 am, David Fejes <fej...@gmail.com> wrote: > Hello there, > > I want use a GCLK pin in a Xilinx CPLD as a regular input. > Unfortunatelly the fitter designates it to global clock. > How can I tell to the fitter that this input is a regular data signal? > I've tried the BUFG constraint in the UCF file, but didn't success. > > GCLKs can operate as regular output so I think they have to able to > work as regular input too.. Am I wrong? > > Many thanks in advance > > David Fejes It appears that with the 9500 series, the clock pins connect to the matrix, so can be used as GPIO. It does not seem to be that way with the CoolRunner series. ALArticle: 140154
jprovidenza@yahoo.com wrote: > Clearly, a Verilog simulator can run your Verilog logic. > Are you asking if it is possible for a Verilog simulator > to talk to external h/w such as a camera or LEDs? > Well, it's just software, so anything is possible, especially > with PLI or VPI code. But remember, a simulator will run MUCH > slower than an FPGA, so it could take minutes or hours to > process each facial image. More specifically, writing it in a compiled language such as C will be much faster than simulating verilog. The usual reason for doing it in an FGPA is that the software version isn't fast enough. -- glenArticle: 140155
Hi all, Just a wild though: I wonder if the FPGA is still "partial functioning" if one of the ground pin on the BGA is not connected ? The device is the Spartan-3 1000 package = FG676 Thanks,Article: 140156
My guess is that depending somewhat on which particular ground ball it is not soldered, the chip is probably mostly functional, but the signal integrity on the IOs in close proximity to this ball might be affected especially for faster IO standards. /Mikhail "Mawa_fugo" <ccon67@netscape.net> wrote in message news:8b36d46b-9bbd-498e-b1ed-574cbc98b971@s1g2000prd.googlegroups.com... > Hi all, > > Just a wild though: I wonder if the FPGA is still "partial > functioning" if one of the ground pin on the BGA is not connected ? > > The device is the Spartan-3 1000 package = FG676 > > Thanks, >Article: 140157
On Apr 29, 9:10=A0am, lolita.tang...@gmail.com wrote: > I don=92t know, i have just begun in ISE . > > When I remove everything between "--synopsys synthesis_off" and "-- > synopsys synthesis_on" I was able to synthesize but only the entity > and I don=92t have an architecture for it. > My point was that when you remove the stuff between synthesis_off and synthesis_on you have exactly what the synthesis tool will give you, i.e. nothing. > I tried to implement just the ramx=92s =A0module and I has =A0the followi= ng > error: > > =A0ERROR: Pack:198 - NCD was not produced. All logic was removed from > design. =A0This =A0is usually due to having no input or output PAD > connections in the design and =A0no nets or symbols marked as 'SAVE'. > You can either add PADs or 'SAVE' =A0attributes to the design, or run > 'map -u' to disable logic trimming in the =A0mapper. > > So, I has a another code for a real =A0ram =A0( because the other is just > a simulation model), I was able to synthesize and I can implement it, > I changed it for use. > The new code is: > > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_arith.all; > --library mc8051; > --use mc8051.mc8051_p.all; > ------------------------ ENTITY DECLARATION ------------------------- > entity mc8051_ram is > > =A0 port (clk =A0 =A0 =A0 =A0: in =A0std_logic; =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 -- clock signal > =A0 =A0 =A0 =A0 reset =A0 =A0 =A0: in =A0std_logic; =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 -- reset signal > =A0 =A0 =A0 =A0 ram_data_i : in =A0std_logic_vector(7 downto 0); =A0-- da= ta input > =A0 =A0 =A0 =A0 ram_data_o : out std_logic_vector(7 downto 0); =A0-- data= output > =A0 =A0 =A0 =A0 ram_adr_i =A0: in =A0std_logic_vector(15 downto 0); =A0--= adresses > =A0 =A0 =A0 =A0 ram_wr_i =A0 : in =A0std_logic; =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 -- read=3D0, write=3D1 > =A0 =A0 =A0 =A0 Bypass_TM =A0 : in =A0std_logic); =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0 -- inactive=3D0;active=3D1 > > end mc8051_ram; > > architecture sim of mc8051_ram is > > =A0 type =A0 ram_type is array (65535 downto 0) of std_logic_vector(7 > downto 0); > > =A0 =A0signal gpram: =A0 =A0 =A0 =A0ram_type; =A0 =A0 =A0 =A0 =A0 =A0 -- = general purpose RAM > > begin > > -------------------------------------------------------------------------= ----- > -- ram_read > -------------------------------------------------------------------------= ----- > > =A0 p_read : process (clk, reset) > =A0 begin > =A0 =A0 if reset=3D'1' then > =A0 =A0 =A0 ram_data_o <=3D "00000000"; > =A0 =A0 else > =A0 =A0 =A0 if Rising_Edge(clk) then > =A0 =A0 =A0 =A0 ram_data_o <=3D gpram(conv_integer(unsigned(ram_adr_i))); > =A0 =A0 =A0 end if; > =A0 =A0 end if; > =A0 end process p_read; > > -------------------------------------------------------------------------= ----- > -- ram_write > -------------------------------------------------------------------------= ----- > > =A0 p_write : process (clk, reset) > =A0 begin > =A0 =A0 if reset=3D'1' then > =A0 =A0 =A0 gpram <=3D (others =3D> (others =3D>'0')); =A0 =A0-- reset ev= ery bit This is the part a real RAM can't handle. If you want to initialize every bit at startup, use an initial block instead. The place to find the proper code for instantiating a RAM is the synthesis manual for Xilinx. Go under Help --> Software Manuals and open the synthesis and simulation guide. It has chapters like "Implementing Memory", "Block RAM Inference", etc. > =A0 =A0 else > =A0 =A0 =A0 if Rising_Edge(clk) then > =A0 =A0 =A0 =A0 if =A0(ram_wr_i=3D'1') then > =A0 =A0 =A0 =A0 =A0 gpram(conv_integer(unsigned(ram_adr_i))) <=3D ram_dat= a_i; > =A0 =A0 =A0 =A0 end if; > =A0 =A0 =A0 end if; > =A0 =A0 end if; > =A0 end process p_write; > > end sim; > > when I was able to synthesize I have the following error: > > ERROR:Pack:18 - The design is too large for the given device and > package. > > Therefore, I taught to use the bram_block but i dont' know how. > > Regards. > lolitaArticle: 140158
On Apr 30, 5:42=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > Jacko wrote: > > is there anyway to specify that the combinational fn is two cycle? the > > register retiming options seem to remove the carry bit, and replace it > > with and implicit signal. Maybe the retiming does an eval of the state > > machine order and realizes?? > > I think my synthesis discussion confused the issue. > To avoid a timing constraint, I have to treat fn() > like a rom =A0and do a read cycle > with a wait counter in a synch process. > > count to n, set ready bit, wait for ack bit. > > > It seems that because the synthesis tool does not realize the data in > > port remains constant, because the address bus remains constant, it > > freaks a little and routes accordingly. As a latch is totally un- > > necessary. > > Synthesis does what the code says. > I need a simulator to check the code, not synthesis. > > > I don't have timing quest money or time. > > A free simulator is good enough to verify this controller. > The only timing requirement inside a synch design is Fmax. > Luts and flops are cheap. > > =A0 -- Mike Treseler The point was to get the synthesis tool to do it. But no matter anymore. I moved onto the half width (byte) data bus interface version got 49MHz estimate (nibzC.vhd) This avoids many of the propergation problems as each instruction takes 4 cycles. Which a over 10 MIPS will be fine. A big endian design which loads the little end first... The code is so simple...at 394 LEs, and highly orthogonal instruction decode and execution. The delayed write of the high byte consumes quite a few gates, but it does prevent the need for multiphasing the clock as the instruction fetch interleaves the two written bytes, so RW SRAM line has no need to be async to get the two rising edges. cheers jacko http://nibz.googlecode.comArticle: 140159
On Apr 30, 3:35=A0am, 1stderivat...@gmail.com wrote: > The problem is that my code cant be > implemented on the FPGA boards available in my university lab. Why not?Article: 140160
Does anyone know if EDK11.1 can be installed and used standalone without an ISE license? What about SDK only installation, i.e. without EDK? I believe it wasn't possible in the previous versions... EDK required ISE, and I believe SDK without EDK wasn't working either, although I am not confident about the latter. Now with increased prices my management wants to save some money on licenses... I searched Xilinx knowledge base but couldn't find an answer... /MikhailArticle: 140161
On May 1, 5:40=A0am, "MM" <mb...@yahoo.com> wrote: > Does anyone know if EDK11.1 can be installed and used standalone without = an > ISE license? What about SDK only installation, i.e. without EDK? I believ= e > it wasn't possible in the previous versions... EDK required ISE, and I > believe SDK without EDK wasn't working either, although I am not confiden= t > about the latter. Now with increased prices my management wants to save s= ome > money on licenses... =A0I searched Xilinx knowledge base but couldn't fin= d an > answer... > > /Mikhail you should be able to buy EDK only license, even if it is not offered as separate product in main price table i think. it would REAL bad move from Xilinx to limit the EDK only to be used with paid ISE version as ISE+EDK bundle AnttiArticle: 140162
On May 1, 5:40 am, "MM" <mb...@yahoo.com> wrote: > Does anyone know if EDK11.1 can be installed and used standalone without > an > ISE license? What about SDK only installation, i.e. without EDK? I believe > it wasn't possible in the previous versions... EDK required ISE, Sure. EDK 10.1 works with just the webpack. If there's a webpack 11.1, I would imagine EDK would work then also. > and I > believe SDK without EDK wasn't working either, although I am not confident > about the latter. What would that workflow look like? Seems to me anything useful would involve a license violation of some sort. I hate to be the one to say this, but MS has a Lite version of VS2008 for free download. As with Eclipse, you either love it or you hate it, and I happen to hate Eclipse. Why bother with SDK? (That wasn't rhetorical. I'm wondering this moment if there's something awefully compelling to make you contemplate what you're contemplating.)Article: 140163
On Apr 30, 4:40=A0pm, padu...@gmail.com wrote: > On Apr 29, 8:40=A0am, meti...@gmx.de wrote: > > > > > Hi, > > > first off, this subject keeps bugging me since i work with (Xilinx) > > FPGAs. > > > So,..there is an OFFSET OUT constraint to specify for Outputs. > > > So far i understand from timing reports, PAR evaluates OFFSET OUT as a > > maximum value. > > > But...design i'm currently doing restricts me also for suppliying a > > minimum clock-to-output > > > constraint. Seems like this is currently not possible with xilinx > > tools...am i right? > > > I need to specify an maximum and minimum value for OFFSET OUT. > > > All i can do is...after PAR finishes...do timing anaylsis with "Report > > fastest paths/verbose hold paths" check box selected. > > > This gives me the setup/hold paths for all timing paths avaliable in > > the design, right? > > So at least i can check what my current min. clk-to-out delay is. > > > And, i found also something like Speedgrade -0 for checking best case > > timing results. > > > (referring tohttp://www.xilinx.com/support/answers/4506.htm) > > > Do someone know the difference. > > > Thanks > > I looked in the Xilinx Timing Constraints User's Guidehttp://www.xilinx.c= om/support/documentation/sw_manuals/xilinx11/ug612.... > > It seems there is an OFFSET OUT AFTER constraint that checks for > maximum clock-to-out (setup) and then there is an OFFSET OUT BEFORE > constraint that checks for hold. > > =A0 Pete Hi, i always thought OFFSET OUT BEFORE is the same as AFTER, same thing defined with other words. But honestly, i have never tried it before. May be should give a try and see what happens. But i don't think it will help. May be, to be more exact, can you tell me the example constraints for defining max clock to output of lets say 3 ns and min clock to output of 0,7 ns. How whould you code this in the constraints? Thanks MetinArticle: 140164
On May 1, 12:09=A0pm, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > On May 1, 5:40 am, "MM" <mb...@yahoo.com> wrote: > > > Does anyone know if EDK11.1 can be installed and used standalone withou= t > > an > > ISE license? What about SDK only installation, i.e. without EDK? I beli= eve > > it wasn't possible in the previous versions... EDK required ISE, > > Sure. EDK 10.1 works with just the webpack. If there's a webpack 11.1, I > would imagine EDK would work then also. > > > and I > > believe SDK without EDK wasn't working either, although I am not confid= ent > > about the latter. > > What would that workflow look like? Seems to me anything useful would > involve a license violation of some sort. I hate to be the one to say thi= s, > but MS has a Lite version of VS2008 for free download. As with Eclipse, y= ou > either love it or you hate it, and I happen to hate Eclipse. Why bother w= ith > SDK? (That wasn't rhetorical. I'm wondering this moment if there's someth= ing > awefully compelling to make you contemplate what you're contemplating.) well, the worry of OP comes from the fact that with 11.1 there is no price given for EDK any more, the only possibility to obtain EDK includes buying a package that includes a FULL ISE version. so if you want EDK 11.1, you can buy it from Avent: 3395$ stock NO, lead time 26 weeks, or nuhorizons, price 3395, stock NO, lead time 2 weeks. ISE/EDK or any other software is no longer available from Xilinx online store, only from distributors. So for me it is clear that the OP doesnt want to pay $3395 for the EDK license (and this is for one year only!). AnttiArticle: 140165
On Apr 30, 5:59=A0pm, LittleAlex <alex.lo...@email.com> wrote: > On Apr 29, 8:22 am, David Fejes <fej...@gmail.com> wrote: > > > Hello there, > > > I want use a GCLK pin in a Xilinx CPLD as a regular input. > > Unfortunatelly the fitter designates it to global clock. > > How can I tell to the fitter that this input is a regular data signal? > > I've tried the BUFG constraint in the UCF file, but didn't success. > > > GCLKs can operate as regular output so I think they have to able to > > work as regular input too.. Am I wrong? > > > Many thanks in advance > > > David Fejes > > It appears that with the 9500 series, the clock pins connect to the > matrix, so can be used as GPIO. > > It does not seem to be that way with the CoolRunner series. > > AL I use XC95144XL family. In theorem, the pins connects to the FastConnect switch matrix. I have disabled in the properties of the fitter the using of global clocks. But the fitter still sends the a warning, that these signals are designated to global clock. Anyway, in the fitter report the number of global clocks seems to be zero. I don't understand the situation... I've tried now the config PROHIBIT=3D... constraint in various form, but didn't succeed... DaveArticle: 140166
On Apr 30, 2:48=A0pm, "MM" <mb...@yahoo.com> wrote: > My guess is that depending somewhat on which particular ground ball it is > not soldered, the chip is probably mostly functional, but the signal > integrity on the IOs in close proximity to this ball might be affected > especially for faster IO standards. > > /Mikhail > > "Mawa_fugo" <cco...@netscape.net> wrote in message > > news:8b36d46b-9bbd-498e-b1ed-574cbc98b971@s1g2000prd.googlegroups.com... > > > > > Hi all, > > > Just a wild though: I wonder if the FPGA is still "partial > > functioning" if one of the ground pin on the BGA is not connected ? > > > The device is the Spartan-3 1000 package =3D FG676 > > > Thanks,- Hide quoted text - > > - Show quoted text - Thanks for sharing your opinion !Article: 140167
On Wed, 29 Apr 2009 22:54:42 -0700 (PDT), JSreeniv wrote: >I have a module called CCM (core control module) with 16-bit data bus >if i want to write 32-bit data how can i write and how to represent on >expected results; > >can i represent: > >--Upper 16 bits--Ist cycle >dsp_d(15:0) = 0x0123 >--Lower 16 bits--2nd cycle >dsp_d(15:0) = 0x4567 Of course, you can write and read the data in any order you choose. The real question is: where are these two 16-bit words stored in your 16-bit memory? If the upper half is stored at the lower-numbered address, you have "big-endian" convention. If the upper half is stored at the higher-numbered address, it is "little endian". Both make sense, provided you use them consistently. > >(or) > >reading 32-bits of data in two cycle burst of 16-bit words. >dsp_d(15:0) = 0xDDDD. Sorry, I have no idea what you mean here. >Please give me some exposure on this. because we have like CCM's three >kinds one is having READ and WRITE data buses same widths but others >are having different so make balance conventions i required >suggestions. Your own module can do whatever it wants. The problems will arise when the same data, stored in your memory, is used by other subsystems such as a CPU. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 140168
There is no way to define minimum CLK to OUT with the OFFSET constraint. Instead you should make sure that the output flip-flops are placed in the IOBs and choose an IO standard with parameters hopefully matching your timing requirements. You can also move your output clock edge in a few different ways if needed. /MikhailArticle: 140169
The Matrox X.AVCio features a DVI input and supports 1080p at 50 and 60 (59.94) fps. Contact your local Matrox Imaging representative for more information: http://www.matrox.com/imaging/buy/home.cfm On Apr 28, 4:45=A0pm, Petter Gustad <newsmailco...@gustad.com> wrote: > Thank you for your reply. I'm looking for something which can handle > 1080p/60 or more. > > PetterArticle: 140170
"MikeWhy" <boat042-nospam@yahoo.com> wrote in message news:s%yKl.15543$hc1.2411@flpi150.ffdc.sbc.com... > > What would that workflow look like? Seems to me anything useful would > involve a license violation of some sort. I hate to be the one to say > this, but MS has a Lite version of VS2008 for free download. As with > Eclipse, you either love it or you hate it, and I happen to hate Eclipse. > Why bother with SDK? (That wasn't rhetorical. I'm wondering this moment if > there's something awefully compelling to make you contemplate what you're > contemplating.) > We currently have to support two projects. From the hardware point of view both of them have top level in ISE and both include a PPC subsystem. One is implemented in V4FX60 and another in V4FX20/40. On the software side the bigger board runs under VxWorks and we are using VxWorks design environment (another Eclipse) for the application software development. However, to build a BSP for that board, EDK has to be run on a PC where VxWorks is installed or at least that's what we believe, I can imagine that this can be worked around somehow. As mostly a hardware designer I don't have VxWorks on my PC, so this step is done by a software person. The smaller board runs with no OS and the application for it is maintained in SDK. I think debugger facility in SDK will not work if EDK is not installed. Also, starting from 10.1 or perhaps even 9, SDK would alsways ask for an xmp file when started and it would then try to verify if BSP is up to date. I can't see how this will work without EDK... /MikhailArticle: 140171
<Antti.Lukats@googlemail.com> wrote in message news:beb204d5-4792-4298-afb5-85b167e7e32f@b7g2000pre.googlegroups.com... > >So for me it is clear that the OP doesnt want to pay $3395 for the EDK >license (and this is for one year only!). Antti, We have a team of 3 people (1 hardware, and 2 software, one of which is occasional) and I need to find an optimal licensing solution for all. /MikhailArticle: 140172
Jacko wrote:
> The point was to get the synthesis tool to do it. But no matter
> anymore. I moved onto the half width (byte) data bus interface version
> got 49MHz estimate (nibzC.vhd) This avoids many of the propergation
> problems as each instruction takes 4 cycles. Which a over 10 MIPS will
> be fine. A big endian design which loads the little end first...
> The code is so simple...at 394 LEs, and highly orthogonal instruction
> decode and execution. The delayed write of the high byte consumes
> quite a few gates, but it does prevent the need for multiphasing the
> clock as the instruction fetch interleaves the two written bytes, so
> RW SRAM line has no need to be async to get the two rising edges.
> cheers jacko
>
> http://nibz.googlecode.com
Thanks for the link.
That looks like a good place to collaborate.
Sorry I didn't follow your problem,
but thanks for posting the solution.
I always prefer changing my design over
turning the knobs on synthesis.
-- Mike Treseler
Article: 140173<Antti.Lukats@googlemail.com> wrote in message news:beb204d5-4792-4298-afb5-85b167e7e32f@b7g2000pre.googlegroups.com... On May 1, 12:09 pm, "MikeWhy" <boat042-nos...@yahoo.com> wrote: > On May 1, 5:40 am, "MM" <mb...@yahoo.com> wrote: > > > Does anyone know if EDK11.1 can be installed and used standalone without > > an > > ISE license? What about SDK only installation, i.e. without EDK? I > > believe > > it wasn't possible in the previous versions... EDK required ISE, > > Sure. EDK 10.1 works with just the webpack. If there's a webpack 11.1, I > would imagine EDK would work then also. > > > and I > > believe SDK without EDK wasn't working either, although I am not > > confident > > about the latter. > > What would that workflow look like? Seems to me anything useful would > involve a license violation of some sort. I hate to be the one to say > this, > but MS has a Lite version of VS2008 for free download. As with Eclipse, > you > either love it or you hate it, and I happen to hate Eclipse. Why bother > with > SDK? (That wasn't rhetorical. I'm wondering this moment if there's > something > awefully compelling to make you contemplate what you're contemplating.) well, the worry of OP comes from the fact that with 11.1 there is no price given for EDK any more, the only possibility to obtain EDK includes buying a package that includes a FULL ISE version. so if you want EDK 11.1, you can buy it from Avent: 3395$ stock NO, lead time 26 weeks, or nuhorizons, price 3395, stock NO, lead time 2 weeks. ISE/EDK or any other software is no longer available from Xilinx online store, only from distributors. So for me it is clear that the OP doesnt want to pay $3395 for the EDK license (and this is for one year only!). Antti ============================= Yeah. I wondered what the issue was. EDK licensing was rather unreasonable I thought. I find I now have Transition Licenses that expire very soon. Better find out what that's all about. And I see they no longer license sysgen alone, only with acceldsp.Article: 140174
"MikeWhy" <boat042-nospam@yahoo.com> wrote in message news:75GKl.28897> > > well, the worry of OP comes from the fact that with 11.1 there is no > price > given for EDK any more, the only possibility to obtain EDK includes > buying > a package that includes a FULL ISE version. > > Antti > It's not quite true. You can still get EDK separately for $495 (http://www.xilinx.com/onlinestore/design_resources.htm), and it looks as it comes with a separate license, but it is not clear to me based on my previous experience whether EDK can actually be used on its own without ISE. I guess Webpack is an option if it will support the devices I need... /Mikhail
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z