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Messages from 143750

Article: 143750
Subject: Re: Time stability of clock on FPGA board
From: Alex <victous@gmail.com>
Date: Fri, 23 Oct 2009 12:21:05 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 23 =CF=CB=D4, 20:40, doug <x...@xx.com> wrote:
> Nico Coesel wrote:
> > -jg <jim.granvi...@gmail.com> wrote:
>
> >>On Oct 23, 11:51=3DA0am, -jg <jim.granvi...@gmail.com> wrote:
>
> >>>So, having decided every-cycle precision is not practical, you have to
> >>>decide over what time you need this 0.1Hz ?
> >>>Suppose you need it over 100ms, then you can generate 99,999 cycles of
> >>>1.00us, and one cycle of
>
> >>( oops, Hit the wrong button...)
> >>Finishing that example: in a pure digital domain
>
> >>For a 100ms time average, of your 1000000.1 Hz, we generate
> >>99,999 cycles of 1,00us and one cycle 10ns less
> >>Frequency is then Cycles.Time =9A=3D3D
>
> >>100000/(99999*1.0u + (1u-10n)) =3D3D 1000000.10000001
>
> >>So, you _can_ generate 1MHz to 0.1Hz increments, over multiples of
> >>greater than 100ms, with a 10ns timebase.
> >>That certainly is FPGA doable.
>
> > It certainly is. Years ago I build a DPLL in an FPGA that way for
> > synchronising to an E1 line. It has a range of +/- 200ppm in less than
> > 0.5ppm steps. Its just a matter of skipping or inserting extra clock
> > cycles each frame.
>
> This works fine for locking to a fixed frequency over a narrow range
> and many of us have used it. =9AThe deficiency of it is that it is fine
> for digital clocks but is bad for analog signals. =9AFor generating
> arbitrary frequencies, you are better off using a DDS. =9AThe DDS is even
> available as a coregen element for Xilinx (the digital part anyway).

Xilinx DDS Compiler seems suitable for my project.

Article: 143751
Subject: ISe 10.1 nightmare bug
From: Mawa_fugo <ccon67@netscape.net>
Date: Fri, 23 Oct 2009 12:32:58 -0700 (PDT)
Links: << >>  << T >>  << A >>
I have SP3 installed in the 10.1 -  but sometimes - once a while, the
entire project just corrupted - when "rerun all" it TOOK the topmodule
source from "nowhere" - nomatter how you change your topmodule it
still lock the topmodule source fom that mystery source

Oh my goodness

Article: 143752
Subject: Re: Time stability of clock on FPGA board
From: Peter Alfke <alfke@sbcglobal.net>
Date: Fri, 23 Oct 2009 12:33:13 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 23, 12:21=C2=A0pm, Alex <vict...@gmail.com> wrote:
> On 23 =C3=8F=C3=8B=C3=94, 20:40, doug <x...@xx.com> wrote:
>
>
>
>
>
> > Nico Coesel wrote:
> > > -jg <jim.granvi...@gmail.com> wrote:
>
> > >>On Oct 23, 11:51=3DA0am, -jg <jim.granvi...@gmail.com> wrote:
>
> > >>>So, having decided every-cycle precision is not practical, you have =
to
> > >>>decide over what time you need this 0.1Hz ?
> > >>>Suppose you need it over 100ms, then you can generate 99,999 cycles =
of
> > >>>1.00us, and one cycle of
>
> > >>( oops, Hit the wrong button...)
> > >>Finishing that example: in a pure digital domain
>
> > >>For a 100ms time average, of your 1000000.1 Hz, we generate
> > >>99,999 cycles of 1,00us and one cycle 10ns less
> > >>Frequency is then Cycles.Time =C5=A1=3D3D
>
> > >>100000/(99999*1.0u + (1u-10n)) =3D3D 1000000.10000001
>
> > >>So, you _can_ generate 1MHz to 0.1Hz increments, over multiples of
> > >>greater than 100ms, with a 10ns timebase.
> > >>That certainly is FPGA doable.
>
> > > It certainly is. Years ago I build a DPLL in an FPGA that way for
> > > synchronising to an E1 line. It has a range of +/- 200ppm in less tha=
n
> > > 0.5ppm steps. Its just a matter of skipping or inserting extra clock
> > > cycles each frame.
>
> > This works fine for locking to a fixed frequency over a narrow range
> > and many of us have used it. =C5=A1The deficiency of it is that it is f=
ine
> > for digital clocks but is bad for analog signals. =C5=A1For generating
> > arbitrary frequencies, you are better off using a DDS. =C5=A1The DDS is=
 even
> > available as a coregen element for Xilinx (the digital part anyway).
>
> Xilinx DDS Compiler seems suitable for my project.

Alex, I have some experience with DDS circuits, and with various
methods of jitter reduction.
If you want to, we can discuss the issues and trade-offs off-line.
Peter Alfke, formerly Xilinx Applications
alfke@sbcglobal.net

Article: 143753
Subject: Re: Time stability of clock on FPGA board
From: Alex <victous@gmail.com>
Date: Fri, 23 Oct 2009 13:58:39 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 23 =D0=BE=D0=BA=D1=82, 22:33, Peter Alfke <al...@sbcglobal.net> wrote:
> On Oct 23, 12:21=C2=A0pm, Alex <vict...@gmail.com> wrote:
>
>
>
> > On 23 =C3=8F=C3=8B=C3=94, 20:40, doug <x...@xx.com> wrote:
>
> > > Nico Coesel wrote:
> > > > -jg <jim.granvi...@gmail.com> wrote:
>
> > > >>On Oct 23, 11:51=3DA0am, -jg <jim.granvi...@gmail.com> wrote:
>
> > > >>>So, having decided every-cycle precision is not practical, you hav=
e to
> > > >>>decide over what time you need this 0.1Hz ?
> > > >>>Suppose you need it over 100ms, then you can generate 99,999 cycle=
s of
> > > >>>1.00us, and one cycle of
>
> > > >>( oops, Hit the wrong button...)
> > > >>Finishing that example: in a pure digital domain
>
> > > >>For a 100ms time average, of your 1000000.1 Hz, we generate
> > > >>99,999 cycles of 1,00us and one cycle 10ns less
> > > >>Frequency is then Cycles.Time =C5=A1=3D3D
>
> > > >>100000/(99999*1.0u + (1u-10n)) =3D3D 1000000.10000001
>
> > > >>So, you _can_ generate 1MHz to 0.1Hz increments, over multiples of
> > > >>greater than 100ms, with a 10ns timebase.
> > > >>That certainly is FPGA doable.
>
> > > > It certainly is. Years ago I build a DPLL in an FPGA that way for
> > > > synchronising to an E1 line. It has a range of +/- 200ppm in less t=
han
> > > > 0.5ppm steps. Its just a matter of skipping or inserting extra cloc=
k
> > > > cycles each frame.
>
> > > This works fine for locking to a fixed frequency over a narrow range
> > > and many of us have used it. =C5=A1The deficiency of it is that it is=
 fine
> > > for digital clocks but is bad for analog signals. =C5=A1For generatin=
g
> > > arbitrary frequencies, you are better off using a DDS. =C5=A1The DDS =
is even
> > > available as a coregen element for Xilinx (the digital part anyway).
>
> > Xilinx DDS Compiler seems suitable for my project.
>
> Alex, I have some experience with DDS circuits, and with various
> methods of jitter reduction.
> If you want to, we can discuss the issues and trade-offs off-line.
> Peter Alfke, formerly Xilinx Applications
> al...@sbcglobal.net

Hi Peter,
I'll need to start from basics of DDS, what would be boring for
professionals to talk about. Anyway, thanks!

Article: 143754
Subject: Re: Time stability of clock on FPGA board
From: doug <xx@xx.com>
Date: Fri, 23 Oct 2009 13:56:30 -0800
Links: << >>  << T >>  << A >>


Alex wrote:

> On 23 , 20:40, doug <x...@xx.com> wrote:
> 
>>Nico Coesel wrote:
>>
>>>-jg <jim.granvi...@gmail.com> wrote:
>>
>>>>On Oct 23, 11:51=A0am, -jg <jim.granvi...@gmail.com> wrote:
>>
>>>>>So, having decided every-cycle precision is not practical, you have to
>>>>>decide over what time you need this 0.1Hz ?
>>>>>Suppose you need it over 100ms, then you can generate 99,999 cycles of
>>>>>1.00us, and one cycle of
>>
>>>>( oops, Hit the wrong button...)
>>>>Finishing that example: in a pure digital domain
>>
>>>>For a 100ms time average, of your 1000000.1 Hz, we generate
>>>>99,999 cycles of 1,00us and one cycle 10ns less
>>>>Frequency is then Cycles.Time  =3D
>>
>>>>100000/(99999*1.0u + (1u-10n)) =3D 1000000.10000001
>>
>>>>So, you _can_ generate 1MHz to 0.1Hz increments, over multiples of
>>>>greater than 100ms, with a 10ns timebase.
>>>>That certainly is FPGA doable.
>>
>>>It certainly is. Years ago I build a DPLL in an FPGA that way for
>>>synchronising to an E1 line. It has a range of +/- 200ppm in less than
>>>0.5ppm steps. Its just a matter of skipping or inserting extra clock
>>>cycles each frame.
>>
>>This works fine for locking to a fixed frequency over a narrow range
>>and many of us have used it.  The deficiency of it is that it is fine
>>for digital clocks but is bad for analog signals.  For generating
>>arbitrary frequencies, you are better off using a DDS.  The DDS is even
>>available as a coregen element for Xilinx (the digital part anyway).
> 
> 
> Xilinx DDS Compiler seems suitable for my project.

You have to decide if the jitter from this is ok for you. The ways
of reducing the jitter include increasing the clock rate or by
feeding the output through a d/a converter with a baseband
filter. The idea is to use the filter to do the interpolation of
the zero crossings. This is one of the real nice features of the
Analog Devices parts. You can clock at hundreds of MHz and for
low frequency outputs, the jitter is effectively zero.

You never told us what kind of output you really want. A digital
clock?  An audio test signal?  What are the distortion and
purity specs?


Article: 143755
Subject: Re: CPLD/FPGA with Linux
From: nico@puntnl.niks (Nico Coesel)
Date: Fri, 23 Oct 2009 22:16:22 GMT
Links: << >>  << T >>  << A >>
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote:

>- Voltage tolerance needed (only XC95XV is (limited ) 5-Volt tolerant

Xilinx's Spartan 2 (not 2E!) is also 5V tolerant. Same goes for older
Virtex devices.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
                     "If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------

Article: 143756
Subject: connecting Xilinx XUP expansion headers
From: Alderaan <giovannibusonera@yahoo.it>
Date: Sat, 24 Oct 2009 02:53:19 +0200
Links: << >>  << T >>  << A >>
Hello,
I'm having a problem connecting a Xilinx XUP board with an ADC board.
The scheme is very simple, from XUP board I send a clock (20MHz) to the 
ADC board that sends back 16bit parallel samples and a clock (20MHz). 
These signals (1.8V) enter to the low speed connector of the Xup board. 
The cable I chosed for the connection between boards is an ATA-133 cable.
Actually, that cable is causing the problem because signas at the output 
of ADC pins are good but, if I look at them at the end of the cable, 
they are corrupted (clock is very bad). I think that cable has too high 
capacitance to be driven from the ADC board buffers.
Could you suggest me another kind of cable that I can use with the XUP 
low speed connector? Using single cables would be better (I think no 
but...)? Could I do something to make things better using the ATA-133 cable?
Thank you in advance.
Bye
Giovanni

Article: 143757
Subject: Re: problem while receiving negative integer in microblaze
From: GrIsH <grishkunwar@gmail.com>
Date: Fri, 23 Oct 2009 18:44:03 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 23, 5:19=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> Goran_Bilski <goran.bil...@xilinx.com> wrote:
>
> (snip)
>
> > MicroBlaze use big-endian byte-ordering and big-endian bit ordering.
> > This is a legacy from PowerPC and CoreConnect bus.
> > It's not only PowerPC who uses big-endian ordering.
> > As much as the msb bit number changes for big-endian so does the lsb
> > bit number for little-endian.
>
> (snip)
>
> > I do however prefer big-endian byte order since when dumping bytes
> > from memory will show the word in the right order.
> > We tend to write numbers with the most significant numbers to the left
> > and that is how big-endian is storing bytes within a word.
>
> The VAX/VMS DUMP program prints the HEX data right to left, and
> the ASCII data left to right with the address in the middle.
> Big endian avoids strange solutions like that.
>
> -- glen


lot of thanks to all of you that you people have great discussion on
this topic..........i'm new to ubalze and this is my first project in
ublaze and i got the chance to know lots of things from these
discussions........I'm so sorry that i could not be a part of this
discussion for one week because i have a festival here which is one of
our great festival and now i'm in course.............

 i gave continuity to my work from yesterday,i simulated my design
with BFM(Bus Function Module) simulation and found the result bit
confusing .....

I already told that i'm new one..You people have great discussion its
fine!! But still my problem is with me, i think its very easy for you
people....

How is this happen??
I have signal "cnt" of integer type and was mapped to IP2Bus_Data as
IP2Bus_Data(0 to 31) <=3D std_logic_vector(to_signed(cnt,32));

after simulation , i found the data in the PLB bus was in 2's
complement form but i think it should be in signed form so how??

i mean.....
if i send +4(that is value of "cnt"), data in the PLB bus was
"00000000000000000000000000000100"(32 bit)
if -4 was send then it was "11111111111111111111111111111100" BUT i
think in signed form it should be
"10000000000000000000000000000100"......

-Grish



Article: 143758
Subject: Picoblaze assembler not running Help!!!
From: "wixization" <mosfets.bjt@gmail.com>
Date: Fri, 23 Oct 2009 21:08:10 -0500
Links: << >>  << T >>  << A >>
Hi everyone.

can anybody tell why KCPSM3 assembler doesnt run on my windows sp2 version
2002.
I tried it on one of my friendz pc but it did'nt run their either. we both
have different version of windows and picoblaze assembler for spartan 3
KCPSM3 cannot be executed on my PC. Help plzz. i need it.

thx in advance 



Article: 143759
Subject: Re: ISe 10.1 nightmare bug
From: Antti <antti.lukats@googlemail.com>
Date: Fri, 23 Oct 2009 23:15:03 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 23, 10:32=A0pm, Mawa_fugo <cco...@netscape.net> wrote:
> I have SP3 installed in the 10.1 - =A0but sometimes - once a while, the
> entire project just corrupted - when "rerun all" it TOOK the topmodule
> source from "nowhere" - nomatter how you change your topmodule it
> still lock the topmodule source fom that mystery source
>
> Oh my goodness

I just had another ise 10.1 project nightmare too, it was a real
nightmare
ah yes, sometimes the project files did show files that well i have no
idea
where it got them, as the file did not have them, I updated a fresh
known
good copy of the ise file from SVN repo maybe 40 times, but each time
ISE did destroy the ise on opening or then displayed wrong content.

I know, upgrade to 11.x is a must, but for this project we can not do
it
so we are left to fight with the ISE nightmares

Antti



Article: 143760
Subject: Re: ISe 10.1 nightmare bug
From: Herbert Kleebauer <klee@unibwm.de>
Date: Sat, 24 Oct 2009 10:35:44 +0200
Links: << >>  << T >>  << A >>
Mawa_fugo wrote:
> 
> I have SP3 installed in the 10.1 -  but sometimes - once a while, the
> entire project just corrupted - when "rerun all" it TOOK the topmodule
> source from "nowhere" - nomatter how you change your topmodule it
> still lock the topmodule source fom that mystery source

Create a new project and then copy all your design files from the old
to the new project. This requires only a few seconds and then you
can continue your work for a few hours before you have to create 
the next new project version. I really would like to have the good
old DOS development software back which they shipped for the XC3000
FPGA's twenty years ago.

Article: 143761
Subject: Re: problem while receiving negative integer in microblaze
From: Goran_Bilski <goran.bilski@xilinx.com>
Date: Sat, 24 Oct 2009 02:37:54 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 24, 3:44=A0am, GrIsH <grishkun...@gmail.com> wrote:
> On Oct 23, 5:19=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
>
>
>
>
>
> > Goran_Bilski <goran.bil...@xilinx.com> wrote:
>
> > (snip)
>
> > > MicroBlaze use big-endian byte-ordering and big-endian bit ordering.
> > > This is a legacy from PowerPC and CoreConnect bus.
> > > It's not only PowerPC who uses big-endian ordering.
> > > As much as the msb bit number changes for big-endian so does the lsb
> > > bit number for little-endian.
>
> > (snip)
>
> > > I do however prefer big-endian byte order since when dumping bytes
> > > from memory will show the word in the right order.
> > > We tend to write numbers with the most significant numbers to the lef=
t
> > > and that is how big-endian is storing bytes within a word.
>
> > The VAX/VMS DUMP program prints the HEX data right to left, and
> > the ASCII data left to right with the address in the middle.
> > Big endian avoids strange solutions like that.
>
> > -- glen
>
> lot of thanks to all of you that you people have great discussion on
> this topic..........i'm new to ubalze and this is my first project in
> ublaze and i got the chance to know lots of things from these
> discussions........I'm so sorry that i could not be a part of this
> discussion for one week because i have a festival here which is one of
> our great festival and now i'm in course.............
>
> =A0i gave continuity to my work from yesterday,i simulated my design
> with BFM(Bus Function Module) simulation and found the result bit
> confusing .....
>
> I already told that i'm new one..You people have great discussion its
> fine!! But still my problem is with me, i think its very easy for you
> people....
>
> How is this happen??
> I have signal "cnt" of integer type and was mapped to IP2Bus_Data as
> IP2Bus_Data(0 to 31) <=3D std_logic_vector(to_signed(cnt,32));
>
> after simulation , i found the data in the PLB bus was in 2's
> complement form but i think it should be in signed form so how??
>
> i mean.....
> if i send +4(that is value of "cnt"), data in the PLB bus was
> "00000000000000000000000000000100"(32 bit)
> if -4 was send then it was "11111111111111111111111111111100" BUT i
> think in signed form it should be
> "10000000000000000000000000000100"......
>
> -Grish- Hide quoted text -
>
> - Show quoted text -

Hi,

The function to_signed converts it's to 2-complement format which is
the default way of handling negative numbers.
The "sign,magnitude" format is not used that much since all arithmetic
operations has to be handled specially while 2-complement is just
normal operations.

If you really want the "sign,magnitude" format, you have to manually
set the sign bit and to a "abs" on the cnt value.

G=F6ran



Article: 143762
Subject: Generating delay using logic gates
From: Sharath Raju <brsharath@gmail.com>
Date: Sat, 24 Oct 2009 03:19:06 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,

This question isn't directly related to FPGAs, I felt people may be
able to help.

I am trying to generate PWM pulses of width 'W' in sync to a square
wave signal X . Please refer Fig1.http://brsharath.googlepages.com/
24102009.jpg

I tried to delay the signal X using logic gates and xored the delayed
signal with the original signal, to get pulses whose ON time equals
the sum of the propagation delay of the logic gates.

See Fig 2 http://brsharath.googlepages.com/24102009001.jpg

Though I am able to see the pulses on the oscilloscope, I see ringing
at the falling edge of the pulse.

What is the cause of ringing ?, and

Are there any alternative ways of generating PWM pulses.

Article: 143763
Subject: Re: ISe 10.1 nightmare bug
From: Mawa_fugo <ccon67@netscape.net>
Date: Sat, 24 Oct 2009 07:51:45 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 24, 3:35=A0am, Herbert Kleebauer <k...@unibwm.de> wrote:
> Mawa_fugo wrote:
>
> > I have SP3 installed in the 10.1 - =A0but sometimes - once a while, the
> > entire project just corrupted - when "rerun all" it TOOK the topmodule
> > source from "nowhere" - nomatter how you change your topmodule it
> > still lock the topmodule source fom that mystery source
>
> Create a new project and then copy all your design files from the old
> to the new project. This requires only a few seconds and then you
> can continue your work for a few hours before you have to create
> the next new project version. I really would like to have the good
> old DOS development software back which they shipped for the XC3000
> FPGA's twenty years ago.

Yup - that's the only way to overcome this nightmare - but for a
fairly big project it take some effort to make sure you ghosting the
exact project

Article: 143764
Subject: Re: CPLD/FPGA with Linux
From: Anssi Saari <as@sci.fi>
Date: Sat, 24 Oct 2009 18:53:48 +0300
Links: << >>  << T >>  << A >>
"Scorpiion" <Robert.nr1@gmail.com> writes:

> I have looked at some of Xilinks and Alteras homepages and it seams that
> they have software for Linux. But it would be good to hear from someone
> with experince how the different software packages work?

I've used Xilinx ISE and EDK in Linux a lot, Modelsim too (the
expensive Modelsim SE usually). They work just fine, since version 9.1
as I recall. Previous versions were a little bad in the GUI
department, since that was done with some kind of converter tool.

I haven't really used a Xilinx cable driver in Linux since 2006. 
Worked fine then, but the labs I've been in since then have had
Windows machines.

> (if some company have better software than other, or someones
> software is better for the Linux platform)

You may want to look at the free offerings from Lattice and Actel too,
as far as I know they provide free Modelsim and Synplify. Not sure if
they provide it for a student though.

I don't know what the story is with Altera. I vaguely remember
finding, downloading and running their free Web Edition for Linux last
spring, but I can't find it now.

Article: 143765
Subject: Re: Generating delay using logic gates
From: General Schvantzkoph <schvantzkoph@yahoo.com>
Date: 24 Oct 2009 16:23:06 GMT
Links: << >>  << T >>  << A >>
On Sat, 24 Oct 2009 03:19:06 -0700, Sharath Raju wrote:

> Hi,
> 
> This question isn't directly related to FPGAs, I felt people may be able
> to help.
> 
> I am trying to generate PWM pulses of width 'W' in sync to a square wave
> signal X . Please refer Fig1.http://brsharath.googlepages.com/
> 24102009.jpg
> 
> I tried to delay the signal X using logic gates and xored the delayed
> signal with the original signal, to get pulses whose ON time equals the
> sum of the propagation delay of the logic gates.
> 
> See Fig 2 http://brsharath.googlepages.com/24102009001.jpg
> 
> Though I am able to see the pulses on the oscilloscope, I see ringing at
> the falling edge of the pulse.
> 
> What is the cause of ringing ?, and
> 
> Are there any alternative ways of generating PWM pulses.

You need to terminate the signal.

Article: 143766
Subject: Re: ISe 10.1 nightmare bug
From: kevin93 <kevin@whitedigs.com>
Date: Sat, 24 Oct 2009 09:51:13 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 23, 12:32=A0pm, Mawa_fugo <cco...@netscape.net> wrote:
> I have SP3 installed in the 10.1 - =A0but sometimes - once a while, the
> entire project just corrupted - when "rerun all" it TOOK the topmodule
> source from "nowhere" - nomatter how you change your topmodule it
> still lock the topmodule source fom that mystery source
>
> Oh my goodness

The "Cleanup Project Files" under the "Project" menu can solve many of
these problems.

kevin

Article: 143767
Subject: ISE 9.2 - RTL Schematic problem (separating of included components)
From: "sdaau" <sd@imi.aau.dk>
Date: Sat, 24 Oct 2009 12:57:04 -0500
Links: << >>  << T >>  << A >>
Hi all, 

I am trying to experiment in ISE Webpack 9.2 on Linux, and I have a top
level VHDL file, which uses externally defined, or "included" components
(some in VHDL, some in Verilog). 

I have a slight problem with RTL schematic view: 

1) When I try to hook up these "included" components to pins defined for
the top level, all "included" components show up in RTL schematic view
(after the first "Push into Selected Instance") with their defined
schematic symbol - as they should. 

2) However, if I then try to define signals, and use those to interconnect
the pins of the included components, the RTL schematic doesn't show the
top-level schematic symbols of the included components anymore - it shows
their constituents parts instead. 

See the screenshot for reference: 
http://img408.imageshack.us/img408/5024/isertlschematicmacroins.png

the image on left shows 1) - the image on right shows 2). 

The way I'm trying to experiment is, by placing the individual components
in a top container, making some connections, and then viewing the 'one
below' top level RTL schematic - and then changing either the interfaces of
the components, or changing connections, until things seem right. Of
course, this concept will be possible only if I can display the included
objects with their schematic symbols (or "macros", as I understand they are
called??) . 

Can anyone tell me why this happens, and possibly how to prevent it? 

Thanks, 
Cheers!

	   
					
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Article: 143768
Subject: Re: Time stability of clock on FPGA board
From: Alex <victous@gmail.com>
Date: Sat, 24 Oct 2009 11:18:55 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 24 =D0=BE=D0=BA=D1=82, 00:56, doug <x...@xx.com> wrote:
> Alex wrote:
> > On 23 =C3=8F=C3=8B=C3=94, 20:40, doug <x...@xx.com> wrote:
>
> >>Nico Coesel wrote:
>
> >>>-jg <jim.granvi...@gmail.com> wrote:
>
> >>>>On Oct 23, 11:51=3DA0am, -jg <jim.granvi...@gmail.com> wrote:
>
> >>>>>So, having decided every-cycle precision is not practical, you have =
to
> >>>>>decide over what time you need this 0.1Hz ?
> >>>>>Suppose you need it over 100ms, then you can generate 99,999 cycles =
of
> >>>>>1.00us, and one cycle of
>
> >>>>( oops, Hit the wrong button...)
> >>>>Finishing that example: in a pure digital domain
>
> >>>>For a 100ms time average, of your 1000000.1 Hz, we generate
> >>>>99,999 cycles of 1,00us and one cycle 10ns less
> >>>>Frequency is then Cycles.Time =C2=A0=3D3D
>
> >>>>100000/(99999*1.0u + (1u-10n)) =3D3D 1000000.10000001
>
> >>>>So, you _can_ generate 1MHz to 0.1Hz increments, over multiples of
> >>>>greater than 100ms, with a 10ns timebase.
> >>>>That certainly is FPGA doable.
>
> >>>It certainly is. Years ago I build a DPLL in an FPGA that way for
> >>>synchronising to an E1 line. It has a range of +/- 200ppm in less than
> >>>0.5ppm steps. Its just a matter of skipping or inserting extra clock
> >>>cycles each frame.
>
> >>This works fine for locking to a fixed frequency over a narrow range
> >>and many of us have used it. =C2=A0The deficiency of it is that it is f=
ine
> >>for digital clocks but is bad for analog signals. =C2=A0For generating
> >>arbitrary frequencies, you are better off using a DDS. =C2=A0The DDS is=
 even
> >>available as a coregen element for Xilinx (the digital part anyway).
>
> > Xilinx DDS Compiler seems suitable for my project.
>
> You have to decide if the jitter from this is ok for you. The ways
> of reducing the jitter include increasing the clock rate or by
> feeding the output through a d/a converter with a baseband
> filter. The idea is to use the filter to do the interpolation of
> the zero crossings. This is one of the real nice features of the
> Analog Devices parts. You can clock at hundreds of MHz and for
> low frequency outputs, the jitter is effectively zero.
>
> You never told us what kind of output you really want. A digital
> clock? =C2=A0An audio test signal? =C2=A0What are the distortion and
> purity specs?

Hi doug,

I actually have not decided yet on distortion and purity specs..
The output has to be a train of amplitude modulated RF pulses whose
amplitude, waveform, phase, frequency could be set specifically for
each pulse. Frequency can be in range from 100 kHz to about 50 MHz
(adjustable in steps equal to 0.1 Hz).

Article: 143769
Subject: Virtex 5 I/O
From: "maxascent" <maxascent@yahoo.co.uk>
Date: Sat, 24 Oct 2009 13:53:08 -0500
Links: << >>  << T >>  << A >>


I have a pcb with a Virtex 5 and a programmable clock generator. I want to
use an LVDS clcok signal from the clock gen to the fpga. The problem is
that the clock generators default output is two 3.3V signals. The fpga bank
is connected to 1.8V. I would like to know if this will be a problem having
a 3.3V signal going to a 1.8V bank. Once I have programmed the clock to be
LVDS output it should be ok but there is a brief period with the other
signals. 

Thanks

Jon	   
					
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Article: 143770
Subject: Re: Generating delay using logic gates
From: KJ <kkjennings@sbcglobal.net>
Date: Sat, 24 Oct 2009 12:45:04 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 24, 6:19=A0am, Sharath Raju <brshar...@gmail.com> wrote:

> I tried to delay the signal X using logic gates and xored the delayed
> signal with the original signal, to get pulses whose ON time equals
> the sum of the propagation delay of the logic gates.
>

There are parts called delay lines that generate controlled delays of
specified amounts.  Having a design depend on prop delays through
logic is a design that can be depending upon unspecified behavior.
Does the part you're using specify both a minimum and a maximum prop
delay?  If not, how do you guarantee a minimum pulse width coming
out?  Presumably you have a requirement for that.

> See Fig 2http://brsharath.googlepages.com/24102009001.jpg
>
> Though I am able to see the pulses on the oscilloscope, I see ringing
> at the falling edge of the pulse.
>
> What is the cause of ringing ?, and
>

The output impedance of the driver does not match the impedance of the
circuit board and the receiver.  Add either a ~33 ohm resistor in
series with the output pin or tack on a ~50 ohm resistor to ground
across the output.  Either method will get rid of most of your
ringing.

Kevin Jennings

Article: 143771
Subject: Re: ISE 9.2 - RTL Schematic problem (separating of included components)
From: "sdaau" <sd@imi.aau.dk>
Date: Sat, 24 Oct 2009 15:05:15 -0500
Links: << >>  << T >>  << A >>
Hi all, 

>
>2) However, if I then try to define signals, and use those to
interconnect
>the pins of the included components, the RTL schematic doesn't show the
>top-level schematic symbols of the included components anymore - it shows
>their constituents parts instead. 
>

Right, I think I got it - I stumbled accidentally across this document
which helped:

Xilinx XAPP918 Incremental Design Reuse with Partitions ... - 
http://www.xilinx.com/support/documentation/application_notes/xapp918.pdf

Noobs may have noticed, that when you synthesize in ISE, and then view
Technology/RTL schematics, what you look at is .ngr/.ngc files. So what I
did is this:
- Compiled (that is, synthesized) my design with pins wired to individual
components so the RTL schematic shows.
- After it completes, right-click on all components that should "stay
together", and make them a new partition 
- Synthesize again - one can notice that each element selected as a
partition, now has own .ngc/.ngr file
- Make all changes - i.e. use signals instead of pins - and synthesize
again; now the top schematic symbols of the instances will remain in view,
while the routing between them will change accordingly.

Cheers ! :) 
	   
					
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Article: 143772
Subject: Re: Time stability of clock on FPGA board
From: doug <xx@xx.com>
Date: Sat, 24 Oct 2009 15:46:37 -0800
Links: << >>  << T >>  << A >>


Alex wrote:

> On 24 окт, 00:56, doug <x...@xx.com> wrote:
> 
>>Alex wrote:
>>
>>>On 23 ÏËÔ, 20:40, doug <x...@xx.com> wrote:
>>
>>>>Nico Coesel wrote:
>>
>>>>>-jg <jim.granvi...@gmail.com> wrote:
>>
>>>>>>On Oct 23, 11:51=A0am, -jg <jim.granvi...@gmail.com> wrote:
>>
>>>>>>>So, having decided every-cycle precision is not practical, you have to
>>>>>>>decide over what time you need this 0.1Hz ?
>>>>>>>Suppose you need it over 100ms, then you can generate 99,999 cycles of
>>>>>>>1.00us, and one cycle of
>>
>>>>>>( oops, Hit the wrong button...)
>>>>>>Finishing that example: in a pure digital domain
>>
>>>>>>For a 100ms time average, of your 1000000.1 Hz, we generate
>>>>>>99,999 cycles of 1,00us and one cycle 10ns less
>>>>>>Frequency is then Cycles.Time  =3D
>>
>>>>>>100000/(99999*1.0u + (1u-10n)) =3D 1000000.10000001
>>
>>>>>>So, you _can_ generate 1MHz to 0.1Hz increments, over multiples of
>>>>>>greater than 100ms, with a 10ns timebase.
>>>>>>That certainly is FPGA doable.
>>
>>>>>It certainly is. Years ago I build a DPLL in an FPGA that way for
>>>>>synchronising to an E1 line. It has a range of +/- 200ppm in less than
>>>>>0.5ppm steps. Its just a matter of skipping or inserting extra clock
>>>>>cycles each frame.
>>
>>>>This works fine for locking to a fixed frequency over a narrow range
>>>>and many of us have used it.  The deficiency of it is that it is fine
>>>>for digital clocks but is bad for analog signals.  For generating
>>>>arbitrary frequencies, you are better off using a DDS.  The DDS is even
>>>>available as a coregen element for Xilinx (the digital part anyway).
>>
>>>Xilinx DDS Compiler seems suitable for my project.
>>
>>You have to decide if the jitter from this is ok for you. The ways
>>of reducing the jitter include increasing the clock rate or by
>>feeding the output through a d/a converter with a baseband
>>filter. The idea is to use the filter to do the interpolation of
>>the zero crossings. This is one of the real nice features of the
>>Analog Devices parts. You can clock at hundreds of MHz and for
>>low frequency outputs, the jitter is effectively zero.
>>
>>You never told us what kind of output you really want. A digital
>>clock?  An audio test signal?  What are the distortion and
>>purity specs?
> 
> 
> Hi doug,
> 
> I actually have not decided yet on distortion and purity specs..
> The output has to be a train of amplitude modulated RF pulses whose
> amplitude, waveform, phase, frequency could be set specifically for
> each pulse. Frequency can be in range from 100 kHz to about 50 MHz
> (adjustable in steps equal to 0.1 Hz).

Your life will be a lot simpler if you just use the Analog Devices
parts. The AD9954 or AD9956 will do most of what you want. You will
need an external D/A for the amplitude control.

Article: 143773
Subject: Re: Generating delay using logic gates
From: Sharath Raju <brsharath@gmail.com>
Date: Sat, 24 Oct 2009 20:18:33 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 25, 12:45=A0am, KJ <kkjenni...@sbcglobal.net> wrote:
> On Oct 24, 6:19=A0am, Sharath Raju <brshar...@gmail.com> wrote:
>
> > I tried to delay the signal X using logic gates and xored the delayed
> > signal with the original signal, to get pulses whose ON time equals
> > the sum of the propagation delay of the logic gates.
>
> There are parts called delay lines that generate controlled delays of
> specified amounts.
I wasn't aware of them. Thanks
=A0Having a design depend on prop delays through
> logic is a design that can be depending upon unspecified behavior.
> Does the part you're using specify both a minimum and a maximum prop
> delay? =A0If not, how do you guarantee a minimum pulse width coming
> out? =A0Presumably you have a requirement for that.

I had initially thought of using a 555 monostable multivibrator to
generate pulses of a specified width. The problem is that the
monostable ckt is only falling edge triggered. So I thought of making
a circuit (Fig2 http://brsharath.googlepages.com/24102009001.jpg) that
can recognize both rising and falling edges. and then use it to
trigger the 555.

So as such, I dont have a specific requirement for the width. The only
requirement is to detect both rising and falling edges.


Of course, using delay lines and xor logic, i think the 555 can be
avoided.

>
> > See Fig 2http://brsharath.googlepages.com/24102009001.jpg
>
> > Though I am able to see the pulses on the oscilloscope, I see ringing
> > at the falling edge of the pulse.
>
> > What is the cause of ringing ?, and
>
> The output impedance of the driver does not match the impedance of the
> circuit board and the receiver. =A0Add either a ~33 ohm resistor in
> series with the output pin or tack on a ~50 ohm resistor to ground
> across the output. =A0Either method will get rid of most of your
> ringing.
shall try that and see.

>
> Kevin Jennings
thanks


Article: 143774
Subject: Re: Generating delay using logic gates
From: -jg <jim.granville@gmail.com>
Date: Sat, 24 Oct 2009 22:03:58 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 24, 11:19=A0pm, Sharath Raju <brshar...@gmail.com> wrote:
>
> Are there any alternative ways of generating PWM pulses.

There are many ways of generating PWM pulses.
It depends what is important to you.

 The simplest, for both edges, is as you describe with a XOR gate +
delay element, which can be gates, or a RC, depending on the absolute
times involved. Universal Tiny Logic gates have XOR/XNOR choices,and
schmitt pins.

 Then, issues of jitter, stability and matching come into play, and
they might push you into different solution directions.

As you have failed to give any numbers for any of these, advice is
impossible.
-jg



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