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On Aug 17, 11:46=A0am, "Symon" <symon_bre...@hotmail.com> wrote: > fpgabuilder wrote: > > I am writing some logic that is supposed to work at 80MHz in one mode > > and 40MHz in another. =A0I am wondering if I need to run timing analysi= s > > at both the frequencies? =A0The idea is to use clock muxes to select on= e > > or the other clock during operation. > > > TIA for any insights. > > > Best regards, > > Sanjay > > Run it at 80MHz all the time. Use a clock enable to make it go at 40MHz. > That makes the timing analysis easy. > Syms. This causes the clock network to draw the same amount of power. Using global clocks this is a pretty good hit percentage wise to the system power. We discovered something like 150mW in SL70I4L.Article: 142576
On 2009-08-16, Antti <antti.lukats@googlemail.com> wrote: > no free Assembler). It is using GPL v2 licensed SDCC derived compiler. FWIW, I've used SDCC (for various flavors of PIC) and the output was frequently incorrect and usually poor. This is part of the reason I gave up on PICs in general. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 142577
On Mon, 17 Aug 2009 21:31:03 +0100, "Roger" <rogerwilson@hotmail.com> wrote: >Comparing the Virtex 6 and Spartan 6 devices , one difference is the lack of >any Embedded Memory Controller hard cores in the Virtex 6. These cores look >very useful so why aren't they also included in the V6? Does anyone have a >view? > Speculating... The V6 is probably fast enough that memory cores work just fine using the regular FPGA fabric (with self-calibrating I/O timings as in the V5). But the S6 needs a bit of help to meet the speeds a modern memory inteface requires, so it gets some custom hardware for the purpose; thus neatly converting a drawback into a selling point... Using the fabric in V5 presumably lets you implement any number and style of interface you want, while the embedded HW may only cover a few memory configurations for tha mass market. - BrianArticle: 142578
Please ignore anyone telling you not to mention your timing diagram software. It looks useful and I've played around with it a bit. You give it away for free. No one "runs" usenet so use it as you will as long as you are respectful. I guarantee you that no one cares if you piss off Zheng. It's free software as per your website; not everyone wants to release their source code. As much as I love open source software it isn't the end all be all philosophy on like. "Muzaffer Kal" <kal@dspia.com> wrote in message news:8b8f85dne5la79bf07b262mig9u5tu8tbd@4ax.com... > Hi everyone, > The latest version of GTKWave (3.2.2) windows binary is available > here: http://www.dspia.com/gtkwave.html > > -- > Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Services > http://www.dspia.comArticle: 142579
"Pratap" <pratap.iisc@gmail.com> wrote in message news:1bc417fc-61e2-44d9-a1d4-969ae79a9661@b15g2000yqd.googlegroups.com... > Yes...variance will also do... Well, depending on your need for speed, I can assume you can take your time and build up the necessary sums. The variance is the mean square minus the mean squared (subtle addition of the d means something here). So, your algorithm looks like this: 1. Define two numbers: sum, sumsq 2. Set both to zero to start 3. For each point from 1 to N: sum <= sum + x; sumsq <= sumsq + (x * x); When done: mean <= sum / N; -- Here's the mean if you need it var <= sumsq / N - (mean * mean); Power of two divisions can of course be replaced by shifts, or if you want some form of floating point you are adjusting the exponent and leaving the mantissa alone. If you want the variance of a number stream relative to a forced zero mean you can dispense with the calculation of the mean and just take the sum of squares divided by N. -MartyArticle: 142580
On Aug 17, 12:15 pm, JimLewis <J...@SynthWorks.com> wrote:
> Hi Rick,
> Integers and such are great for sim run time, however, if you are not
> getting the hardware you want, here is an array based algorithm that
> only uses one carry cell to implement the zero detect. It has a few
> extras that you may want to remove. BaseReg is the loadable base
> register. CntReg keeps the current count value. IntReg is a
> registered version of the zero detect.
>
> Best,
> Jim
> SynthWorks VHDL training
>
> TimerProc : process (Clk, nReset)
> variable Dec : unsigned(CntReg'Length downto 0) ;
> begin
> if (nReset = '0') then
> BaseReg <= (others => '0') ;
> CntReg <= (others => '0') ;
> IntReg <= '0' ;
> elsif rising_edge(Clk) then
> if (TimerSel = '1' and Read = '0') then
> BaseReg <= unsigned(DataIn) ;
> end if ;
> Dec := ('0' & CntReg) - 1 ;
> if (Dec(Dec'Left) = '1') then
> CntReg <= BaseReg ;
> else
> CntReg <= Dec(CntReg'Range);
> end if ;
> IntReg <= Dec(Dec'Left) ;
> end if ;
> end process ;
I don't have any problem getting the basic counter to use the carry
chain, but I can not get the carry out for other purposes. The result
seems to depend on size and how the tool is invoked. If I use the
Lattice tool, an 8 bit counter uses 3 LUTs to detect the terminal
count. At 16 bits it duplicates the adder chain and pulls off the
carry out. Using Synplify directly the technology view shows two
adders while the RTL view shows one adder with 24 bits. The carry
comes out of the top and the lower N bits are used for the counter.
Go figure...
Rick
Article: 142581I want to know that why we need to implement the things on the FPGA board. i.e If we can do the post sunthesys netlist simulation then we can verify our synthesized design. Then Why to spend extra money to buy the FPGA board? What's the advantage of each?Article: 142582
On Aug 18, 7:52=A0am, "cris" <viharson...@yahoo.com> wrote: > I want to know that why we need to implement the things on the FPGA board= . To see if the design might actually work in some actual hardware environment. > > If we can do the post sunthesys netlist simulation then we can verify our > synthesized design. Not true. A post-synthesis netlist simulation does not verify correct timing. All timing parameters are specified as a range with a min and a max, a post-synthesis simulation will choose a particular value, not a range. To verify timing, you perform static timing analysis, not a netlist simulation. > Then Why =A0to spend extra money to =A0buy the FPGA board? > Because it might give you a faster way to verify your design in some real hardware prior to getting the final hardware that the FPGA will ultimately be a part of. Plus board designs can have their own design problems. If you're trying to debug your FPGA design, you'd hate to chase a problem that turns out to be a PCBA design issue...unless you're responsible for both in which case getting all the bugs out on the table can be a good thing. Maybe all that is worth something to you, in the end that's why one always spends money. KJArticle: 142583
Tobasco, At least tell me you have the intelligence to tell the difference between gtkwave (which I wholeheartedly support) and timing-diagrams.com (whose intention is still unclear till today). Zheng On Mon, 17 Aug 2009 19:43:06 -0500 "Tobasco" <nothankstoemail@nothanks.com.cx.ch> wrote: > Please ignore anyone telling you not to mention your timing diagram > software. It looks useful and I've played around with it a bit. You > give it away for free. No one "runs" usenet so use it as you will as > long as you are respectful. I guarantee you that no one cares if you > piss off Zheng. It's free software as per your website; not everyone > wants to release their source code. As much as I love open source > software it isn't the end all be all philosophy on like. > > "Muzaffer Kal" <kal@dspia.com> wrote in message > news:8b8f85dne5la79bf07b262mig9u5tu8tbd@4ax.com... > > Hi everyone, > > The latest version of GTKWave (3.2.2) windows binary is available > > here: http://www.dspia.com/gtkwave.html > > > > -- > > Muzaffer Kal > > > > DSPIA INC. > > ASIC/FPGA Design Services > > http://www.dspia.com >Article: 142584
KJ wrote: >> If we can do the post sunthesys netlist simulation then we can verify our >> synthesized design. > > Not true. A post-synthesis netlist simulation does not verify correct > timing. All timing parameters are specified as a range with a min and > a max, a post-synthesis simulation will choose a particular value, not > a range. To verify timing, you perform static timing analysis, not a > netlist simulation. right, as an example, when I began programming in VHDL I developed a stopwatch. The first version was unstable , i.e. some digits did not stop when pressing the stop button - or better they stopped at random. Then next version was stable. I don't know if I would have found that error by only simulating. The EDK threw a warning, but I'd say that it's better to see what happens on real hardware. -TKArticle: 142585
Frank Buss wrote: > Antti.Lukats@googlemail.com wrote: > > > so if you write an AVR program in Assembler > > then assembler that converts the code is not able to figure out > > shortest branch types for all jumps/branches - this just isnt possible > > withing 2 passes > > my compiler uses what he thinks the branch types should be, compiles > > the binary, then checks if there are places where jumps can be > > optimized, does the optimizations, checks the code if there are no > > branches "out of ranges" fixes, and optimizes, doing iterations, up to > > 20 passes or when no more optimizations are possible and fixes are > > needed. > > How much percent do you save with this concept? And I guess good assemblers > does this, too. BTW: this is an interesting article on this topic: > > http://coding.derkeiler.com/Archive/Assembler/alt.lang.asm/2006-11/msg00216.html > > It is interesting to see that none of both common algorithms "start with > all small branches and fix the branches which need to be longer" and "start > with all long branches and adjust all possible branches to small ones" are > perfect, even with 20 passes. The article says, that it is a NP complete > problem, so for an optimal solution you need 2^n passes, where n is the > number of branches. Has anyone a link to the mathematically proof? > > But who cares? Except for pathologically cases I think the approach > starting with small branches would lead to nearly perfect code, maybe 0.1% > longer than perfect :-) But of course, you'll need many passes, not just 2. There are several instruction sets that have both address specific within a page and pc relative instructions where starting with the longest or shortest form does not solve the branch optimization problem. Branch optimization is a NP complete problem. However there are some very fast and good solutions now. Many of the current compilers are using a single pass algorithm to solve the branch selection problem that has as a worst case error if one non optimal branch in the generated code. The algorithm described by antti has a significant problem in the branch selection is unstable and doesn't always converge. The algorithm analyses a single branch at a time and may wind up with a toggling condition in a loop of alliterative passes toggling between two non optimal solutions. In some cases we had cases with loop intervals of 10 or more passes. Regards, -- Walter Banks Byte Craft Limited http://www.bytecraft.comArticle: 142586
On Aug 17, 2:32=A0am, Steve <srk...@gmail.com> wrote: > 4. Using the supplied SPI core with 250E's results in corrupt code > being written to flash causing excess (950mA+) current to be consumed > by VCCint (1V2) and the device failing to execute downloads. We dont > know what is consuming the excess current, but speculate the cause to > be from high speed boot retries of the corrupt code. Interesting... I had a single example of an 250E turn itself into a space heater a few weeks back while working on code for loading it from an embedded processor. It had previously worked flawlessly, as did the replacement. Perhaps there are certain invalid bit streams that will introduce enough internal "shorts" to kill it?Article: 142587
On Aug 4, 6:32=A0am, Steve <srk...@gmail.com> wrote: > Hi Brian, > > Thanks for the solid response. Ill try the things you suggest to see > if that resolves the problem, but I do have a few initial comments on > some of these suggestions; > > > =A0The recommendation to select JTAG mode during indirect > > SPI programming can be found in the newer Xilinx SPI > > programming application notes [Ref 1]. > > --> Thats somewhat dissapointing, as i have an existing design in > production based on their "Designs can migrate between > the XC3S250E and XC3S500E without further consideration." statement > found on page 189 of their DS312 datasheet (who knows if its current, > or true - does it matter?) > > > > > > sorta defeats having a bootable FPGA. > > > =A0Set it to JTAG when you connect the JTAG cable to program > > the SPI flash with Impact, set it back when you are done... > > Hard to do with 0402 components, but ill bolt it on an see what > happends. > > > > > =A0Adding a mode select jumper block hardly reduces the > > functionality of a board, particularly when this mode > > jumper is often needed to use the JTAG port without > > experiencing the sort of problems that you are seeing. > > I think it does. For upgrades, plugging up to the JTAG port and > downloading is a lot easier than including instructions for jumpers, > especially when the product is closed to the world. DS312, it also > states JTAG always gets priority over other methods, well, up until > now. A jumper is a bug fix for this device, for xilinx. Again, may > have to do it, but if I have to spin the board again, its just as easy > for me to put another vendor device on there. > > > > > =A0If you want the mode selection to be automatic, the 2mm > > 14 pin JTAG header pinout can be used to provide a JTAG > > cable detect [Ref 2]. > > --> I dont wish to be tied to just xilinx programmers. Native JTAG > interface is what we are using. JTAG has too many pins as it is. > > > > > > The 500E version works fine without needing to do this. > > > =A0These PROM/JTAG boot conflicts can vary from part to part, > > and between mask steppings of the same device. > > Ive noticed with xilinx, the same part varies as well - going with an > xilinx ES part is suicide. However, since it was spelt out in DS312 > its ok to swap a 250E with a 500E with only code changes, I sorta > thought that meant I could swap between a 250E and a 500E with only > code changes. > > steve Hi Steve, i almost always used own JTAG-SPI bypass soft cores and own PC host software for SPI flash programming (before the feature was added to impact) as I see the impact solution is still a problem. eh it would be so much better if xilinx would supply source code of the spi indirect cores... but they do not :( AnttiArticle: 142588
(excuse if this is a double post - I tried to send this same message via http://www.fpgacentral.com/group/newsgroup/fpga/ but it seems it doesn't send to comp.arch.fpga - so I'm trying again via http://www.fpgarelated.com/usenet/fpga.php) Hi all, I am just starting to learn about FPGA's, and as I found one schematic which I think I can read: The Xilinx Spartan - II Evaluation Board http://www.fpga.synth.net/evalboards/files/fes2_user.pdf .. so, I'd basically like to rebuild this board for learning purposes. The problem is that it uses a programmable oscillator "EPSON’s MG-7010SA selectable-output PLL crystal oscillator", which has been discontinued: http://www.epsontoyocom.co.jp/english/discon/discon_osc.html .. and thus I cannot find it anywhere anymore (although I do get some hits with some russian sites). What I like about this chip, is that the frequency can be controlled via dip switches, as is done in fes2_user.pdf - which means, I don't have to worry about setting frequency through resistors or capacitors (and thus worrying about their value tolerances); nor about setting it through SPI or similar digital interfaces. I have been trying to look for alternatives to this chip, but without any success. Would any in the community have an idea if something similar to that chip currently exists for purchase? (btw I'd prefer RS Components or Farnell as suppliers). If there is no such chip manufactured anymore, what would be, in your opinion, the next best thing to use with the fes2_user.pdf Spartan-2 board? Thanks in advance for any answers... Cheers !!Article: 142589
"Andrew Holme" <ah@nospam.co.uk> wrote in message
news:3%Rhm.249607$bA.175329@newsfe16.ams2...
> I'm implementing BCD adders in a Spartan 3 using instance arrays of these:
>
> module BCD_ADDER (
> input [3:0] a,
> input [3:0] b,
> input cin,
> output cout,
> output [3:0] s);
>
> wire [4:0] unadj = a+b+cin;
> assign {cout, s} = unadj<10? unadj : unadj+6;
> endmodule
>
> This article http://www.edn.com/archives/1996/021596/04di3.htm shows a
> more resource-efficient way to do it, using wider binary adders, requiring
> access to the fast carry chain between slices. The slices have outputs XB
> and YB which tap the carry chain; but I can't get the tools to use them.
> This doesn't do what I want:
>
> module Test(
> input [7:0] a,
> input [7:0] b,
> output [7:0] s,
> output yb
> );
> assign {yb,s[3:0]} = a[3:0]+b[3:0];
> assign s[7:4] = a[7:4]+b[7:4]+yb;
> endmodule
>
> Any tips would be appreciated.
>
> TIA
>
I found the answer: make full adders by instantiating MUXCY and XORCY
elements explicitly.
Article: 142590On Wed, 19 Aug 2009 01:15:35 -0500, "sdaau" <sd@imi.aau.dk> wrote: >(excuse if this is a double post - I tried to send this same message via >http://www.fpgacentral.com/group/newsgroup/fpga/ but it seems it doesn't >send to comp.arch.fpga - so I'm trying again via >http://www.fpgarelated.com/usenet/fpga.php) > >Hi all, > >I am just starting to learn about FPGA's, and as I found one schematic >which I think I can read: > >The Xilinx Spartan - II Evaluation Board >http://www.fpga.synth.net/evalboards/files/fes2_user.pdf >The problem is that it uses a programmable oscillator "EPSON’s MG-7010SA >selectable-output PLL crystal oscillator", which has been discontinued: >What I like about this chip, is that the frequency can be controlled via >dip switches, as is done in fes2_user.pdf - which means, I don't have to >worry about setting frequency through resistors or capacitors (and thus >worrying about their value tolerances); nor about setting it through SPI or >similar digital interfaces. > >I have been trying to look for alternatives to this chip, but without any >success. Would any in the community have an idea if something similar to >that chip currently exists for purchase? Frankly I'd just put down a DIP8 or DIP14 socket and buy a handful of oscillator modules of different frequencies. Why worry about anything more complicated? But then I'd start with a newer FPGA (Spartan-3 at least) which has some form fo internal clock manager (DLL or DCM) to generate a range frequencies related to whatever master clock you supply. (Plus the tools still support it, etc etc) If you haven't found any published Spartan-3 schematics I can only suggest you haven't looked very hard. - BrianArticle: 142591
On Aug 19, 9:15=A0am, "sdaau" <s...@imi.aau.dk> wrote: > (excuse if this is a double post - I tried to send this same message viah= ttp://www.fpgacentral.com/group/newsgroup/fpga/but it seems it doesn't > send to comp.arch.fpga - so I'm trying again viahttp://www.fpgarelated.co= m/usenet/fpga.php) > > Hi all, > > I am just starting to learn about FPGA's, and as I found one schematic > which I think I can read: > > The Xilinx Spartan - II Evaluation Boardhttp://www.fpga.synth.net/evalboa= rds/files/fes2_user.pdf > > .. so, I'd basically like to rebuild this board for learning purposes. > > The problem is that it uses a programmable oscillator "EPSON=92s MG-7010S= A > selectable-output PLL crystal oscillator", which has been discontinued: > > http://www.epsontoyocom.co.jp/english/discon/discon_osc.html > > .. and thus I cannot find it anywhere anymore (although I do get some > hits with some russian sites). > > What I like about this chip, is that the frequency can be controlled via > dip switches, as is done in fes2_user.pdf - which means, I don't have to > worry about setting frequency through resistors or capacitors (and thus > worrying about their value tolerances); nor about setting it through SPI = or > similar digital interfaces. > > I have been trying to look for alternatives to this chip, but without any > success. Would any in the community have an idea if something similar to > that chip currently exists for purchase? (btw I'd prefer RS Components or > Farnell as suppliers). If there is no such chip manufactured anymore, wha= t > would be, in your opinion, the next best thing to use with the > fes2_user.pdf Spartan-2 board? > > Thanks in advance for any answers... > > Cheers !! DO NOT DO NOT make any new board with Spartan-II use s3a, nothing older AnttiArticle: 142592
On 17 Aug., 11:41, Andrew Holme <ajho...@hotmail.com> wrote:
> On 17 Aug, 07:28, backhus <goo...@twinmail.de> wrote:
>
>
>
> > Hi Andrew,
> > first of all, the second approach doesn't handle BCD at all. Just
> > simple binary.
> > Your first module is a single BCD adder that can be used for wider
> > numbers by cascading the adders.
> > The edn paper describes an approach to add wider BCD numbers in a
> > single module, using two adders.
> > One simply adds up the numbers in binary style , the other one adds 6
> > to the result as you did in your module with the line : assign {cout,
> > s} =3D unadj<10? unadj : unadj+6;
> > Then follows a special network of multiplexors to choose the right
> > result of either the first or the second adder.
> > The advantage is that the adders can work straight over all bits, and
> > this makes them use the carry chains. Your first module cant do that
> > because of the BCD-correction.
> > Your module Test doesn't have any correction circuit, and misses the
> > second adder (for 8 bits: +66(dez).)
>
> > a little hint (uncomplete):
>
> > =A0module Test2(
> > =A0=A0input =A0[7:0] a,
> > =A0=A0input =A0[7:0] b,
> > =A0=A0output [7:0] s
> > =A0);
> > =A0 wire yb;
> > =A0 wire yc;
> > =A0=A0assign yb =3D a + b;
> > =A0=A0assign yc =A0=3D yb + 8b01100110;
> > #
> > # =A0add multiplexor structure here to generate output s from yb and yc
> > #
> > =A0endmodule
>
> > Have a nice synthesis
> > =A0 Eilert
>
> The "second approach" was not supposed to be a BCD adder! =A0It's just
> an attempt to persuade the Xilinx tools to use the YB port of a
> Spartan 3 SLICE.
>
> The binary adders in the EDN schematic have intermediate carry outputs
> C4, C8, C12 and D4, D8, D12 e.t.c. =A0Their method relies on getting
> access to the carry chain at these points.
Hi Andrew,
ok, now I understand.
I did some testing too, without success.
The synthesis tool either generates no adder macro at all, or fails at
optimizing away unnecessary LUTs.
If there's no better solution, you probably have to instantiate all
the primitives. (or draw a schematic if you like)
Have a nice synthesis
Eilert
Article: 142593On Aug 19, 2:15=A0am, "sdaau" <s...@imi.aau.dk> wrote: > (excuse if this is a double post - I tried to send this same message viah= ttp://www.fpgacentral.com/group/newsgroup/fpga/but it seems it doesn't > send to comp.arch.fpga - so I'm trying again viahttp://www.fpgarelated.co= m/usenet/fpga.php) > > Hi all, > > I am just starting to learn about FPGA's, and as I found one schematic > which I think I can read: > > The Xilinx Spartan - II Evaluation Boardhttp://www.fpga.synth.net/evalboa= rds/files/fes2_user.pdf > > .. so, I'd basically like to rebuild this board for learning purposes. > > The problem is that it uses a programmable oscillator "EPSON=92s MG-7010S= A > selectable-output PLL crystal oscillator", which has been discontinued: > > http://www.epsontoyocom.co.jp/english/discon/discon_osc.html > > .. and thus I cannot find it anywhere anymore (although I do get some > hits with some russian sites). > > What I like about this chip, is that the frequency can be controlled via > dip switches, as is done in fes2_user.pdf - which means, I don't have to > worry about setting frequency through resistors or capacitors (and thus > worrying about their value tolerances); nor about setting it through SPI = or > similar digital interfaces. > > I have been trying to look for alternatives to this chip, but without any > success. Would any in the community have an idea if something similar to > that chip currently exists for purchase? (btw I'd prefer RS Components or > Farnell as suppliers). If there is no such chip manufactured anymore, wha= t > would be, in your opinion, the next best thing to use with the > fes2_user.pdf Spartan-2 board? > > Thanks in advance for any answers... > > Cheers !! We use the Cypress CY2292F and CY22392F chips. The latter has higher frequency range, but more jitter and cannot run multiple outputs in phase unless the PLL output divisor is one. The former is a bit old, but works well enough to run a DLL in Spartan 2. Either chip requires programming, but they both have three select inputs so you can have up to 8 frequencies selectable by DIP switch. When I first started to use these I was able to obtain a programmed sample from Cypress. The application to generate the JEDEC programming files is available on the Cypress Semi website and is called "CyberClocks". If you search for "programmable oscillator" on the DigiKey website you will find a number of other possibilities. Regards, GaborArticle: 142594
On Wed, 19 Aug 2009 05:09:44 -0700 (PDT), gabor <gabor@alacron.com> wrote: >On Aug 19, 2:15 am, "sdaau" <s...@imi.aau.dk> wrote: >> (excuse if this is a double post - I tried to send this same message viahttp://www.fpgacentral.com/group/newsgroup/fpga/but it seems it doesn't >> send to comp.arch.fpga - so I'm trying again viahttp://www.fpgarelated.com/usenet/fpga.php) >> >> Hi all, >> >> I am just starting to learn about FPGA's, and as I found one schematic >> which I think I can read: >> >> The Xilinx Spartan - II Evaluation Boardhttp://www.fpga.synth.net/evalboards/files/fes2_user.pdf >> >> .. so, I'd basically like to rebuild this board for learning purposes. >> >> The problem is that it uses a programmable oscillator "EPSON’s MG-7010SA >> selectable-output PLL crystal oscillator", which has been discontinued: >> >> http://www.epsontoyocom.co.jp/english/discon/discon_osc.html >> >> .. and thus I cannot find it anywhere anymore (although I do get some >> hits with some russian sites). >> >> What I like about this chip, is that the frequency can be controlled via >> dip switches, as is done in fes2_user.pdf - which means, I don't have to >> worry about setting frequency through resistors or capacitors (and thus >> worrying about their value tolerances); nor about setting it through SPI or >> similar digital interfaces. >> >> I have been trying to look for alternatives to this chip, but without any >> success. Would any in the community have an idea if something similar to >> that chip currently exists for purchase? (btw I'd prefer RS Components or >> Farnell as suppliers). If there is no such chip manufactured anymore, what >> would be, in your opinion, the next best thing to use with the >> fes2_user.pdf Spartan-2 board? >> >> Thanks in advance for any answers... >> >> Cheers !! > >We use the Cypress CY2292F and CY22392F chips. The latter has >higher frequency range, but more jitter and cannot run multiple >outputs in phase unless the PLL output divisor is one. The >former is a bit old, but works well enough to run a DLL in >Spartan 2. Either chip requires programming, but they both >have three select inputs so you can have up to 8 frequencies >selectable by DIP switch. When I first started to use these >I was able to obtain a programmed sample from Cypress. The >application to generate the JEDEC programming files is >available on the Cypress Semi website and is called >"CyberClocks". > >If you search for "programmable oscillator" on the DigiKey >website you will find a number of other possibilities. > >Regards, >Gabor It would be interesting to use a VCO and a trimpot. One could tease the clock frequency to FPGA failure. There are lots of cheap-ish VCOs with octave tuning range. Or make your own, with a trimpot, capacitor, and a TinyLogic schmitt. That might cover a decade. JohnArticle: 142595
My company is intertested in doing emulation of complex CISC superscaler processor using FPGAs. Currently we are not using the FPGA technology but instead using Cadence technology. I would like to hear your views on this. What are the pros and cons of using the FPGA technology? Also if I want to go with the FPGA technology then what are the options? Thanks.Article: 142596
On Aug 18, 11:15=A0pm, "sdaau" <s...@imi.aau.dk> wrote: > (excuse if this is a double post - I tried to send this same message viah= ttp://www.fpgacentral.com/group/newsgroup/fpga/but it seems it doesn't > send to comp.arch.fpga - so I'm trying again viahttp://www.fpgarelated.co= m/usenet/fpga.php) > > Hi all, > > I am just starting to learn about FPGA's, and as I found one schematic > which I think I can read: > > The Xilinx Spartan - II Evaluation Boardhttp://www.fpga.synth.net/evalboa= rds/files/fes2_user.pdf > > .. so, I'd basically like to rebuild this board for learning purposes. > > The problem is that it uses a programmable oscillator "EPSON=92s MG-7010S= A > selectable-output PLL crystal oscillator", which has been discontinued: > > http://www.epsontoyocom.co.jp/english/discon/discon_osc.html > > .. and thus I cannot find it anywhere anymore (although I do get some > hits with some russian sites). > > What I like about this chip, is that the frequency can be controlled via > dip switches, as is done in fes2_user.pdf - which means, I don't have to > worry about setting frequency through resistors or capacitors (and thus > worrying about their value tolerances); nor about setting it through SPI = or > similar digital interfaces. > > I have been trying to look for alternatives to this chip, but without any > success. Would any in the community have an idea if something similar to > that chip currently exists for purchase? (btw I'd prefer RS Components or > Farnell as suppliers). If there is no such chip manufactured anymore, wha= t > would be, in your opinion, the next best thing to use with the > fes2_user.pdf Spartan-2 board? > > Thanks in advance for any answers... > > Cheers !! If you don't need the "rock-stable" frequency of a crystal oscillator, you can use 3 pins of the FPGA, 2 resistors and one capacitor, and build a surprisingly stable adjustable oscillator (google "Xilinx six easy pieces") More importantly, do not start fresh with an obsolete design, go for Spartan 3. Even more importantly: When you design and make your own multi-layer pc board, you will struggle with, and hopefully learn many things, like signal integrity, soldering of surface-mount components etc. You need to master that before you even start designing the logic inside the FPGA. My advice: Buy a ready-made, populated and tested board for $50 to 150, and save yourself a lot of grief and time. Then you can concentrate on the real job. Always minimize the number of unknown obstacles... Peter Alfke, Xilinx Applications.Article: 142597
Seeing as you are posting from AMD, I don't think FPGAs are going to give you respectable results for say a x86 compatible processor. But, if you can give a better idea of the entire feature set and desired frequency, readers could give a more tailored answer. I know Intel research uses FPGAs for much of their processor and feature research, but not for implementing their entire commercial processor. ---Matthew Hicks > My company is intertested in doing emulation of complex CISC > superscaler processor using FPGAs. Currently we are not using the > FPGA technology but instead using Cadence technology. I would like to > hear your views on this. What are the pros and cons of using the FPGA > technology? Also if I want to go with the FPGA technology then what > are the options? > > Thanks. >Article: 142598
Matthew Hicks wrote: > Seeing as you are posting from AMD, I don't think FPGAs are going to give > you respectable results for say a x86 compatible processor. But, if you > can give a better idea of the entire feature set and desired frequency, readers > could give a more tailored answer. I know Intel research uses FPGAs for > much of their processor and feature research, but not for implementing their > entire commercial processor. It seems like this article describes a setup with a Virtex 4, which implemented a Pentium: http://portal.acm.org/citation.cfm?id=1216927 So maybe a Virtex 6 could be used for more modern CPUs, but maybe not at full speed, just for testing the functionality in real hardware. For Virtex 5 there are ASIC development boards, like this one with 16 LX330s: http://www.dinigroup.com/DN9000k10.php I didn't found the price, but I think this is really expensive :-) There are other boards, like this one, with 100 Spartan FPGAs: http://www.enterpoint.co.uk/merrick/merrick1.html Maybe they are not as fast as Virtex FPGAs, but it could be more cost effective. And there are some nice boards with Altera Stratix: http://www.dinigroup.com/index.php?product=DN7020k10 With 50 million ASIC gates you can emulate multiple Pentium CPUs (but not with full cache). -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 142599
Iam using XPS 8.2i.I have built a custom peripheral and attached it to MicroBlaze (v 5.0) via OPB bus.My peripheral generates the two interrupts.These interrupts pins are input to the interrupt controller INTC (1.00 c). Initially both interrupts are disabled.Then only high priority interrupt is enabled. What my objective is that when a high priority interrupt occurs:in its ISR it should disabled itself and enabled the other interrupt on interrupt controller. But actually what is happening that when high priority interrupt is occurred it goes into its ISR and it doesnot disable itself.the other interrupt is enabled and the microblaze is stuck in handling both the interrupts. Any help in this regard is welcomed!
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