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"apalopohapa" <mr.arango@gmail.com> wrote:
>Hello.
>
>I am using a global buffer input as clock input, the signal then goes
>through a DCM, and I need to output the inverted clock through a pin into
>another chip. Can I use any pin for this clock output or are there
>specific pins that better serve this purpose?
You can use any pin. Its best to use a DDR flipflop in the IOB.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 144576On Dec 14, 5:40=A0am, "ines_fr" <benhlima_i...@yahoo.fr> wrote: > hello, > > I am using spartan 3 starter board (with MB7.1) to work with 2 processors > cores using EDK10.1 (my reference is the Xilinx tutorial XAPP996). I want > to add, between the two processors, a shared memory BRAM_block_v1_00_a wi= th > the controler xps_bram_if_cntlr_v1_00_a. > > the problem is: when I want to share the bus of the bram controller =A0SP= LB, > changing the parameter C_SPLB_P2P to 0, nothing happens and the SPLB bus > does not connect the two buses mb_plb_0 and mb_plb_1 respectively of the > fist CPu and the the second. > if someone has an idea please help me because I'm stuck. :( > Thanks in advance > > INES =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com You should be able to add two BRAM controllers (not a BRAM), one connected to each processor's PLB, and add a single BRAM. Connect one of the BRAM's two ports (A or B) to one BRAM controller, and connect the other BRAM port to the other BRAM controller. I'm not sure how the address mapping will work out. I haven't done exactly this, but I have run a BRAM interface to external ports, to interface to a BRAM that is outside of the EDK project (in ISE). DaveArticle: 144577
>On Mon, 14 Dec 2009 01:02:25 -0800 (PST), Ben Jones <benjjuk@gmail.com> wrote: > >>On Dec 11, 6:07�pm, Mike Treseler <mtrese...@gmail.com> wrote: >> >>> True, but it simplifies simulation having a reset >>> for the input and output registers, even if (especially if ?) >>> the rams and some shifters don't have one. >> >>I agree that it's a Very Good Idea to have a reset, but I don't see >>why it has to be an asynchronous one. By default I try to make >>everything synchronous, including resets, unless there is a strong >>case to do otherwise. I have found that this leads to fewer problems >>throughout implementation. > >For most of the design I would agree. > >I confess I once had trouble with synchronous resets on clock generators, DCMs >and the like. (The clock stops, so they never come out of reset.) > >So there are occasional roles for asynch reset... > >- Brian > Can any one Give Xct Code for this .. it would be great help for me .. In advance thanks ... --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144578
On 15 Dez., 07:24, "Joshi & Joshi" <joship...@gmail.com> wrote: > my problem is before writing vhdl Code i want generate timings ADC to > FPGA but > > (1) i don no what is this timing generation ? > (2) why this necessary before Code ? We also don't know. I find it really hard from your post to understand what it is that you need. Maybe you are talking about a testbench that when run in a simulator creates the waveforms that you see in the data sheet so that you can see whether your hdl code reacts correctly to them? In this case you can do stuff like this: wait for 10ns; cs <= '1'; wait for 5ms; .... Kolja SulimmaArticle: 144579
On 14 Dez., 23:58, "dlopez" <d...@designgame.ca> wrote: > > Now I only saw problems and corner cases with this approach. The PC, which > is sending the data and commands, does not have easy visibility on the FPGA > FIFO, so it doesn't really know the right mix of data/command to send. I think you did not understand what I meant. What you are talking about is having control and data in one stream. This gives you all the potential problems you describe. I was talking about splitting the FIFO on a cycle by cycle basis and wasting half of the bandwidth of the fifo to tell the FPGA what stream a byte belongs to by packing bytes into 16 bit words. Do the math: Half of 60MB/s is still more than the 25MB you get from the async FIFO. The handling of the streams should be implemented in the USB chips firmware. The PC should not need to know about this. > Then one command, > somewhere between my C# code and the FPGA, might get stuck in the pipeline > since the FPGA won't grab more data from the USB chip. In this approach the FPGA should allways empty the USB chip FIFO.There is nothing to loose because it does not matter which FIFO overflows if the sink is stuck. I believe that in this case the packet approach that you suggested is save and it has even more performance. Kolja SulimmaArticle: 144580
>On Dec 14, 5:40=A0am, "ines_fr" <benhlima_i...@yahoo.fr> wrote: >> hello, >> >> I am using spartan 3 starter board (with MB7.1) to work with 2 processors >> cores using EDK10.1 (my reference is the Xilinx tutorial XAPP996). I want >> to add, between the two processors, a shared memory BRAM_block_v1_00_a wi= >th >> the controler xps_bram_if_cntlr_v1_00_a. >> >> the problem is: when I want to share the bus of the bram controller =A0SP= >LB, >> changing the parameter C_SPLB_P2P to 0, nothing happens and the SPLB bus >> does not connect the two buses mb_plb_0 and mb_plb_1 respectively of the >> fist CPu and the the second. >> if someone has an idea please help me because I'm stuck. :( >> Thanks in advance >> >> INES =A0 =A0 =A0 >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> This message was sent using the comp.arch.fpga web interface onhttp://www= >.FPGARelated.com > >You should be able to add two BRAM controllers (not a BRAM), one >connected to each processor's PLB, and add a single BRAM. Connect one >of the BRAM's two ports (A or B) to one BRAM controller, and connect >the other BRAM port to the other BRAM controller. I'm not sure how the >address mapping will work out. I haven't done exactly this, but I have >run a BRAM interface to external ports, to interface to a BRAM that is >outside of the EDK project (in ISE). > >Dave > Hi, thank you for the idea that helped me a lot! thank you again!!! :)))) INES --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144581
On Dec 16, 6:56=A0am, "Joshi" <Joship...@gmail.com> wrote:
> Can any one Give Xct Code for this ..
> it would be great help for me ..
I for one have no idea what "Xct Code" might be. Two people have
already posted some VHDL which improves on the original code you
posted, and others have given useful advice.
There are plenty of introductory textbooks that run through this sort
of material. If you are seeking a better understanding of digital
design for its own sake, you will find plenty of people willing to
help you here. If, on the other hand, all you want is for someone to
present you with a fully working solution to a homework problem,
there's unlikely to be much sympathy around...
-Ben-
Article: 144582>>On Dec 14, 5:40=A0am, "ines_fr" <benhlima_i...@yahoo.fr> wrote: >>> hello, >>> >>> I am using spartan 3 starter board (with MB7.1) to work with 2 >processors >>> cores using EDK10.1 (my reference is the Xilinx tutorial XAPP996). I >want >>> to add, between the two processors, a shared memory BRAM_block_v1_00_a >wi= >>th >>> the controler xps_bram_if_cntlr_v1_00_a. >>> >>> the problem is: when I want to share the bus of the bram controller >=A0SP= >>LB, >>> changing the parameter C_SPLB_P2P to 0, nothing happens and the SPLB >bus >>> does not connect the two buses mb_plb_0 and mb_plb_1 respectively of >the >>> fist CPu and the the second. >>> if someone has an idea please help me because I'm stuck. :( >>> Thanks in advance >>> >>> INES =A0 =A0 =A0 >>> >>> --------------------------------------- =A0 =A0 =A0 =A0 >>> This message was sent using the comp.arch.fpga web interface >onhttp://www= >>.FPGARelated.com >> >>You should be able to add two BRAM controllers (not a BRAM), one >>connected to each processor's PLB, and add a single BRAM. Connect one >>of the BRAM's two ports (A or B) to one BRAM controller, and connect >>the other BRAM port to the other BRAM controller. I'm not sure how the >>address mapping will work out. I haven't done exactly this, but I have >>run a BRAM interface to external ports, to interface to a BRAM that is >>outside of the EDK project (in ISE). >> >>Dave >> >Hi, >thank you for the idea that helped me a lot! thank you again!!! >:)))) > > >INES > >--------------------------------------- >This message was sent using the comp.arch.fpga web interface on >http://www.FPGARelated.com > Hi, Is that you know how many processors can be integrated on spartan 3 starter boards??? Thanks INES --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144583
On Dec 16, 12:56=A0am, "Joshi" <Joship...@gmail.com> wrote: > Can any one Give Xct Code for this .. > it would be great help for me .. > > In advance thanks ... =A0 =A0 =A0 Joshi, This purpose of this group is to help you to understand and use vhdl, not to find someone else to understand and use vhdl for you (unless you are trying to hire someone). You have been given "xct code" for your circuit that implements an asynchronous reset. If you are looking for "xct code" that implements a synchronous reset, I would suggest you google "vhdl synchronous reset" and apply what you learn from that to the example you have already been given. AndyArticle: 144584
Hello, I am a beginner in FPGA design and try to learn using material presented at http://ecasp.ece.iit.edu/fpdesign.html which relies on XPS 7.1i and allows to add cores by click Project->Add/Edit Cores at top of Xilinx Platform Studio window. However I use XPS 9.1i where there is no 'Add/Edit Cores' option in Project menu. Hence, I am interested how to add a core in XPS 9.1i? Thank you.Article: 144585
I am wondering the same thing too. Have you solve your problem? Regards HV --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144586
>The VHDL code below was used to start up some >video interface chips that have a quite a few >control registers. > Hi, Thanks a lot for the code. However, this seems more like a replacement for the opencores.org I2C master core! I was wanting to use this core since it supports all the 'harder-to-support' I2C specifications and it has been debugged for quite a while now. The only problem is that it only brings things up to the 'byte' level. There still needs to be a fair level of handshaking and pooling in order to generate a transfer of the type'write ABCD at address 08'. Anyone has done it with a picoblaze? This would seem like quite a nice way to go... Diego --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 144587
Hello everybody, someone knows if the Actel Igloo(s) devices can be partial reconfigured like xilinx devices do? It is not important if this is supported by the software, I just need to know if this is theorically possible. Any idea is welcome!!! Thank you PRGArticle: 144588
Paolo Roberto Grassi wrote: > Hello everybody, > someone knows if the Actel Igloo(s) devices can be partial > reconfigured like xilinx devices do? > It is not important if this is supported by the software, I just need > to know if this is theorically possible. Don't really know much about these devices but I believe Actle devices are usually flash-based, not SRAM-based like Xilinx devices. As far as I know, partial reconfiguration only works on SRAM-based devices. HTH, SeanArticle: 144589
On Dec 7, 1:18=A0am, water <water9...@yahoo.com> wrote: > Anyone have TCP/IPoffload(TOE) core in FPGA or design experience? I have one of these coming: http://www.orangetreetech.com/fpga_board_zestet= 1.html If it lives up to its billing it'll be a great development board. Seems ideal for high-bandwidth applications where you don't want to do all of the Ethernet work yourself. Anyone else have any experience with the ZestET1? -- john, KE5FXArticle: 144590
Hi everyone, The latest version of GTKWave (3.3.0 preliminary with TCL/TK 8.5) windows binary is available here: http://www.dspia.com/gtkwave.html -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 144591
On Dec 16, 6:01=A0pm, Alex <vict...@gmail.com> wrote: > Hello, > > I am a beginner in FPGA design and try to learn using material > presented athttp://ecasp.ece.iit.edu/fpdesign.htmlwhich relies on > XPS 7.1i and allows > to add cores by click Project->Add/Edit Cores at top of Xilinx > Platform Studio window. > > However I use XPS 9.1i where there is no 'Add/Edit Cores' option in > Project menu. > > Hence, I am interested how to add a core in XPS 9.1i? > > Thank you. Hello, I have XPS 11.3 on a linux machine. If you mean page 8 of the tutorial (create a new soft-core system) what you maybe should do is File - New Peoject and use the wizard. If you mean page 18 of the tutorial (you have a system and you want to add your own IP) what you maybe should do is Hardware - Create or import Peripherals. I hope this helps. Good luck, fab. Ps I am a beginner tooArticle: 144592
Tobasco, At least tell me you have the intelligence to tell the difference between gtkwave (which I wholeheartedly support) and timing-diagrams.com (whose intention is still unclear till today). Zheng On Mon, 17 Aug 2009 19:43:06 -0500 "Tobasco" - Hide quoted text - <nothankstoem...@nothanks.com.cx.ch> wrote: > Please ignore anyone telling you not to mention your timing diagram > software. It looks useful and I've played around with it a bit. You > give it away for free. No one "runs" usenet so use it as you will as > long as you are respectful. I guarantee you that no one cares if you > piss off Zheng. It's free software as per your website; not everyone > wants to release their source code. As much as I love open source > software it isn't the end all be all philosophy on like. I guess I don't see the big deal? What does it matter what the intentions of timing_analyzer are? I guess if you become dependent on the software and the project dies, it could be frustrating? But in either case small plugs for the software should be tolerable (not much different than having a company signature at the end of each post). Timing analyzer is still free software and others have found benefit and use out of the project. I am not bothered by the posts for Timing analyzer. chrisArticle: 144593
My apologies if this has been addressed - my web searches came up
empty.
I am using a DCM in a spartan3 to generate the internal clocks - a 1-X
clock and a 1/2-X clock.
The output of the DCM goes to a BUFG. The output of the BUFG goes to
the feedback pin of the DCM, and to the rest of the logic.
After initialization, the input clock changes frequency. Shortly
after that, I send a reset (7 clock wide) to the DCM.
The locked signal from the DCM goes away about 22uS after the input
clock changes. I see a short pulse on status[1] indicating that it
didn't like the input clock, and 22uS later Locked goes low.
About 20uS after that, I send the reset pulse to the DCM. Locked
never (never) goes high again.
The output clock is present, but the logic is behaving like the
warning on pg 15 of Xapp462 ("can exhibit glitches, spikes, or other
spurious behavior") is very true.
Any clues, hints, sympathy?
Redards,
Gary.
Article: 1445941) Has anybody designed a board that will work with all members of the Spartan3A family in an FT256? Do you use any special pin programming on, for example an XC3S400A, to keep it from pulling excessive current when it's in the transition region because it's connected to VCCINT (because that pin site is a VCCINT pin in an XC3S700A/XC321400A)? Also, it seems like the extra startup current (before configuration) for all the XC3S700A/XC3S1400A VCCINT/GND pins which are I/O pins in an XC3S400 would be in the range of 10 mA or so for the XC3S400. Does that sound about right? 2) The Spartan 3A documentation states that LVDS output can only be used on banks 0 and 2. It also states that internal 100 ohm LVDS receive termination is only available on pins that are output pins, but it doesn't explicitly state whether this includes output pins in banks 1 and 3, or whether "output" in this context means "pins which are capable of LVDS output" (which would only include pins in banks 0 and 2). I suppose for question 2 I can fairly easily fire up ISE and find the answer. Maybe I'll do that tomorrow. Thanks, PatArticle: 144595
On Dec 18, 5:52=A0pm, ghelbig <ghel...@lycos.com> wrote:
> My apologies if this has been addressed - my web searches came up
> empty.
>
> I am using a DCM in a spartan3 to generate the internal clocks - a 1-X
> clock and a 1/2-X clock.
>
> The output of the DCM goes to a BUFG. =A0The output of the BUFG goes to
> the feedback pin of the DCM, and to the rest of the logic.
>
> After initialization, the input clock changes frequency. =A0Shortly
> after that, I send a reset (7 clock wide) to the DCM.
>
> The locked signal from the DCM goes away about 22uS after the input
> clock changes. =A0I see a short pulse on status[1] indicating that it
> didn't like the input clock, and 22uS later Locked goes low.
>
> About 20uS after that, I send the reset pulse to the DCM. =A0Locked
> never (never) goes high again.
>
> The output clock is present, but the logic is behaving like the
> warning on pg 15 of Xapp462 ("can exhibit glitches, spikes, or other
> spurious behavior") is very true.
Is the new input clock frequency within the valid frequency range for
using feedback? (That range is a lot smaller than if you are only
using the DFS).
Also, I know Xilinx says it will reset after 4 clocks, but for some
reason I always seem to reset for longer than that. Can't remember if
I've ever been burned or if it just seemed to work out that way.
Regards,
Pat
Article: 144596Our Craignell2 DIL module http://www.enterpoint.co.uk/component_replacement= s/craignell2.html has been built with FPGA parts from the XC3S200A to XC3S1400A in the FTG256 package. We did to confirm that we didn't have pinning issues. We didn't bother with the XC3S50A because it caused to many issues with pins in the design. I think the XC3S700A and XC3S1400A were afterthoughts in the family and hence the power pin moves on those parts. The derivative development board product Drigmorn2 is being built with XC3S700A but we will probably build it with other chip fits for OEM customers. Whilst these boards were not built to support LVDS we avoided a lot of pin problems by not using pins that become input only on any of the variants. This does cut down the usable pins a lot and one of my pet hates of an otherwise good family. Interestingly Spartan-6 looks a lot better in this respect and we put a lot LVDS support into Drigmorn3 the next member of the family. For LVDS output you are restricted to banks 0 and 2. For inputs use any bank. We have not had any problems with excessive power either. John Adair Enterpoint Ltd. - Home of Drigmorn2. The Spartan-3A Starter Board. On 19 Dec, 05:48, Patrick Maupin <pmau...@gmail.com> wrote: > 1) Has anybody designed a board that will work with all members of the > Spartan3A family in an FT256? =A0Do you use any special pin programming > on, for example an XC3S400A, to keep it from pulling excessive current > when it's in the transition region because it's connected to VCCINT > (because that pin site is a VCCINT pin in an XC3S700A/XC321400A)? > Also, it seems like the extra startup current (before configuration) > for all the XC3S700A/XC3S1400A VCCINT/GND pins which are I/O pins in > an XC3S400 would be in the range of 10 mA or so for the XC3S400. =A0Does > that sound about right? > > 2) The Spartan 3A documentation states that LVDS output can only be > used on banks 0 and 2. =A0It also states that internal 100 ohm LVDS > receive termination is only available on pins that are output pins, > but it doesn't explicitly state whether this includes output pins in > banks 1 and 3, or whether "output" in this context means "pins which > are capable of LVDS output" =A0(which would only include pins in banks 0 > and 2). > > I suppose for question 2 I can fairly easily fire up ISE and find the > answer. =A0Maybe I'll do that tomorrow. > > Thanks, > PatArticle: 144597
Don't rely on the locked signal for anything. Use the status lines and
make your own locked signal.
The DCM does take a while to fully lock up during which time you will
get strange frequencies and strange mark/space ratios. If you are
trying to do something like a power saving frequency switch you might
be better either to use clock enables to change effective clock rate
or alternatively using an external synthesiser that supports these
sort of frequency changes a bit more elegantly.
John Adair
Enterpoint Ltd.- Home of Merrick1. The Data Mining Solution.
On 18 Dec, 23:52, ghelbig <ghel...@lycos.com> wrote:
> My apologies if this has been addressed - my web searches came up
> empty.
>
> I am using a DCM in a spartan3 to generate the internal clocks - a 1-X
> clock and a 1/2-X clock.
>
> The output of the DCM goes to a BUFG. =A0The output of the BUFG goes to
> the feedback pin of the DCM, and to the rest of the logic.
>
> After initialization, the input clock changes frequency. =A0Shortly
> after that, I send a reset (7 clock wide) to the DCM.
>
> The locked signal from the DCM goes away about 22uS after the input
> clock changes. =A0I see a short pulse on status[1] indicating that it
> didn't like the input clock, and 22uS later Locked goes low.
>
> About 20uS after that, I send the reset pulse to the DCM. =A0Locked
> never (never) goes high again.
>
> The output clock is present, but the logic is behaving like the
> warning on pg 15 of Xapp462 ("can exhibit glitches, spikes, or other
> spurious behavior") is very true.
>
> Any clues, hints, sympathy?
>
> Redards,
> Gary.
Article: 144598
Details I should have included:
The external clock is a synthesizer that defaults to 50MHz. After
initialization, it is changed to 100MHz. The DCM is used to reduce
the skew between the internal clock and the external clock and create
a half-speed clock for some of the logic.
Some percentage of the time, the chip "just don't run"; my current
theory is that the clock comes up strange.
I'm not getting anything useful from the status lines. At the time
the frequency is changed, I get a pulse on status[1]; after that, they
are always low. I've waited "forever", and the locked signal never
goes true.
Thanks!
On Dec 19, 2:36 am, John Adair <g...@enterpoint.co.uk> wrote:
> Don't rely on the locked signal for anything. Use the status lines and
> make your own locked signal.
>
> The DCM does take a while to fully lock up during which time you will
> get strange frequencies and strange mark/space ratios. If you are
> trying to do something like a power saving frequency switch you might
> be better either to use clock enables to change effective clock rate
> or alternatively using an external synthesiser that supports these
> sort of frequency changes a bit more elegantly.
>
> John Adair
> Enterpoint Ltd.- Home of Merrick1. The Data Mining Solution.
>
> On 18 Dec, 23:52, ghelbig <ghel...@lycos.com> wrote:
>
> > My apologies if this has been addressed - my web searches came up
> > empty.
>
> > I am using a DCM in a spartan3 to generate the internal clocks - a 1-X
> > clock and a 1/2-X clock.
>
> > The output of the DCM goes to a BUFG. The output of the BUFG goes to
> > the feedback pin of the DCM, and to the rest of the logic.
>
> > After initialization, the input clock changes frequency. Shortly
> > after that, I send a reset (7 clock wide) to the DCM.
>
> > The locked signal from the DCM goes away about 22uS after the input
> > clock changes. I see a short pulse on status[1] indicating that it
> > didn't like the input clock, and 22uS later Locked goes low.
>
> > About 20uS after that, I send the reset pulse to the DCM. Locked
> > never (never) goes high again.
>
> > The output clock is present, but the logic is behaving like the
> > warning on pg 15 of Xapp462 ("can exhibit glitches, spikes, or other
> > spurious behavior") is very true.
>
> > Any clues, hints, sympathy?
>
> > Redards,
> > Gary.
Article: 144599On Dec 9, 6:14 pm, "moonlight721" <245298...@qq.com> wrote: > >On Dec 9, 6:39=3DC2=3DA0am, "moonlight721" <245298...@qq.com> wrote: > >> Hi > > >> Thanks for the HELP in advance > > >> I use the EDK9.1i to make my design=3DEF=3DBC=3D8Cthen I come to the E= DK10.1 > to=3D > > update > >> my > >> design=3DEF=3DBC=3D8C that works half year ago=3DEF=3DBC=3D8Cbut for n= ow=3DEF=3DBC=3D8Cit > d=3D > >oes not work=3DEF=3DBC=3D81The > >> error is =3DE2=3D80=3D9C No license for component <plb_uart16550_v1_00= _c> > found=3D > >=3DE2=3D80=3D9D > >> =3DEF=3DBC=3D8Csince I made my design in EDK9.1i thus I used the > >> =3DE2=3D80=3D9Cplb_uart16550_v1_00_c=3DE2=3D80=3D9D=3DEF=3DBC=3D8Cbut = it works > before=3DEF=3DBC=3D > >=3D8Cbut now it doesn't=3DEF=3DBC=3D8C > >> could you help me find out the problem=3DEF=3DBC=3D81 Is it the > plb_uart16550_v=3D > >1_00_c > >> cann't use in EDK10.1 anymore=3DEF=3DBC=3D9F Or the other reason=3DEF= =3DBC=3D9F > >> my board is Virtex II pro 30 > > >> Thanks again > > >Looking at the error message =3DE2=3D80=3D9CNo license for component > ><plb_uart16550_v1_00_c> found=3DE2=3D80=3D9D my guess is that you don't = have a > >license for that component. > > >No license, you can't use it. You could either design it out, or get > >a license for it. > > >My suspicion is that you're using an illicit copy of ISE/EDK. Good > >luck with that. > > >AL > >Thanks for your answer=EF=BC=81 > > I find out the answer=EF=BC=8C I change the system time to 2009.3.10=EF= =BC=8Cthen I can > use it=E3=80=82 > When I setup the EDK&ISE on my computer it comes up with =E2=80=9Cthe lic= ence > setup failed=E2=80=9D I think this is the problem=EF=BC=8C could you help= me how can I > solve this problem=EF=BC=9F=EF=BC=88But The ISE&EDK software is applied f= rom the Xilinx > company=EF=BC=81=EF=BC=89 > Thanks again=EF=BC=81 > > --------------------------------------- > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com It looks like you are using an expired license. That still counts as illicit software. As much as I dislike Xilinx's licensing policy, I work with it to get my job done. Contact Xilinx and get a new license. AL
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