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melinda wrote: > Is there a way of viewing the internal signals declared in the instantiated > verilog modules in Modelsim in wave window? add wave -r /*Article: 143926
Antti <antti.lukats@googlemail.com> wrote:
>On Nov 2, 8:36=A0pm, Frank Buss <f...@frank-buss.de> wrote:
>> Nico Coesel wrote:
>> > NXP's LPC1700 series (Cortex M3) is probably cheaper and has at least
>> > 5 times more performance.
>>
>> You are right, the chip is interesting. The smallest one of the LPC1700
>> family with network support costs about the same as the W7100, but has an
>> additional DAC, ADC and USB:
>>
>> http://search.digikey.com/scripts/DkSearch/dksus.dll?vendor=3D0&keyword..=
>.
>>
>> --
>> Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-sys=
>tems.de
>
>yes and no, I have the LPC1768 sample on my desk, yet i consider the
>W7100
>interesting too. LPC1768 has no ethernet PHY and W7100 has lots of
>ethernet
>"in hardware" so for tasks where you need ETH+something and do not
>need
>the extras the W7100 maybe better
But what if you want something special? I bet the hardware tcp/ip
stack is very limited. I have been using the LPC2000 series (even the
ones without MAC) within IP networks for several years now and
sometimes you really need some extra flexibility.
Also beware of internal PHYs. The process for a good phy is different
than for a good microcontroller. You'll probably end up with a power
guzzling controller. Last year I evaluated a Freescale controller with
internal phy. It consumed about 1W and required a 4 layer board for
adequate heat sinking.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 143927Hi all, I'm having a problem where I'm not getting initialized how I expect after startup on a Spartan-3E. For example, one of my state machines is not in its initial state after startup, even though that state is coded all zeros. I don't have access to an external reset, so I have to generate one internally somehow... Does anyone have any ideas? Thanks, EdArticle: 143928
Hi Melinda, Can we assume that you are adding the internal signals with some GUI commands like this: View - Workspace - browse for your entitiy - Right Click - Add - Add to Wave Brad Smallridge AiVision "melinda" <melinda.mel3@gmail.com> wrote in message news:Soudna7GPeTPo23XnZ2dnUVZ_vWdnZ2d@giganews.com... > Hi all, > > I am simulating a entity with Modelsim (v6.5c). Modelsim > only displays the input/output signals of the simulated top entity. > > When I run simulation Modelsim displays only changes of input/output > signals of the top entity verilog module i.e. testbench (in objects window > i.e. in wave window), but nothing happening with signals declared in the > instantiated verilog modules. > (PS: In Cadence SimVision, I know that I was able to see changes of all > signals in testbench and also in instantiated verilog modules, in wave > window) > > Is there a way of viewing the internal signals declared in the > instantiated > verilog modules in Modelsim in wave window? > > Thanks very much > > Regards > > >Article: 143929
nico@puntnl.niks (Nico Coesel) writes: > guzzling controller. Last year I evaluated a Freescale controller with > internal phy. It consumed about 1W and required a 4 layer board for > adequate heat sinking. Was that the M52235? I have a couple eval boards that does not seem to get hot at all. They can also run PoE. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 143930
On Nov 2, 12:46=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Sun, 1 Nov 2009 09:58:10 -0800 (PST), Ben Jones <benj...@gmail.com> wr= ote: > >On Oct 30, 11:14=A0pm, Brian Drummond <brian_drumm...@btconnect.com> > >wrote: > >> ... snip ... > > >> for a reasonably large ROM, or a complex function (e.g. function calls= nested 4 > >> levels deep) XST will take an unbelievably long time to synthesise it.= There's > >> an N^2 algorithm in there somewhere; if it takes 15 minutes for a 1000= element > >> array, it'll take an hour for 2000 elements, 4 hours for 4000, etc... > > >Is this *still* happening? This has been CRed so many times, and I > >know it's been fixed for at least some of the test cases we came up > >with internally... if you have some example code that exhibits this in > >the latest ISE, and you're willing to share it, let me know and I'll > >try to beat the XST team around the head with it again. :-/ > > I have been informed by a student employee it's still true in ISE11.1 but > haven't verified it myself. Will check in the next couple of days and ema= il you > privately. > > Alternatively you may be able to access a pathological testcase attached = to > Webcase 717144, as used by above student. > > It asserts on every LUT entry, so you can watch it slow down... (and no, = the > assert is not the performance bottleneck!) > > - Brian Thanks, Brian. I'll check it out.Article: 143931
On Nov 3, 2:25=A0pm, ed <ed.agu...@gmail.com> wrote:
> Hi all,
>
> I'm having a problem where I'm not getting initialized how I expect
> after startup on a Spartan-3E.
>
> For example, one of my state machines is not in its initial state
> after startup, even though that state is coded all zeros.
>
> I don't have access to an external reset, so I have to generate one
> internally somehow...
>
> Does anyone have any ideas?
>
> Thanks,
> Ed
Standard practice on Xilinx devices when you have no reset signal
is to instantiate a few flip-flops to form a short shift register.
For an active high reset, use FDP (asynch preset, also preset on
start-up / config). In verilog it looks like:
wire [2:0] rst_sr;
wire sys_reset;
FDP rst_ffs [3:0]
(
.D ({rst_sr,1'b0}), // shift in zero from right
.Q ({sys_reset,rst_str}),
.PRE (1'b0), // Only preset on config
.C (clock)
);
If you have trouble with state machine startup it's also a
good practice to have a post-reset state that does nothing
but drop into the idle state. This extra state acts like
a synchronous reset to the remainder of the FSM. This is
especially important with Xilinx tools which usually one-hot
encode your state logic (so starting up "all zero" doesn't
make any difference).
HTH,
Gabor
Article: 143932
On Nov 3, 12:28=A0pm, "melinda" <melinda.m...@gmail.com> wrote:
> Thanks Nigel,
>
> I was try that, but I'm still not able to see any changes of signals in
> instantiated modules(in wave form window).
>
> When I put some signals from instantiated verilog modules to wave form
> window, after I hit "run" simulation those signals remain X.
>
> Do you have any idea why is that so?
>
> Best Regards =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> This message was sent using the comp.arch.fpga web interface onhttp://www=
.FPGARelated.com
There are two things that happen in wave windows when you add signals,
first the signal is added to the wave viewer, but at the same time it
is added to the log. Normally in the wave view the signal will appear
as a total blank ("No Data") up to the point in the simulation where
you added it to the wave window. After that as you continue to run
the
sim it is filled in with the current state. If you want to be able
to add signals to the wave and see their full history, you should
add everything to the log when you start the simulation:
add log -r /*
Regards,
Gabor
Article: 143933On 3 Nov., 20:25, ed <ed.agu...@gmail.com> wrote: > Hi all, > > I'm having a problem where I'm not getting initialized how I expect > after startup on a Spartan-3E. > > For example, one of my state machines is not in its initial state > after startup, even though that state is coded all zeros. > > I don't have access to an external reset, so I have to generate one > internally somehow... > > Does anyone have any ideas? > > Thanks, > Ed Hi Ed, Xilinx FPGAs have a primitive element called STARTUP which provides you with a global Reset signal and other stuff. Check the library guide or the ISE template browser on how to instantiate it. Another (Xilinx XST specific) option is to assign default values to your FSM signals: e.g. signal mystate : state_type := INITIAL_STATE; This value is normally only used for simulation, but XST also puts it into the bitstream as an initial value for the FFs after power up. Also, If you use DCMs you can use the LOCKED signal for resetting purposes. Have a nice synthesis. EilertArticle: 143934
Hi Altera is promising 25% more fabric speed than S6 with their new Cyclone IV AnttiArticle: 143935
On Nov 3, 5:28=A0pm, "melinda" <melinda.m...@gmail.com> wrote: > Thanks Nigel, > > I was try that, but I'm still not able to see any changes of signals in > instantiated modules(in wave form window). > > When I put some signals from instantiated verilog modules to wave form > window, after I hit "run" simulation those signals remain X. > > Do you have any idea why is that so? > > Best Regards =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com If you can see the signals you want in the Objects window and can add them to the Wave window then you've sorted any optimization accessibility issues. The fact that you're seeing X on signals simply reflects the value Modelsim has calculated for them. You're into plain old circuit debug activity now ! As others have suggested, log all the signals in your design with log -r /* run the simulation and then back/forward trace signals to see where the X is introduced. The Dataflow window is very useful for this. - NigelArticle: 143936
Morten, Whatever solution you go with - my advice is this: * Get readable commented source code - or get a good option to buy it at a decent cost. It pays in the end. * When thinking about price, take your own cost into consideration. One engineering day in the Nordic region cost about EUR 5-600 all included (yes, more than just salary). So if you are trying to save say EUR 4000 (which incidentally is about 50% of the solution we have :-), you have about 7 days in total to do so. This needs to include everything. And that is just breaking even. If your company usually have you do something that is more valuable than the cost of having you hanging around :-) Which I hope they do :-) They would want you to generate more savings than the time you spend. So better budget at most about 3-4 days to save the EUR 4000 :-) // Rolf -- Axcon - The FPGA Power House www.axcon.dk | PCIe core: http://en.axcon.dk/pcie-core/ FPGA Training: www.axcon.dk/training | Also don't miss: Signal Integrity w/ Lee Ritchey: www.axcon.dk/lee (Dec 1-3/09)Article: 143937
>If you can see the signals you want in the Objects window and can add >them to the Wave window then you've sorted any optimization >accessibility issues. > >The fact that you're seeing X on signals simply reflects the value >Modelsim has calculated for them. >You're into plain old circuit debug activity now ! > >As others have suggested, log all the signals in your design with >log -r /* >run the simulation and then back/forward trace signals to see where >the X is introduced. >The Dataflow window is very useful for this. > >- Nigel > > Hi, When I said that I see X on signals... lets me explain you on example: Suppose we have counter.v and counter_tb.v in our design. (counter_tb.v instantiates counter.v) I add all signals from counter.v from objects window to wave window. Then also add all signals from counter_tb.v objects window to wave window. What I can see is all signal changes from counter_tb.v, including counter instance signals from counter_tb.v. With signals (in wave window) from counter.v nothing happening though counter_tb.v instantiate counter.v module ???? Do you know how to see that signals in instantianed modules in wave window. (i.e. if we have clock signal in tesbench(counter_tb.v) which maps to clock signal in counter.v I can see clock signal from testbench toogling but nothing happens with clock signal in counter.v (in wave window)) (PS: all mapping-signal orders etc... is just fine, just cant see what I describe above) Bets regards --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143938
"Antti" <antti.lukats@googlemail.com> wrote in message news:bb804275-4a39-41f6-ac65-a631278af1fd@m16g2000yqc.googlegroups.com... > Hi > Altera is promising 25% more fabric speed than S6 with their new > Cyclone IV > Antti Aye, but the first devices aren't available until next March. That's almost _6_ months away. :-( Nial.Article: 143939
On Nov 4, 10:38=A0am, "melinda" <melinda.m...@gmail.com> wrote: > >If you can see the signals you want in the Objects window and can add > >them to the Wave window then you've sorted any optimization > >accessibility issues. > > >The fact that you're seeing X on signals simply reflects the value > >Modelsim has calculated for them. > >You're into plain old circuit debug activity now ! > > >As others have suggested, log all the signals in your design with > >log -r /* > >run the simulation and then back/forward trace signals to see where > >the X is introduced. > >The Dataflow window is very useful for this. > > >- Nigel > > Hi, > > When I said that I see X on signals... lets me explain you on example: > Suppose we have counter.v and counter_tb.v in our design. (counter_tb.v > instantiates counter.v) =A0 > I add all signals from counter.v from objects window to wave window. > Then also add all signals from counter_tb.v objects window to wave window= . > What I can see is all signal changes from counter_tb.v, including counter > instance signals from counter_tb.v. > With signals (in wave window) from counter.v nothing happening though > counter_tb.v instantiate counter.v module ???? > > Do you know how to see that signals in instantianed modules in wave > window. > (i.e. if we have clock signal in tesbench(counter_tb.v) which maps to clo= ck > signal in counter.v > I can see clock signal from testbench toogling but nothing happens with > clock signal in counter.v (in wave window)) > > (PS: all mapping-signal orders etc... is just fine, just cant see what I > describe above) > > Bets regards =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com- Hide quoted text - > > - Show quoted text - It sounds like you are seeing the instantianed module signal values, it's just they aren't what you expect ! If you see a value for a signal in the Wave window then you are logging it correctly. Use the 'drivers' command to check correct connectivity eg drivers /counter_tb/i_cnt/clk will show where the clk signal in the instance i_cnt is driven from - hopefully from code in counter_tb Can you post any code we can look at? Otherwise contact your local Mentor support team who can look at this in more detail. - NigelArticle: 143940
hi,all
I am trying to target the XUP by Digilent with my big application. My
settings are almost there, but for some reason I get the following output:
..
Address Map for Processor microblaze
(0x0000000-0x5fffffff) DDR_256MB_64Mx64_rank2_row13_col10_cl2_5 sopb
(0x0000000-0x000ffff) dlmb_cntrl slmb
(0x0000000-0x000ffff) ilmb_cntrl slmb
(0x40600000-0x4060ffff) RS232_Uart_1 sopb
(0x41400000-0x4140ffff) debug module sopb
ERROR:Data2MEM:33 - Matching ADDRESS_SPACE for code segment #4 not found
in 'sys
tem_stub_bd.bmm'.
Code segment #4 occupies [0x50000000:0x5002B357]
thanks for your help..
---------------------------------------
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com
Article: 143941hi all, thanx for your reply... i finally figure out how to save the data in txt files..I used sjinn linux application and xil_print to my c program in microblaze.. however,i am not able to save all samples that adc outputs..my fsm make the onboard adc to give 1 sample every 700ns... Is microblaze fast enough to capture these data? Do i need some external ram to save first data and transfer them afterwards? thanx in advance, i really appreciate it.. --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143942
Hi,recently,I receive a task to add another new function to the project previously finished,but the problem is that the old project have consume about 5K of total 7K LUTs,and the new function need about 2.5K LUTs,so I must optimize the old logic but I have no idea,can someone give some advice about the logic optimization,the chip is spartan3,the synthesis tool is synplify9.4 pro,P&R tool is 10.1.Article: 143943
On Nov 4, 9:27=A0am, "bjzhan...@gmail.com" <bjzhan...@gmail.com> wrote: > Hi,recently,I receive a task to add another new function to the > project previously finished,but the problem is that the old project > have consume about 5K of total 7K LUTs,and the new function need about > 2.5K LUTs,so I must optimize the old logic but I have no idea,can > someone give some advice about the logic optimization,the chip is > spartan3,the synthesis tool is synplify9.4 pro,P&R tool is 10.1. You might want to look at the block RAM utilization and see if you can gain anything by using additional block RAM's (if available) to replace some of the logic.Article: 143944
On Nov 4, 6:27=A0am, "bjzhan...@gmail.com" <bjzhan...@gmail.com> wrote: > Hi,recently,I receive a task to add another new function to the > project previously finished,but the problem is that the old project > have consume about 5K of total 7K LUTs,and the new function need about > 2.5K LUTs,so I must optimize the old logic but I have no idea,can > someone give some advice about the logic optimization,the chip is > spartan3,the synthesis tool is synplify9.4 pro,P&R tool is 10.1. You need 7.5K, you have 7.0 - welcome to the real world. You will need to rewrite/remove some logic - Synplify, ISE, etc - these are not the tools that will do that. I suggest 'emacs' and 'modelsim' - that's what I would use. RKArticle: 143945
On Wed, 4 Nov 2009 07:43:32 -0800 (PST) d_s_klein <d_s_klein@yahoo.com> wrote: > You need 7.5K, you have 7.0 - welcome to the real world. You will probably also want to aim for less than 100% usage - timing constraints tends to get very hard to meet the higher the utilization is. I've seen any number of exponential graphs, all indicating that around 75-85% utilization it gets iffy. Of course, if the design doesn't need to be clocked particularly high, you'd be fine with higher utilization. //OscarArticle: 143946
All, I was puzzled that they used a push of the 65nm technology node (to 60nm). It is a huge investment for a FPGA device company to launch a new family, and to launch one with "the old" technology node means that the latest technology node is guaranteed to beat you on price, power, and/or performance (since 90nm, we do not get to choose all three, we are at best a two out of three for a new node). True, S6 is optimized for power (first time we have ever used a low power process from a foundry), so bragging about performance is one way to shout very loudly "we sure burn a lot more power!" When we asked customers what their number one need was for S6, it was "lower the power!" I know that many like to use the latest Spartan node to replace the previous Virtex node (lower their bill of materials costs), but frankly, S6 was designed for a new markets, and not intended to cannibalize Virtex 5 sockets. Anyway, it is always fun to watch how these things play out, AustinArticle: 143947
Petter Gustad <newsmailcomp6@gustad.com> wrote:
>nico@puntnl.niks (Nico Coesel) writes:
>
>> guzzling controller. Last year I evaluated a Freescale controller with
>> internal phy. It consumed about 1W and required a 4 layer board for
>> adequate heat sinking.
>
>Was that the M52235? I have a couple eval boards that does not seem to
>get hot at all. They can also run PoE.
I think so. Perhaps it will consume a lot of power if a long ethernet
cable is connected. The datasheet / application note recommends a 4
layer board for cooling.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 143948On Nov 3, 10:50=A0pm, backhus <goo...@twinmail.de> wrote: > On 3 Nov., 20:25, ed <ed.agu...@gmail.com> wrote: > > > Hi all, > > > I'm having a problem where I'm not getting initialized how I expect > > after startup on a Spartan-3E. > > > For example, one of my state machines is not in its initial state > > after startup, even though that state is coded all zeros. > > > I don't have access to an external reset, so I have to generate one > > internally somehow... > > > Does anyone have any ideas? > > > Thanks, > > Ed > > Hi Ed, > Xilinx FPGAs have a primitive element =A0called STARTUP which provides > you with a global Reset signal and other stuff. > Check the library guide or the ISE template browser on how to > instantiate it. > > Another (Xilinx XST specific) option is to assign default values to > your FSM signals: > e.g. > =A0signal mystate : state_type :=3D INITIAL_STATE; > > This value is normally only used for simulation, but XST also puts it > into the bitstream as an initial value for the FFs after power up. > > Also, If you use DCMs you can use the LOCKED signal for resetting > purposes. > > Have a nice synthesis. > =A0 Eilert I thought that if enumerated states are used, then most synthesis tools will use the left-most state as it's initial state. Isn't that correct? I'm not using XST. I'm using Synplify Pro and it is sequentially coding the initial state to all zeros, which is what I would expect the device to be in after configuration... but that's not the case. After configuration, the state is reading "110". I don't understand why this is happening. Thanks for the shift-register reset tip. I will try that.Article: 143949
Antti wrote: > Hi > > Altera is promising 25% more fabric speed than S6 with their new > Cyclone IV And us hobbyist types are wondering: will Altera give us a _free_ development environment for Linux this time? (just in case anyone from Altera drops in here occasionally). -- Torfinn Ingolfsen, Norway
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