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Jaap, You can't just probe in the middle of the trace and expect to see on your 'scope what the receiver sees. The 'scope will introduce an impedance discontinuity. What probe are you using? This is particularly the case with FPGAs; the Xilinx Virtex 4 has about 10pF of input capacitance per pin which is produced by all those other IOBs configuration options, specifically 24mA output FETs. High speed signals hit those 'caps' and reflect back. If you really want to probe the signals, you could add an attenuator to your design. So, is it working or not. You don't seem to describe your problem except the signal doesn't look good on your 'scope. HTH., Syms. p.s. Brian Davis posted on CAF about using attenuators for probing, you might be able to google for it.Article: 143501
On Oct 13, 5:19=A0am, "gkonstan" <paraharak...@gmail.com> wrote: > >The last device to have a "inrush" current was the Virtex E, > > >Since then, the parts have no "excess" current requirements. =A0Now, the > >poster may have a design which is using more power than he is able to > >supply with his power supply design, so by forcing the part to NOT > >configure (change mode pins, =A0ground the DIN pin, etc.) they will be > >able to see if the power supplies can power the part when there is no > >bitstream. > > >While the part waits for a bitstream, the power is virtually identical > >to what the power is while loading the bitstream, and what the power > >is immediately after the bitstream is loaded, before the part starts > >doing whatever it is that the customer has told it to do. > > Actually I had followed the standard procedure, and the code I inserted w= as > identical to the one that already worked, with the addition of one led > which was supposed to stay always on (and it did, though in lower scale > than supposed). > Thank you all very much for your help, in the end when I started going > 'hardware', unplugging stuff and so, I noticed that the input current of > the board was close to 1,5A, (rather big, isnt it?)so I just told my > supervisor and we are checking if it is possible to find a new Fpga. > Thank you again for your time and trouble. =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www= .FPGARelated.com Did you try the Mode pin idea? i.e. if the FPGA draws too much power when it isn't configured, it's broken. If not it could be your design. Changing a small thing like turning on an LED seems like it shouldn't cause your problem, but there are cases that can cause severe overcurrent. One I run into all the time is that ISE suddenly decides not to use my .ucf file and blithely re-locates all my pins. You can see for yourself what that would do if your outputs are randomly attached to other board signal sources. Did you look through the report files? The Place & route report shows the percentage of LOC'd IOBs right near the top. Regards, GaborArticle: 143502
>Jaap, > >The waveforms will look different at any point OTHER than across the >termination. > >You can see this for yourself in the simulation, by placing the >package element in the simulation (i.e. two short -- 10-20mm t-lines >before the termination and IO pin loading model). > >If you have already done this, then you are aware of where you look >influences what you see. > >Looking directly across the termination is what the receiver sees, so >that is what matters. OK, clear from a simulation point of view. We are measuring as close as possible to the receiver e.g. the termination, but this is not always possible, due to the location of via's (micro-strip to stripline and v.v.), which may not always be as close to the termination as you would like them to be. Anyhow, what we see is not a "normal" reflection, but a RC-curve on top of the reflection. This RC-curve is "killing", the reflection itself is more or less as expected. If we manually place a 100 ohm resistor on the board, and disable the on-die termination, the RC-curve has disappeared, and the signal looks as neat as you can possibly expect. In this case, the reflection is there but very OK, and the eye-diagram is well open. The problem is that we need about 40 of these extra 100 ohm resistors, on a board which is already loaded.... > >The termination is not a carbon resistor, but it is as good as one >when it comes to looking like a resistor, so that is not the issue. >Often, the attribute is not set properly, and the resistor is not >enabled. Have you checked in FPGA_editor, and do you clearly see the >resistor termination enabled? Yes, we did this check, the attribute was set both in the VHDL as in the UCF, and we checked the results using the FPGA Editor, and the pinning file. >Does the receive voltage appear twice >as high as it is indicated in the simulation? (clearly indicating the >resistor is not enabled) > >You do not mention the problem: bad data, occasional incorrect data, >bad data when other IOs switch only, etc. Basically all of the items mentioned above. Bad data could be the result of many issues (internal FPGA I/O timing, SSN, clock jitter requirements, etc.). We are trying to eliminate them one by one, to narrow down on the real cause(s). > >As a customer, the magic words are "lines down." If you say this, the >case MUST be escalated. If unresolved, it must be escalated again and >again, until it gets to the "Fire Marshall" who reports to the Senior >VP and CEO on unresolved cases, and their status. > >Since I invented, implemented, this system, and was the first Fire >Marshall, I am very familiar with the system, and it works really well >-- use it! > >A case number is very useful: if you email it to me, I can check on >its status, and help get it escalated. OK, thanks. As I said, Xilinx is already involved, a RMA procedure was started but temporary halted on our request because we needed more time to do our homework. Until now, we haven't been able to find anything that we have done wrong ourselves. Today, I have been working with some collegues to connect a DSP evaluation board (ADI EZ-Lite TS201) with LVDS-based DSP Link Ports direcly to a FPGA evaluation board (Xilinx ML403), e.g. without any hardware being designed by ourselves (only interconnect consisting of two RJ45/UTP cables). The FPGA only will contain a loopback (TX to RX and v.v.), elimination any possible internal timing issues. If we encounter the same RC-curves on this design, we can stop our attempts to find the error in our own designs (PCB/board/FPGA), and redesign/relayout all our boards, which will be extremly costly and also time consuming. We have already started these redesigns (in parralel), to reduce leadtime and risk. We are finishing a report on our measurements, simulations, etc this week, and we will forward it to our Xilinx representatives. > > --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143503
>Jaap, > >You can't just probe in the middle of the trace and expect to see on >your 'scope what the receiver sees. The 'scope will introduce an >impedance discontinuity. What probe are you using? We are aware of that. It is impossible to probe at the ideal location, due to the layout, vias positions, etc. We are using a LeCroy SDA 6000A with a D600A differential probe. I believe these devices suitable (if not over-qualified) for these measurements.... ;-) > >This is particularly the case with FPGAs; the Xilinx Virtex 4 has about >10pF of input capacitance per pin which is produced by all those other >IOBs configuration options, specifically 24mA output FETs. High speed >signals hit those 'caps' and reflect back. Is this 10 pF input capacitance per pin based on having on-die termination enabled, disabled or perhaps both? > >If you really want to probe the signals, you could add an attenuator to >your design. So, is it working or not. You don't seem to describe your >problem except the signal doesn't look good on your 'scope. The problem is bad/corrupted data (occasionally), for more details see my follow-up to the Austin in this same thread. > >HTH., Syms. > >p.s. Brian Davis posted on CAF about using attenuators for probing, you >might be able to google for it. OK, thanks, we will do that. > > > --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143504
Test01, The initial mapping to an FPGA prototyping board is indeed a big undertaking. However, if you use the dedicated tools described in the previous post, then updating the prototype when the HDL changes will be push-button in the vast majority of cases. Changes that would require some assistance are of the kind that invalidate the partition: - changes to the interface between two modules that are in different devices. This would require to incrementally update the partition and pin assignment (Certify supports this, not sure about Auspy) - significant increase in resources leading to an overflow of one or more devices. This would require an incremental update to the partition to reassign logic in devices with some free room - etc Emulation systems are in fact using commercial FPGAs. Thus, the conversion effort is virtually identical. However, the partitioning and board management tasks are fully automated and hidden from the user. The choice between emulation and prototyping should primary be based on your objectives: - to perform early-stage functional debug, emulation is the better choice. To some extent, emulation is HDL simulation on steroids. - to validate the chip in a (near) real-life environment, find the late-stage functional bugs, develop and validate the embedded software, pass certification, etc, prototyping is the better choice. In fact, power users combine emulation and prototyping to validate their SoCs. Cheers, - gael PS: a few additional notes on latches: (1) wether using emulation of prototyping, there is no need to convert latches to flip-flops as latches are supported in most FPGAs. However, you cannot fully rely on timing analysis since it does not support time-borrowing. This introduces the possibility of timing violations on your emulator/prototype that would appear as functional bugs. If you run the emulator/prototype at very low frequencies (e.g. < 1Mhz, like emulators do), then this most likely not a problem. Otherwise, a good option for power users would be to run PrimeTime (or any ASIC STA that supports time-borrowing) on the protoype netlist annotated with delays (SDF). (2) wether using emulation or prototyping, you can opt for fully automatic conversion of latches to flip-flops (Precision and Synplify/ Certify have this feature). While this resolves the above timing analysis problem, it may create a design that is not functionally equivalent. However, in my experience, if latches are used properly, FF conversion will always be functionally equivalent. In other words, if your ASIC design team is experienced and knows its trade, latches should not be an issue and converting them to FFs is best option.Article: 143505
On Oct 13, 4:11=A0pm, Gael Paul <gael.p...@gmail.com> wrote: > (1) wether using emulation of prototyping, there is no need to convert > latches to flip-flops as latches are supported in most FPGAs. However, > you cannot fully rely on timing analysis since it does not support > time-borrowing. This introduces the possibility of timing violations > on your emulator/prototype that would appear as functional bugs. If > you run the emulator/prototype at very low frequencies (e.g. < 1Mhz, > like emulators do), then this most likely not a problem. The timing issue with latches is hold time, not setup time. Hold time violations are independent of clock speed so if you have this problem you'll have it whether you run the design at 1 Hz, or 500 MHz. You'll likely find what turns out to be hold time problems started as something that appears as a sensitivity to temperature, so cold spray and heat guns can make the problem come and go. You can get lucky with timing...or not. Kevin JenningsArticle: 143506
On Oct 13, 5:15=A0am, "CARLA" <bk_a...@hotmail.com> wrote: > HI, > > why we can estimate the energy consumption whith a virtex5 and not with a > virtex3 or 2 for example? what is this special characteristic? > > thank you Your post does not provided enough information for a response. Please elaborate on what your question is about. Also, there is no Virtex-3 FPGA family. Ed McGettigan -- Xilinx Inc.Article: 143507
On Tue, 13 Oct 2009 14:10:34 -0500, "dc207" <jaap.mol@planet.nl> wrote: >Anyhow, what we see is not a "normal" reflection, but a RC-curve on top of >the reflection. This RC-curve is "killing", the reflection itself is more >or less as expected. If we manually place a 100 ohm resistor on the board, >and disable the on-die termination, the RC-curve has disappeared, and the >signal looks as neat as you can possibly expect. ... but do the data errors disappear? I may have a suspicious mind but it looks possible that the visible reflections are a red herring, and the internal termination works just fine ... but something else is causing data corruption. The best time to discover that is _not_ when you get the revised board layout back... - BrianArticle: 143508
On Tue, 13 Oct 2009 07:16:06 -0500, "subagha" <subagha@gmail.com> wrote: >Hi, > I have a small design in VHDL with black box which i am trying to >synthesize >using Xilinx ISE 11.2. > >I get an error when running the command ngdbuild. >ERROR:NgdBuild:604 - logical block 'inst' with type 'my_block' could not >be > resolved. A pin name misspelling can cause this, >>> a missing edif or ngc file, >The design has two files > >my_block.vhd --- >black_box_1.vhd --- >I am using the commandline to run my commands and not the GUI. Have you run synthesis, with the correct settings, on my_block.vhd? You need to synthesise this WITHOUT inserting I/O buffers on its ports, to generate my_block.ngc. If you can't find the correct commandline options, use the GUI to synth without IOB insertion, and copy the command line from the .commandlog file into your scripts. >command which generated error: >ngdbuild -intstyle xflow -sd . -dd _ngo -nt timestamp -p xc5vtx240t-2ff1759 >black_box_1.ngc black_box_1.ngd And as the error message says, it can't find my_block.ngc. If my_block.ngc existed, ngdbuild would use it to fill in the black box. (This is how an EDK project is incorporated into to an ISE flow) If my_block.ngc exists but ngdbuild can't find it, it may be in the wrong directory. You can keep all your black box .ngc files in a separate folder and use a command line option to tell ngdbuild to look there for them. - BrianArticle: 143509
dc207 wrote: >> Jaap, >> >> You can't just probe in the middle of the trace and expect to see on >> your 'scope what the receiver sees. The 'scope will introduce an >> impedance discontinuity. What probe are you using? > > We are aware of that. It is impossible to probe at the ideal location, due > to the layout, vias positions, etc. > We are using a LeCroy SDA 6000A with a D600A differential probe. I believe > these devices suitable (if not over-qualified) for these measurements.... > ;-) > >> This is particularly the case with FPGAs; the Xilinx Virtex 4 has about >> 10pF of input capacitance per pin which is produced by all those other >> IOBs configuration options, specifically 24mA output FETs. High speed >> signals hit those 'caps' and reflect back. > > Is this 10 pF input capacitance per pin based on having on-die termination > enabled, disabled or perhaps both? > >> If you really want to probe the signals, you could add an attenuator to >> your design. So, is it working or not. You don't seem to describe your >> problem except the signal doesn't look good on your 'scope. > > The problem is bad/corrupted data (occasionally), for more details see my > follow-up to the Austin in this same thread. > >> HTH., Syms. >> >> p.s. Brian Davis posted on CAF about using attenuators for probing, you >> might be able to google for it. > > OK, thanks, we will do that. >> >> > > --------------------------------------- > This message was sent using the comp.arch.fpga web interface on > http://www.FPGARelated.com Hi Jaap, OK, it sounds like you are more than a little experienced at this, apologies for teaching you to suck eggs with your probing! Also, apologies in advance if the following is all obvious! So, each pin has 10pF loading on it no matter what the IOB is set up for. Every single mode. There are a bunch of FET's connected to the signal to drive signals out if required by the configuration loaded into the device. Even if these are turned off, for example when the pin is an input, the capacitance is still there. It is the capacitance of the FETs' structure. Look at a datasheet for a discrete FET to see why this is. This should be modelled in the IBIS file. You could try simulating with the IBIS model replaced by a 10pF cap to ground, along with the 100 ohm resistive termination between pins. If this sim looks the 'scope picture, maybe the IBIS model isn't accurate, but I doubt this. FWIW, I've used the on chip termination for Virtex 4 FX devices many, many times without problems, within these limits:- < 667MBps data rate < 6 inches trace length. How good are your power supplies? Are your pairs tightly coupled? Are they routed away from any crosstalk hazards? Are the pairs routed on a layer next to a ground plane? Do they swap layers a lot? HTH, Symon.Article: 143510
Hello, Environment: Virtex II Pro/ Xilinx 9.1i I'm trying to use PLB Master to write on the DDR Ram. I made a C program to make the video frame buffer to read from DDR Ram 0x00000000. Now, I need to make an IP to write on DDR Ram to output something on the video output. I made PLB Master IP to communicate with DDR Ram. In user_logic.v, I'm just assigning IP2Bus_Addr to 0x0 and incrementing it by 64 bits. Whenever the MstWrAck is high, I'm sending some random data like 64'h0000_00ff_0000_00ff. However, it doesn't seem to get an access to the ram. Can anyone give me any simple example that writes some data from PLB Master to DDR Ram? Thank you!!Article: 143511
On Oct 13, 7:08=A0pm, Symon <symon_bre...@hotmail.com> wrote: > jay wrote: > > Hello all, > > > I have an ASIC design to be converted to FPGA, I'm using Spartan-3A. > > > The ASIC uses 60MHz input clock, and divides it to 3 20MHz clocks > > inside, the duty cycle is not 1:1 and has phase shifting like below: > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|<- =A050ns ->| > > =A0 =A0 =A0___ =A0 =A0 =A0 =A0 =A0 ___ =A0 =A0 =A0 =A0 =A0 ___ > > =A0__/ =A0 \___.___/ =A0 \___.___/ =A0 \___.___. > > =A0 =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . > > =A0 =A0 =A0 =A0 =A0 =A0 =A0_ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0_ =A0 =A0 = =A0 =A0 =A0 =A0 =A0 _ > > =A0 _.___._/ \___.___._/ \___.___._/ \___. > > =A0 =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0_ =A0 =A0 =A0 =A0 =A0 =A0 =A0 _ =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0_ > > =A0 _.___.___/ \_.___.___/ \_.___.___/ \_. > > =A0 =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . > > > These 3 clocks are the main clocks in the design, so I want to get > > them from DCM, but found I can't set duty cycles in DCM. > > > Now I use logic to divide the clocks and add BUFG after them, but the > > skew before BUFG can't be managed. > > > Is there anyone has a better idea? > > Hi Jay, > Clock everything at 60 MHz. Use the 60MHz to make three clock enables > for your three phase shifted domains. > HTH., Syms. Hi Symon, This sounds a good idea, but it needs change the whole ASIC design. And two clocks' high period is only half of the 60MHz cycle, I need run my design in 120MHz to catch it. Best Regards, JayArticle: 143512
Jaap, Not much time to type tonight, but here's something: ----------------- A. "RC curves" on LVDS signals > > In the time-domain, we are measuring (with Lecroy SDA) > RC-like curves on the (data)signals, when they have been > stable (either 0 or 1) for a while and when they start > switching again (to 1 or 0 respectively). > This sounds _exactly_ like what you would see if the on board FPGA terminator was not enabled. Many of these high speed A/D parts have LVDS outputs without any internal back termination, so the A/D driver current sources will run off into the rails and saturate on a long string of 1's or 0's without an external termination of some sort- this sounds just like what you are seeing. I would concentrate on verifying, in hardware, that the terminations are REALLY enabled, see section C. IIRC the ADS527x does not have the switchable internal back terminations like other TI A/D parts, but it does have the double-strength LVDS drive setting. If you respin the board, I would highly recommend enabling that control bit and implementing either the back termination at the A/D or a differential attenuator (see links) to provide better matching when driving a V4 FPGA; this will also make it easier to make meaningful measurements with an external probe. ----------------- B. DIFF_TERM attribute problems > > the attribute was set both in the VHDL as in the UCF, and we >checked the results using the FPGA Editor, and the pinning file. > What version of software are you using? What part are you targeting? A bug later on in the flow ( e.g. Bitgen ) could have this effect on the hardware yet still show the terminations in the FPGA editor. Do both sides of the differential buffer ( DIFFM/DIFFS ) show the termination attribute enabled in the FPGA editor? There have been a number of past bugs with the DIFF_TERM's getting dropped somewhere in the flow unless they are done with exactly the right incantation. This is particularly true for the DIFF_OUT variants of the LVDS input buffers, which IIRC are used in some of the high speed serializer app notes to provide two copies of the internal data for better routing delays. Despite a 6-7 year old CR reporting this problem, the last time I checked the bug was still there if the DIFF_TERM attributes were applied directly to a DIFF_OUT buffer in the HDL source code. ----------------- C. DIFF_TERM implementation > > In reality, both terminals have a Thevenin-equivalent circuit, > each consisting of two other "resistors", one from the terminal > up to the I/O supply voltage, and another downto ground. > Note, the _original_ V2 LCDS_25_DCI termination hack worked like this, but the DIFF_TERM's are implemented differently, and look more like ~100 ohm across the pair for signals within the specified common mode input voltage range. I have some half-finished LVDS notes that show a quasi-differential sweep of a V4 DIFF_TERM done with a single-ended curve tracer and a couple resistors, I'll try to post them in a few days; see the link "DIFF_TERM measurements" link below for a written description. You can do something similar with a voltage source and a couple resistors to confirm the presence of the internal termination in the hardware. ----------------- D. IBIS modeling of Xilinx differential terminations > >Note: the on-die termination resistor (100 ohm) was not included in the >IBIS model of the Xilinx LVDS receiver, and needed to be added manually. > If you are using an old version of HyperLynx, you may need a fresher copy. The Xilinx IBIS terminator models have been broken in HyperLynx on both occasions that I've looked into it ( see link below); simulating the termination as an external resistor will not be an exact model, but it is probably close enough to spot many problems. ----------------- Past LVDS Posts and Links ( also see surrounding threads ): Note that my file links referenced in the following posts have moved, as AOL silently axed their FTP site last fall : http://fpgastuff.googlepages.com/oldaolfiles http://fpgastuff.googlepages.com/lvds_current.pdf http://fpgastuff.googlepages.com/lvds_current.zip ADS527x and Xilinx LVDS inputs: http://groups.google.com/group/comp.arch.fpga/msg/95809af82ccbb550 http://groups.google.com/group/comp.arch.fpga/msg/ab999f47d42e50f8 http://groups.google.com/group/comp.arch.fpga/msg/5a8720eec942612e http://groups.google.com/group/comp.arch.fpga/msg/8ad1d05fa4d14e77 DIFF_TERM lab measurements http://groups.google.com/group/comp.arch.fpga/msg/dd70f9f0bea2cbe0 S3E DIFF_TERM tool quirks: http://groups.google.com/group/comp.arch.fpga/msg/45050b8239cecc56 Xilinx/Hyperlnyx differential termination bugs: http://groups.google.com/group/comp.arch.fpga/msg/aa97cb00c9aa721a http://groups.google.com/group/comp.arch.fpga/msg/c6e28cb7cc0ce3d0 good luck, BrianArticle: 143513
On Oct 13, 6:47=A0pm, jay <heavenf...@gmail.com> wrote: > On Oct 13, 7:08=A0pm, Symon <symon_bre...@hotmail.com> wrote: > > > > > > > jay wrote: > > > Hello all, > > > > I have an ASIC design to be converted to FPGA, I'm using Spartan-3A. > > > > The ASIC uses 60MHz input clock, and divides it to 3 20MHz clocks > > > inside, the duty cycle is not 1:1 and has phase shifting like below: > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|<- =A050ns ->| > > > =A0 =A0 =A0___ =A0 =A0 =A0 =A0 =A0 ___ =A0 =A0 =A0 =A0 =A0 ___ > > > =A0__/ =A0 \___.___/ =A0 \___.___/ =A0 \___.___. > > > =A0 =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0_ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0_ =A0 =A0= =A0 =A0 =A0 =A0 =A0 _ > > > =A0 _.___._/ \___.___._/ \___.___._/ \___. > > > =A0 =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0_ =A0 =A0 =A0 =A0 =A0 =A0 =A0 _ = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0_ > > > =A0 _.___.___/ \_.___.___/ \_.___.___/ \_. > > > =A0 =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . > > > > These 3 clocks are the main clocks in the design, so I want to get > > > them from DCM, but found I can't set duty cycles in DCM. > > > > Now I use logic to divide the clocks and add BUFG after them, but the > > > skew before BUFG can't be managed. > > > > Is there anyone has a better idea? > > > Hi Jay, > > Clock everything at 60 MHz. Use the 60MHz to make three clock enables > > for your three phase shifted domains. > > HTH., Syms. > > Hi Symon, > > This sounds a good idea, but it needs change the whole ASIC design. > And two clocks' high period is only half of the 60MHz cycle, I need > run my design in 120MHz to catch it. > > Best Regards, > Jay Jay, find out what the clocks are doing. If they clock only flip- flops, then only the rising edges are important, and the high-time is irrelevant, and Symon's advice is perfect. If, however, the "clocks" are also used for other purposes (e.g. with latches), then you have to be more careful with High and Low timing, and any clock overlap. Peter AlfkeArticle: 143514
On Oct 14, 11:17=A0am, Peter Alfke <al...@sbcglobal.net> wrote: > On Oct 13, 6:47=A0pm, jay <heavenf...@gmail.com> wrote: > > > > > On Oct 13, 7:08=A0pm, Symon <symon_bre...@hotmail.com> wrote: > > > > jay wrote: > > > > Hello all, > > > > > I have an ASIC design to be converted to FPGA, I'm using Spartan-3A= . > > > > > The ASIC uses 60MHz input clock, and divides it to 3 20MHz clocks > > > > inside, the duty cycle is not 1:1 and has phase shifting like below= : > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|<- =A050ns ->| > > > > =A0 =A0 =A0___ =A0 =A0 =A0 =A0 =A0 ___ =A0 =A0 =A0 =A0 =A0 ___ > > > > =A0__/ =A0 \___.___/ =A0 \___.___/ =A0 \___.___. > > > > =A0 =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0_ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0_ =A0 = =A0 =A0 =A0 =A0 =A0 =A0 _ > > > > =A0 _.___._/ \___.___._/ \___.___._/ \___. > > > > =A0 =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . > > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0_ =A0 =A0 =A0 =A0 =A0 =A0 =A0 _ = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0_ > > > > =A0 _.___.___/ \_.___.___/ \_.___.___/ \_. > > > > =A0 =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . =A0 . > > > > > These 3 clocks are the main clocks in the design, so I want to get > > > > them from DCM, but found I can't set duty cycles in DCM. > > > > > Now I use logic to divide the clocks and add BUFG after them, but t= he > > > > skew before BUFG can't be managed. > > > > > Is there anyone has a better idea? > > > > Hi Jay, > > > Clock everything at 60 MHz. Use the 60MHz to make three clock enables > > > for your three phase shifted domains. > > > HTH., Syms. > > > Hi Symon, > > > This sounds a good idea, but it needs change the whole ASIC design. > > And two clocks' high period is only half of the 60MHz cycle, I need > > run my design in 120MHz to catch it. > > > Best Regards, > > Jay > > Jay, find out what the clocks are doing. If they clock only flip- > flops, then only the rising edges are important, and the high-time is > irrelevant, and Symon's advice is perfect. > If, however, the "clocks" are also used for other purposes (e.g. with > latches), then you have to be more careful with High and Low timing, > and any clock overlap. > Peter Alfke Peter, The design mostly used latches, I'm unlucky. All three clocks are registered by main clock however, I think if I can constraint the FF output to BUFG input delay of them (be the same), the phase relationship can be kept. Can I do that? Best Regards, JayArticle: 143515
jay wrote: > > Peter, > > The design mostly used latches, I'm unlucky. > Ouch! > > All three clocks are registered by main clock however, I think if I > can constraint the FF output to BUFG input delay of them (be the > same), the phase relationship can be kept. Can I do that? > > Best Regards, > Jay I can think of two choices, both of which use a DCM to make 120MHz from your 60MHz. 1) Rewrite it all to use FFs only (i.e. no latches) clocked at 120MHz. 2) Use the 120MHz to make the three clock signals the original design used. Constrain these with MAXDELAY to three BUFGs to distribute the clocks. Do (1) if you're ever gonna add any new features to the design. Do (2) if you're planning on getting a job somewhere else soon! ;-) Good luck, Syms.Article: 143516
Hi AM working on Virtex 4 sx35 ML402 board. I have got DDc code form the xilinix which they have developed for V5 and V4 SX25 so using sysgen can we generate HDL n etlist for V4SX35 and can we do Hardware co simulation for the same If any body knows please let me know need it very urgentlyArticle: 143517
Hi, The datasheet isn't very clear to me, maybe you can help me out? I want to to reduce the power consumption of a pipeline during idle cycles. The pipeline is implemented with flip flops on a S3A device. I have two mechanisms available, and don't know which is better. Mechanism #1: Stop toggling input data, so output data will not toggle either. Mechanism #2: Use the clock-enable pin. The former is inherent to my design and I get it for free. So my question is whether the second method gives me any *additional* power reduction, or just increases the routing contention? I know that I can also use a BUFGMUX to reduce the power consumption of the clock distribution itself, but this is not possible in the problem case. I'm already using that in a "deeper" power save mode. Best regards, MarcArticle: 143518
> Please advise me in any sense. If you've any sense you'll pick a more realistic final year project! Sorry to be blunt but from the questions you're asking there's no way you'll get this finished. NialArticle: 143519
Jaap, An RMA is NOT the right way to go. Often people request an RMA when it is a technical problem, not an issue of wanting to return a part for failure analysis. GET OUT OF THE RMA queue, and get into the "solve the problem" queue by entering a webcase. We can't help you if you ask us to do the wrong things. RMA process is to find a supposed fault on a part. Given that faults on V5 parts are running less than 1 ppm right now, unless this is just one part with this problem, and you are sure that it is bad, do not request an RMA. Different people, different skills: they can not find the problem on your board, nor do they even know how to. Email me at austin@xilinx.com with the details (company, names, any case numbers) and I will help get this properly assigned. If you are in the RMA queue, I doubt that you will get any resolution until they reassign this to the right people. You never answered if the voltage swing is the same with the resistor, and also with the LVDS termination. You also never answered if you did the simulation of the resistor at the receiver, or 19-20mm away from the receiver (always observing 10-20mm away from the receiver). It could be you are just chasing this small reflection, that isn't the problem at all!Article: 143520
"Marc Jet" <jetmarc@hotmail.com> wrote in message news:d52f14d7-36c5-4979-a76f-b54ac82eb3f8@x37g2000yqj.googlegroups.com... > Hi, > > The datasheet isn't very clear to me, maybe you can help me out? > > I want to to reduce the power consumption of a pipeline during idle > cycles. The pipeline is implemented with flip flops on a S3A device. > I have two mechanisms available, and don't know which is better. > > Mechanism #1: Stop toggling input data, so output data will not > toggle either. > > Mechanism #2: Use the clock-enable pin. > > The former is inherent to my design and I get it for free. So my > question is whether the second method gives me any *additional* power > reduction, or just increases the routing contention? > > I know that I can also use a BUFGMUX to reduce the power consumption > of the clock distribution itself, but this is not possible in the > problem case. I'm already using that in a "deeper" power save mode. > > Best regards, > Marc All the clock enable pin does is switch the FF D input between the FF Q output or the data input, so either method has the same effect.Article: 143521
Hi, I am interested in reading the post on "ASIC Prototyping using FPGA" in which it mentioned that in ASIC, flip-flops are used to be replaced with latchs. I cound't understand it. For example, a state machine. If FFs are used, after the next clock pulse, FFs change status. If latches are used, I don't know how the latches can be kept unchanged while code outside the state machine is using the state information. anyone would like to expain it more in details? Thank you. WengArticle: 143522
Weng Tianxiang <wtxwtx@gmail.com> wrote: < I am interested in reading the post on "ASIC Prototyping using FPGA" < in which it mentioned that in ASIC, flip-flops are used to be replaced < with latchs. < I cound't understand it. < For example, a state machine. If FFs are used, after the next clock < pulse, FFs change status. If latches are used, I don't know how the < latches can be kept unchanged while code outside the state machine is < using the state information. < anyone would like to expain it more in details? I agree. As far as I know, ASIC libraries use the same type of edge triggered FF's as FPGAs. Well, in the old days people used to do strange things, like dynamic logic. The 8080 and 8086 have minimum clock rates, as the registers will lose their contents if you clock too slow. When the Z80 came out with static logic people were much happier. (You can slow the clock down and watch instructions execute one at a time.) Also, with a two phase clock you can use simpler latches, but as far as I know, that isn't the way current logic works. -- glenArticle: 143523
On Oct 12, 9:01=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > On Oct 12, 4:15=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > On Oct 12, 2:14=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > On Oct 12, 11:08=A0am, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > On Oct 12, 9:07=A0am, rickman <gnu...@gmail.com> wrote: > > > > > > On Oct 11, 8:34=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > > > Hi, > > > > > > Please help. > > > > > > > I want to enclose the following equation data n/2**j with a low= er > > > > > > boundary character pair within Microsoft Office Word 2007. > > > > > > > 0 <=3D i <=3D low_boundary(n/2**j) ; > > > > > > > Thank you. > > > > > > > Weng > > > > > > Have you checked the insert symbol table? =A0If what you need is = not > > > > > there, try inserting a Microsoft Equation object. =A0Insert, Obje= ct, > > > > > Create New, Microsoft Equations 3.0 is the process in Word 2003. > > > > > > Rick > > > > > Hi Rick, > > > > Thank you. I will try your method. The character pair is not within > > > > the insert symbol table. > > > > > Weng- Hide quoted text - > > > > > - Show quoted text - > > > > Hi Rick, > > > Sorry. Your method fails. The reason is when to insert a object, it > > > needs you entering the characters which I don't know. If I know it, I > > > don't have to use the Microsoft Equation. > > > > I think the pair is in some font which I need to know. > > > > Weng > > > I am not familiar with the term "low boundry". =A0Can you explain what > > you mean by this? =A0What does the symbol look like? > > > When I use the Equation editor, I don't need to know *any* > > characters. =A0It gives a toolbar that has various groups of known math > > symbols such as a greek epsilon for summation or a pi for products. > > It also has symbols for set theory which is where I find the term > > "greatest lower bound" used. =A0That symbol is what I was taught was > > called "cap" and looks like an upside down U. =A0Is that the symbol you > > are looking for? > > > Rick- Hide quoted text - > > > - Show quoted text - > > Hi Rick, > The integer lower boundary function: L(1.2) =3D 1, L(2.5) =3D 2, L(3.999) > =3D 3. > > The function drops all data after the decimal point. > > The character is a 'L' in left side and a mirror image of 'L' along Y > aixis is in the right side. > > Thank you. > > Weng Yes, I was able to create a document with that symbol using the equation editor in Word 2003. I believe Open Office has a similar feature, but I have not used it so far. I've sent you an email with a PDF of the word doc... I guess I should have sent he word doc. I'll do that. RickArticle: 143524
On Oct 13, 1:06=A0am, GrIsH <grishkun...@gmail.com> wrote: > > =A0 =A0I tried lots of data types and the conversion function but didn't > get the result what i want...... > So iam going to put my problem straight forward to you.......your any > idea will be gr8ly appreciated.... > > Problem: > 1. i need to count the pulses from quadrature encoder , value of count > can be +ve as well as -ve depending upon direction of rotation of > encoder... > 2.This value is to be send to uBlaze.... > 3.I have a code for counting the encoder pulses that is included in > the "user_logic".... > 4.I have used "user software register" method of transferring data > from my custom IP to uBlaze.. > 5.In phase of transferring the value of count from IP to uBlaze, the > value of count must be mapped to IP2Bus_Data in SLV format data > type.... > 6.Here i had defined "count " that counts value of pulses as integer > and it should be converted SLV while transferring... > 7.But this method didn't work as i expected while receiving data in > uBlaze..... > So...Plz suggest me in.... > > what should be the data type of "count" that support +ve as well -ve > numbers and supports operation count<=3Dcount+1/-1 > ?? > and how -ve values of count are represented in SLV format?? I don't know that your problem is one of converting data types. You clearly are placing the 16 bit data in an odd location on a 32 bit bus and you have not told me that you are certain that this is correct. I have not worked with the uBlaze, so I'm not familiar with its data bus numbering. Is it 0 to N or N downto 0? Have you simulated your design? Before putting a design into the chip, you should always simulate it first to get your logic right. Then you can load it into the chip and see if it works with the real hardware. If you don't answer my questions and follow my advice, I can't help you. To answer your last question, the SLV signal type does not know anything about numbers. It is just an array, or a bus, of std_logic signals. There is no intended interpretation of this bus as a number. That is why the signed and unsigned types were developed. They have an explicit representation of signed and unsigned numbers respectively. When you talk about "converting" a signed value to an SLV, there really is no conversion. It is more like just connecting the wires. So the SLV ends up receiving the exact same set of 1s and 0s that were in the signed signal, according to the way that they connected. I have never worked with SLV in the 0 to N direction. To be honest, I don't remember the details of how assignments are made between buses using different directions of indexes. I wouldn't expect any surprises, but then I have no experience with them. Is there a reason that you are using 0 to N numbering instead of N downto 0 on your SLV arrays? This may not be a problem, but if you are stuck, why use this uncommon convention? But before changing anything you need to simulate your design. That means you will need a testbench which can be automatically generated by many VHDL tools. Then edit the resulting testbench file to add stimulus to your inputs and you will be able to observe any signal in the design in the waveform window. That will let you see each and every change of data in the path from the counter to the uBlaze CPU. Rick
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