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Messages from 14400

Article: 14400
Subject: Re: Power Consumption in FPGAs
From: "Bruce Nepple" <brucen@imagenation.extra.com>
Date: Thu, 28 Jan 1999 14:12:49 -0800
Links: << >>  << T >>  << A >>
Static power, and dynamic power......

I've been burned by Altera parts consuming static power in the IO interface
when there was 5V/3.3V conversion (few years ago).  ....Just a reminder to
be sure to duplicate your IO configurations exactly in your tests.

bruce

Panci Gianpiero wrote in message <78hq1n$a9$1@news.flashnet.it>...
>
>Andres Garcia ha scritto nel messaggio <36A75AD2.FBB0B66@enst.fr>...
>>
>>If anyone knows something about power consumption in FPGAs
>>or if you want to discuss about it, please, send me an e-mail.
>>
>>Thank you.
>>
>>
>I am really interested on FLEX10K power consuption, I am going to realize a
>test bench to measure it!
>someone can give me information ?  Thanks
>
>Panci Gianpiero
>dep.elsys@microelettra.it
>
>
>
>
>


Article: 14401
Subject: Off topic DRAM/SIMM question....
From: "Austin Franklin" <aus3tin@darkroom.com>
Date: 28 Jan 1999 23:13:19 GMT
Links: << >>  << T >>  << A >>
I'm stumped, but since there are so many smart people in this NG, I thought
I'd toss this one out here and see what happens.

I just bought a 72pin standard PC SIMM.  It claims to be 64M 5V 60ns EDO. 
OK, that's all well and good, but it has 12 chips on it.  If 72 pin SIMMs
have a 32 bit data path, how is 32 divisible by 12?

All the chips are the same, they are marked 16X4E8KDW-SS.  They are in a 32
pin SOJ package.  The SIMM is double sided, and has 6 chips on each side. 
There also appears to be a 3.3V regulator on each side (it says SC 3.3
EX1117 on it).

OK, so how does this work?  My only guess is the chips are 16M x 4 (the E
is probably EDO, and the 8 scares me, as that might mean 80ns...., and
these are being sold as 60ns chips), and the chip has ECC.  That would make
16M x 32 for data (64M bytes), and 16M x 8 for ECC????

Austin Franklin
austin@darkroom.com

Article: 14402
Subject: Re: Off topic DRAM/SIMM question....
From: "Austin Franklin" <aus3tin@darkroom.com>
Date: 28 Jan 1999 23:56:31 GMT
Links: << >>  << T >>  << A >>
> All the chips are the same, they are marked 16X4E8KDW-SS.  
> My only guess is the chips are 16M x 4 (the E
> is probably EDO, and the 8 scares me, as that might mean 80ns...., and
> these are being sold as 60ns chips), and the chip has ECC.  That would
make
> 16M x 32 for data (64M bytes), and 16M x 8 for ECC????

Another guess on the 8K is that is the refresh, so 16M x 4 (16X4) EDO (E)
8k refresh (8K) 32 pin SOJ (DW)....the -SS could be a misprint, and suppose
to be -5S, or 50ns self refresh...

Even if I've identified the chips organization, I still don't understand
why 12 chips.  10 chips I would understand if it had 4 bit parity, and 8
chips with no parity.

Austin

Article: 14403
Subject: Re: Off topic DRAM/SIMM question....
From: "Austin Franklin" <aus3tin@darkroom.com>
Date: 29 Jan 1999 00:17:42 GMT
Links: << >>  << T >>  << A >>
> Even if I've identified the chips organization, I still don't understand
> why 12 chips.  10 chips I would understand if it had 4 bit parity, and 8
> chips with no parity.

Apparently they are using four of the x4 chips as x1 chips for true parity.
 Really a waste of memory, but I guess they concluded it's cheaper to do it
that way...  An Asus manual for one of the system boards I have tipped me
off to that, claiming if I wanted to use ECC the SIMM had to have 12 chips,
instead of 8, and claimed the 12 chip SIMMs were 36 bits....

So, I believe I understand it now....

Thanks,

Austin

Article: 14404
Subject: Re: Hysteresis on PLD Clock Inputs
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Thu, 28 Jan 1999 17:41:42 -0700
Links: << >>  << T >>  << A >>
Peter wrote in message <36b4716d.536087703@news.netcomuk.co.uk>...
>
>Peter, I am sure this is incorrect, for the XC3000 config clock input.
>
>After much work with a 350MHz scope (on a PCB with 32-off XC3064 which
>I used to make) I am very sure that even with an extremely clean
>waveform the *maximum* risetime is about 30ns. Any slower than that,
>and it misconfigures.


Read the databook section on configuration.  It says that the CCLK has to be
REAL clean with fast risetimes.  I think it's the most picky part of the
using the chips.

-- andy
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

"In the beginning, there was darkness.  And it was without form, and void.
And there was also me!"
-- Bomb #20, John Carpenter's "Dark Star"



Article: 14405
Subject: No. of CLBs in Xilinx nearly 100% can't implement.
From: atsadang@hotmail.com
Date: Fri, 29 Jan 1999 00:41:46 GMT
Links: << >>  << T >>  << A >>
I'm a FPGA designer, I have a project use Xillinx 4010e-4 PC84 to implement a
digital circuit. My design passed a simulation and place-and-route by Xilinx
Foundation 1.4 program. A utilization in my design is nearly 100% of maximum
CLBs (97%). When I use HardWare Debugger,I wonder why it didn't work. So I
try to reduce one part of a design (reduce to 93% packed CLBs), it can
working. I'm sure that my VHDL and synthesis output files of a design can
implement. If anyone know or have a comment about the cause of this event,
please post a message.	In my opinion, it can't work because delay in a FPGA
chip when it nearly 100%, it has a few CLBs for routing.

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 14406
Subject: Re: The development of a free FPGA synthesis tool
From: "BuckSavage" <wbuckley@transdyn.com>
Date: Thu, 28 Jan 1999 16:47:35 -0800
Links: << >>  << T >>  << A >>

Eric J. Korpela wrote in message <78qdl3$9bg$1@agate.berkeley.edu>...

>I'm not sure I understand what your big problem with "int main()" is.
>Are you arguing that any code that works once is by definition correct
>everywhere?  IMHO, the whole "if it doesn't generate an error it must
>be correct" is a poor standard for program quality.


I do not have a problem with the use of the given construction, just a
problem with programmers who think that such a construction is an
absolute must.  The fact that I can compile and successfully execute
a program which uses the construction "void main()" is sufficient
reason for me to do so.  If the operating system requires some return
code, then the return of such return code can be provided.  However,
this is an operating system issue, not one with the language.  Likewise,
if the compiler complains about the failure to provide a return code,
then it is a compiler issue, and should not effect the operating system.

Operating systems and application programs are not the same thing.
They are each self-contained, and their inter-communication is by
some formal specification.  Failure of one should not adversely
affect the other.  If they do adversely affect the other, then the utility
of each and either is questionable.  Since the goal of automatic
computation is utility, adverse effects are to be avoided.  Hence,
each program must be complete in its own operation, regardless
of the operation of all other programs.

William R. Buckley


Article: 14407
Subject: Re: No. of CLBs in Xilinx nearly 100% can't implement.
From: Ray Andraka <randraka@ids.net>
Date: Thu, 28 Jan 1999 20:32:19 -0500
Links: << >>  << T >>  << A >>
Did you run the timing analyzer on your placed and routed design?  Did you
specify for the PAR to use time constraints.  My guess is that the answer to both
is no.

Why did it work when thinned out but not full, you ask?  An FPGA has limited
resource both in the quantity of logic and in the amount of routing.  When the
device gets packed this full, there is a good chance the routing is congested in
parts of the design, causing some of the routes between CLBs to become very
long.  The 4KE parts are more prone to this than the later 4KX derivatives, as
the later parts have additional routing resources.

The performance of a densely packed design like this can be improved quite
dramatically by floorplanning, which is essentially doing the placement
manually.  You will need to either revert to the Xact6.0 software or upgrade to
Foundation M1.5i to get the graphical floorplanner, which makes looking at the
route congestion and moving CLBs around fairly painless.  Without the graphical
floorplanner, you'll have to get out graph paper and RLOC components in your
design - something that is excessively painful using VHDL synthesis under
Foundation.  With some handcrafting in the form of floorplanning, and perhaps
recoding parts of your VHDL source (or even better working in schematic) you can
usually attain a significant gain in performance (40% or more) and often in
density.  The other option would be to go to a 4013 and/or to a faster speed
grade so that the PAR doesn't have to work so hard to meet timing.  Without some
handcrafting (floorplanning and/or specifying the exact implementation) , you
shouldn't expect to get more than around 60-70% utilization and still make timing
unless you are using very slow clocks.

On something this dense, I would plan on floorplanning and would normally not use
synthesis.

atsadang@hotmail.com wrote:

> I'm a FPGA designer, I have a project use Xillinx 4010e-4 PC84 to implement a
> digital circuit. My design passed a simulation and place-and-route by Xilinx
> Foundation 1.4 program. A utilization in my design is nearly 100% of maximum
> CLBs (97%). When I use HardWare Debugger,I wonder why it didn't work. So I
> try to reduce one part of a design (reduce to 93% packed CLBs), it can
> working. I'm sure that my VHDL and synthesis output files of a design can
> implement. If anyone know or have a comment about the cause of this event,
> please post a message.  In my opinion, it can't work because delay in a FPGA
> chip when it nearly 100%, it has a few CLBs for routing.
>
> -----------== Posted via Deja News, The Discussion Network ==----------
> http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 14408
Subject: Re: Off topic DRAM/SIMM question....
From: "Pascal Dornier" <pdornier@pcengines.com>
Date: Thu, 28 Jan 1999 17:45:49 -0800
Links: << >>  << T >>  << A >>
Austin Franklin wrote in message <01be4b13$ab9800c0$7bab15d1@drt1>...
>I'm stumped, but since there are so many smart people in this NG, I thought
>I'd toss this one out here and see what happens.
>
>I just bought a 72pin standard PC SIMM.  It claims to be 64M 5V 60ns EDO.
>OK, that's all well and good, but it has 12 chips on it.  If 72 pin SIMMs
>have a 32 bit data path, how is 32 divisible by 12?


>All the chips are the same, they are marked 16X4E8KDW-SS.  They are in a 32
>pin SOJ package.  The SIMM is double sided, and has 6 chips on each side.
>There also appears to be a 3.3V regulator on each side (it says SC 3.3
>EX1117 on it).
>
>OK, so how does this work?  My only guess is the chips are 16M x 4 (the E
>is probably EDO, and the 8 scares me, as that might mean 80ns...., and
>these are being sold as 60ns chips), and the chip has ECC.  That would make
>16M x 32 for data (64M bytes), and 16M x 8 for ECC????

The DRAMs are probably 16Mx3 (partially bad 16Mx4 chips) ! The 3.3V
regulators are needed because most 64Mbit DRAMs are 3.3V only. This can
cause you compatibility problems if you also have true 5V SIMMs on the same
DRAM bus.

--------------------------------------------------------------------
Pascal Dornier   pdornier@pcengines.com     http://www.pcengines.com
Your Spec      + PC Engines            = Custom Embedded PC Hardware
--------------------------------------------------------------------


Article: 14409
Subject: Re: The development of a free FPGA synthesis tool
From: Hrvoje Niksic <hniksic@srce.hr>
Date: 29 Jan 1999 03:20:56 +0100
Links: << >>  << T >>  << A >>
"BuckSavage" <wbuckley@transdyn.com> writes:

> I do not have a problem with the use of the given construction, just
> a problem with programmers who think that such a construction is an
> absolute must.  The fact that I can compile and successfully execute
> a program which uses the construction "void main()" is sufficient
> reason for me to do so.

If you compile and successfully execute a program that passes a
different number of arguments to qsort(), will it be the sufficient
reason to do so?

Just like qsort(), int main() is an interface.  By not abiding to the
rules, you are opening a possibility of your program breaking.
Article: 14410
Subject: Atmel IDS 6.00 simulation question
From: "Dr. Vitit Kantabutra" <vkantabu@computer.org>
Date: Thu, 28 Jan 1999 20:18:35 -0700
Links: << >>  << T >>  << A >>
I'm using Atmel IDS 6.00, and have a few questions about the post-layout
(timing) simulator that I'd like to ask all of you about.

(1) I simulated the same circuit using the same command script on all 3
speed ranges; max, typ, and min, and got exactly the same results!  Does
everyone else have this problem?  Something seems quite wrong -- what is
it?

(2) When I simulated the same circuit using different input vectors, all
randomly generated, I got almost the same delay across the different
input vectors for each particular signal.  This shouldn't be the case,
because my circuit has ripple adders!  Again, what's the matter?  Maybe
all my inputs just happen to have the same critical path length (I
haven't checked that), but this appears to be quite unlikely.


Article: 14411
Subject: Re: Off topic DRAM/SIMM question....
From: "Austin Franklin" <aus3tin@darkroom.com>
Date: 29 Jan 1999 03:48:06 GMT
Links: << >>  << T >>  << A >>
> The DRAMs are probably 16Mx3 (partially bad 16Mx4 chips) ! 

That could be so, but then they would not be true parity SIMMs, because you
need to do parity on a byte by byte basis....unless they are ECC, in which
case, it doesn't matter, because the ECC has to be calculated across all 32
bits...

I tried them in my Tyan 1662D 440FX chip set system board, and they pass
the power up memory test but NT won't boot, so I changed back to my 32M
SIMMs, and it boots fine.  Something is different with these chips...

Also, they are the only chips installed in the memory sockets...

Thanks,

Austin

Article: 14412
Subject: Mixed configuration daisy chain
From: John de Papp <jdp@xilinx.com>
Date: Thu, 28 Jan 1999 23:52:02 -0500
Links: << >>  << T >>  << A >>
Has anyone successfully constructed a configuration daisy chain with
Lucent Orca devices and Xilinx FPGA's?  The data sheets indicate the
config. interfaces are nearly identical, but I'm looking for
confirmation from someone who has tried such a scheme.  Any details
would be helpful, like which devices, how many, who served as the
master, etc.

Regards,

john

jdp@xilinx.com


Article: 14413
Subject: Re: Off topic....
From: Brett George <b.george@clarityeq.com>
Date: Fri, 29 Jan 1999 16:57:37 +1000
Links: << >>  << T >>  << A >>
I was going to say humility and compliments generally work wonders
in receiving off-beat replies, but it seems you are responding to your
post more than anyone else!

Brett.

Austin Franklin wrote:

> I'm stumped, but since there are so many smart people in this NG, I thought
> I'd toss this one out here and see what happens.
>
> I just bought a 72pin standard PC SIMM.  It claims to be 64M 5V 60ns EDO.
> OK, that's all well and good, but it has 12 chips on it.  If 72 pin SIMMs
> have a 32 bit data path, how is 32 divisible by 12?
>
> All the chips are the same, they are marked 16X4E8KDW-SS.  They are in a 32
> pin SOJ package.  The SIMM is double sided, and has 6 chips on each side.
> There also appears to be a 3.3V regulator on each side (it says SC 3.3
> EX1117 on it).
>
> OK, so how does this work?  My only guess is the chips are 16M x 4 (the E
> is probably EDO, and the 8 scares me, as that might mean 80ns...., and
> these are being sold as 60ns chips), and the chip has ECC.  That would make
> 16M x 32 for data (64M bytes), and 16M x 8 for ECC????
>
> Austin Franklin
> austin@darkroom.com



Article: 14414
Subject: Hold Time Violation
From: Duck Foot <duckfoot11@hotmail.com>
Date: Fri, 29 Jan 1999 16:42:27 +0900
Links: << >>  << T >>  << A >>
Hi everyone,
    I'm confronting many hold time violations and glitches while
post-synthesis simulation. Since I built the logic with quite high level

description and the logic is very massive, it looks impossible to debug
them one by one.
    Is there any canonical strategy applied to these kind of problems,
or can I ask you for some refernces?



Article: 14415
Subject: Hazard
From: Duck Foot <duckfoot11@hotmail.com>
Date: Fri, 29 Jan 1999 16:59:22 +0900
Links: << >>  << T >>  << A >>
    Textbooks tell how to get rid of static hazards inherent in a sum of
products network. They say the hazard comes from transitions between
neighboring product terms, and can be eliminated by adding redundant
implicants.
    Do we also call the transitions between two apart product terms,
e.g. diagonally positioned ones, hazard? How can I eliminate glitches
born of this kind of network? - In this case circling 0's to eliminate
0-hazard also results in diagonal configuration.

Article: 14416
Subject: Re: C to Hardware translators [was: The development of a free FPGA synthesis tool]
From: ems@riverside-machines.com.NOSPAM
Date: Fri, 29 Jan 1999 11:31:18 GMT
Links: << >>  << T >>  << A >>
On Wed, 27 Jan 1999 10:39:56 +0000, Jonathan Bromley
<jsebromley@brookes.ac.uk> wrote:

>.... Bromley's Criteria for abject failure of any engineering development:
>| 1) it was technically competent
>| 2) it was at least a decade ahead of its time
>| 3) it originated in Britain :-)

and, of course:

4) somebody (a) forgot to patent it, or (b) patented it, and then sold
off the patent without noticing.

i hadn't realised that you could actually *do* anything with Handel-C.
is there a practical mechanism for targetting xilinx? does it work,
how do you do it, how much??

evan

Article: 14417
Subject: Re: Hold Time Violation
From: ems@riverside-machines.com.NOSPAM
Date: Fri, 29 Jan 1999 11:31:44 GMT
Links: << >>  << T >>  << A >>
On Fri, 29 Jan 1999 16:42:27 +0900, Duck Foot <duckfoot11@hotmail.com>
wrote:

>Hi everyone,
>    I'm confronting many hold time violations and glitches while
>post-synthesis simulation. Since I built the logic with quite high level
>
>description and the logic is very massive, it looks impossible to debug
>them one by one.
>    Is there any canonical strategy applied to these kind of problems,
>or can I ask you for some refernces?

you don't give much information, but i assume that you're using an
fpga, since you're posting to c.a.f.

if your fpga has a dedicated clock net, then you should use it. this
should ensure that you don't get any violations.

if you are using a dedicated clock net, and you're still seeing hold
time violations in the simulation, then this is almost certainly
because you're simulating at a clock frequency which is too high for
your device. check your static timing report to find your maximum
operating frequency.

evan

Article: 14418
Subject: Q: Lucent OR3TP12 evaluation board available?
From: Joerg Langwald <Joerg.Langwald@DLR.de>
Date: Fri, 29 Jan 1999 12:33:56 +0100
Links: << >>  << T >>  << A >>
Is there anyone developing/distributing an evaluation board for 
Lucent's FPSC with master/target PCI interface OR3TP12 (PCI or 
PMC formfactor)?

Thanks, Joerg
Article: 14419
Subject: Re: PLL in FPGA
From: "Manfred Kraus" <mkrausnews@cesys.com>
Date: Fri, 29 Jan 1999 13:30:41 +0100
Links: << >>  << T >>  << A >>
Thats the way I tried to implement an DPLL.
Unfortunately it will never be stable. The Accumulator
constant will alternate between its limits.
With a few tricks you can get it stable, but then its
not always locked.

If you need only low frequencies (< 1 MHz) you can
count the System-clock  (> 24 MHz) pulses between the edges of
the referency input frequency. Shift right the result 4, 8 ,16 or 32 times.
Use this value as a constant for an systemclock clocked Accu. You will
get a Accu  overflow frequency of 2, 4, 8 .. times the reference frequency.

This way you can multiply the input (reference) frequency by a power of 2.
If you want you can scale this higher frequency down using another
Accumulator (20..24 Bit) with a fixed constant.

This is the result of 2 years hard work !!!

Manfred Kraus

mkraus@bcesys.com

to answer: remove the b before cesys.



Article: 14420
Subject: Re: Atmel IDS 6.00 simulation question
From: "denis lachapelle" <sysacom@cam.org>
Date: Fri, 29 Jan 1999 07:48:45 -0500
Links: << >>  << T >>  << A >>
Is there a simulator in IDS 6.0 ?
Which simulator do you use ?


--
Denis Lachapelle, sysacom@cam.org
Sysacom R&D plus inc.
www.cam.org/~sysacom
tel 450 585-6396, fax 450 582-3231

Dr. Vitit Kantabutra wrote in message <36B1288A.A0EE3E43@computer.org>...
>I'm using Atmel IDS 6.00, and have a few questions about the post-layout
>(timing) simulator that I'd like to ask all of you about.
>
>(1) I simulated the same circuit using the same command script on all 3
>speed ranges; max, typ, and min, and got exactly the same results!  Does
>everyone else have this problem?  Something seems quite wrong -- what is
>it?
>
>(2) When I simulated the same circuit using different input vectors, all
>randomly generated, I got almost the same delay across the different
>input vectors for each particular signal.  This shouldn't be the case,
>because my circuit has ripple adders!  Again, what's the matter?  Maybe
>all my inputs just happen to have the same critical path length (I
>haven't checked that), but this appears to be quite unlikely.
>
>


Article: 14421
Subject: Re: Hold Time Violation
From: tony.hurson@mindspring.com (Tony Hurson)
Date: Fri, 29 Jan 1999 13:29:48 GMT
Links: << >>  << T >>  << A >>
Duck Foot <duckfoot11@hotmail.com> wrote:

>Hi everyone,
>    I'm confronting many hold time violations and glitches while
>post-synthesis simulation. Since I built the logic with quite high level

>description and the logic is very massive, it looks impossible to debug
>them one by one.
>    Is there any canonical strategy applied to these kind of problems,
>or can I ask you for some refernces?

Check your synthesis tool for clock skew management techniques. The
most common way of designing out hold time violations is via an
adjustable 'clock skew uncertainty factor'. One can adjust this to a
conservatively high number (say, 1.0ns for a 0.25um process) and the
synthesis will automatically insert delay elements within short,
register-to-register or latch-to-latch paths. The uncertainty factor
is equivalent to the worst-case clock skew experienced between any
pair of sequential elements. If you plug too large an uncertainty
value, your design gate count/area will grow, because the synthesis
tool will have to fill up your design with delay elements.

Good luck!

Tony Hurson.

tony.hurson  - at - ieee.org




Article: 14422
Subject: Re: Off topic DRAM/SIMM question....
From: "Austin Franklin" <aus3tin@darkroom.com>
Date: 29 Jan 1999 14:15:04 GMT
Links: << >>  << T >>  << A >>

> > The DRAMs are probably 16Mx3 (partially bad 16Mx4 chips) ! 

You were right!  I buzzed out the SIMM.  The parity bits aren't connected,
all the chips only use 3 bits, and four of the chips have two data pins
tied together (which I think is weird...), so if 8 chips are using 3 bits,
and 4 are using 2 bits, that makes 32 bits!

Hum.

Austin

Article: 14423
Subject: Re: The development of a free FPGA synthesis tool
From: Gabriel Dos_Reis <gdosreis@sophia.inria.fr>
Date: 29 Jan 1999 15:46:27 +0100
Links: << >>  << T >>  << A >>
Hrvoje Niksic <hniksic@srce.hr> writes:


[...]

--------------
| Just like qsort(), int main() is an interface.  By not abiding to the
| rules, you are opening a possibility of your program breaking.
--------------

Unless I'm mistaken, I think he doesn't care of this possibility. Sigh.

-- Gaby
Article: 14424
Subject: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
From: husby@fnal.gov (Don Husby)
Date: Fri, 29 Jan 1999 15:28:45 GMT
Links: << >>  << T >>  << A >>
Phil Hays <spampostmaster@sprynet.com> wrote:
> Perhaps someone will post some prices.  Spartan XL (say XCS05pc84-4)
> would be another interesting point.  It would probably top the
> schematic's speed (the schematic is still locked into whatever Orca's
> cost and speed is)

Not entirely true.  I can still target Xilinx devices with Viewlogic schematics.
I would have to change the SRAM part to use the Xilinx library.

> and I suspect it would be cheaper.  Got the
> numbers?  The VHDL design isn't locked into any part by non portable
> schematics.

I agree.  I'd really like it to be true that some HDL is portable and efficient
for all FPGA designs.  I did this evaluation hoping it was true.  I beleive
that eventually it will be true.  (Maybe we have to wait for a better HDL to
come along.)  But for now it looks to me like schematics are still the tool of
choice for pushing a chip to the max.  Note that my design was targeted
to run at 50 MHz, so all three tools would have met the speed requirements.
However its surprising to see that it took 50% more space when using
VHDL even when I used Exemplar's "Optimize for Area" switch.

Besides, design entry isn't the most time consuming part of a design. It took
maybe 1 hour to translate the schematic to VHDL.  It would take about the
same amount of time to re-enter the schematic if I had to (not including the
documentation). This is small compared to the several hours it took dicking
around with the VHDL tools to try to coax them to do what I wanted.  This is
very small compared to the effort it would take to floorplan a design or fix
a mapping problem when all of the signal names have been changed to b0Z0Z0_3_int.

As an example, look at how Exemplar mapped the 16-bit wide RAM.  The ram and
15 of the output registers were mapped into 4 PFU.  The 16th output register
was mapped into a PFU all by itself, even when it would be smaller and faster
and more routable if it was mapped with the other registers.  I don't know if
it's possible to coax Exemplar into doing it correctly, but I do know that it
would take me at least an hour to figure it out.

Schematics seem to be less prone to this kind of "failed magic".
A clock-enable pin on a flip-flop is hard to misinterpret.  An "if-then"
statement buried in a VHDL process can be synthesized many different
ways, and the designer has almost no control.  In the case of the stray
ram register, the clock-enable was interpreted differently from the other
registers even though they all came from the same VHDL statements.



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