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Messages from 13050

Article: 13050
Subject: Re: placement&routing problems
From: thor@sm.luth.se_SPAM_ME_NOT (Jonas Thor)
Date: Fri, 13 Nov 1998 11:19:08 GMT
Links: << >>  << T >>  << A >>
On Thu, 12 Nov 1998 19:02:25 GMT, fliptron@netcom.com (Philip Freidin)
wrote:

>In article <NRZz7CAfxKS2EwwE@edmoore.demon.co.uk> Edward Moore <edmoore@edmoore.demon.co.uk> writes:
>> etc, etc..
>>4. Contrary to popular belief, structured hierarchical relative
>>placement is possible with VHDL too. In fact it's easier and quicker.
>>Edward Moore
>
>This is an amazing (to me at least) claim. Please give an example of how 
>you do structured hierarchical relative placement in VHDL. 

It is possible to write structural VHDL with RLOCs for the XC6200
device. You can use a tool called VELAB that translates your VHDL to
EDIF. However to my knowledge there is no such tool for the other
Xilinx devices.... which is the problem in this case...

Anyways, here is an example of RLOCed shiftregister for the XC6200
device :

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library PRIMS;
use PRIMS.all;
library XACT;
use XACT.xact6000_attributes_simple.all;


architecture struct of shift is
  component shift_rep
    port (clk ,clr, en : in std_logic;
          D            : in std_logic;
          Q            : out std_logic);
  end component;

  signal dff_out : std_logic_vector (1 to n_bits);

begin
  -- first flip-flop
  first : shift_rep
      port map ( clk     => clk,
                 clr     => clr,
                 en      => en,
                 D       => D,
                 Q => dff_out(1));


  theRest : if (n_bits >1) generate
      shiftrep : for n in 2 to n_bits generate
          -- synopsys translate_off
          attribute RLOC of repcell : label is "X0Y,n," ;
          -- synopsys translate_on
          repcell : shift_rep
              port map ( clk  => clk,
                         clr  => clr,
                         en   => en,
                         D    => dff_out(n-1),
                         Q    => dff_out(n));
      end generate;
  end generate;
                  
  Q <= dff_out;

end struct;


-- **** Repeating bit shift register ***********
library IEEE;
use IEEE.std_logic_1164.all;
library PRIMS;
use PRIMS.all;
library XACT;
use XACT.xact6000_attributes_simple.all;

entity shift_rep is
  port (clk, clr, en : in std_logic;
        D : in std_logic;
        Q : out std_logic);
end shift_rep;

architecture struct of shift_rep is

  component fdc
    port (d, c, clr  : in std_logic;
          q          : out std_logic);
  end component;

  component m2_1
    port (o          : out std_logic;
          d1, d0, s0 : in std_logic);
  end component;

  signal mux_out, Q_i : std_logic;

  ATTRIBUTE rloc OF mux : LABEL IS "X0Y0";
  ATTRIBUTE rloc OF dff : LABEL IS "X0Y0";

begin 
  mux : m2_1
      port map ( d0 => Q_i,
                 d1 => D,
                 s0 => en,
                 o  => mux_out);

  dff : fdc
      port map ( d   => mux_out,
                 c   => clk,
                 clr => clr,
                 q   => Q_i);

  Q <= Q_i;

end struct;  
Article: 13051
Subject: SIS under Linux
From: Dominic Camus <dom@fastram.demon.co.uk>
Date: Fri, 13 Nov 1998 11:28:34 +0000
Links: << >>  << T >>  << A >>
Hi,

Can anyone out there recommend a way of getting the SIS synthesis
package from Berkeley running under Linux (Redhat 5.1) ?

I've downloaded the source and patch from the Berkeley FTP site, but
attempting to compile it throws up huge numbers of errors ( mostly
connected with the Makefiles I think, but my feeble attempts to fix
these problems have met with no success ).

Either a suitable binary (my machine is an Intel Pentium II) or a Linux
patch or just hints on how to get it working would be very welcome !

Cheers,

Dominic.

PS. I have tried the usual SIS help email address at Berkeley, but there    
    has been no response.
 
-- 
------------------------------------------------
| Dominic Camus                                |
| Oxford University Hardware Compilation Group |
| Email: dominic.camus@comlab.ox.ac.uk         |
------------------------------------------------
Article: 13052
Subject: Re: Affordable boundary scan (JTAG) interconnect testing software any
From: Jonathan Bromley <jsebromley@brookes.ac.uk>
Date: Fri, 13 Nov 1998 12:10:09 +0000
Links: << >>  << T >>  << A >>
Edward Wallington wrote:
> 
> Hi,
> 
> apologies if this is slightly off subject, but I figured we must all
> have to do something about testing:

> Has anybody found any affordable(?) JTAG interconnect testing > software?

Interesting idea.  I sympathise strongly - about 12 months ago I did a
board with a 208pin QFP CPU and two FPGAs all of which had JTAG,
so I brought the TAP out to a connector but nobody ever got off their
backside to do anything about test software.  I think there is
probably a neat market niche here, but I'd be surprised if anyone
could ever make money out of it.

As I see it, small-volume system builders would find JTAG very useful
and can see how easy it is: no fundamental reason why you shouldn't
work it slowly off a PC parallel port, and for our sort of quantities
a reliable but slow JTAG test taking 10 minutes or more would be 
time well spent.  But there are many obstacles:
1)
low level driver software to shift bits through the TAP - this is
dead easy
2)
Interface from CAD PCB layout tools' netlists, so we can decide
what tests to perform
3)
Boundary-scan-description-language (BSDL) parser so that we can 
decide what bit patterns to shift in and out in order to test 
various nets
4)
Getting BSDL files out of your device suppliers in machine-readable
form rather than scribbled on the back of a cigarette packet
5)
Test pattern generation software, driven by (2) and (3), to create
an optimal set of tests that will exercise your PCB's netlist

The laughable proliferation of obscure, proprietary, incompatible file
formats for the various CAD data makes this surprisingly hard.  And
that's why JTAG Technologies and so forth need to charge 20k per
seat.  JTAG Technologies have some (yet again) proprietary file
formats that they use for describing memory arrays that are attached
to your JTAG-compliant parts, so that you can do memory tests too.

The EDA companies will rot in purgatory for the hassle they have 
inflicted on us through their inability to settle on a simple,
uniform, TEXT-BASED data interchange format IN THE PUBLIC DOMAIN.
(Sorry, _which_ version of EDIF is it that you support?...)  But
until the final day of judgment, it's the poor punters like you and
me who suffer.

Meanwhile, has any PERL guru out there got (a) a BDSL parser,
(b) a universal netlist translator?

frustratedly

Jonathan Bromley
Article: 13053
Subject: Re: VHDL project
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Fri, 13 Nov 1998 08:38:56 -0500
Links: << >>  << T >>  << A >>
A multiplier isn't all that hard to do.  Check out my website for a discussion of
multiplier architectures suited for FPGAs (hint: a multiplier optimized for an
ASIC implementation is usually not a good fit for an FPGA).

Another project idea is (OH NO, Andraka's pitching CORDIC **again**) a CORDIC
processor.  CORDIC is a shift add algorithm for rotating vectors.  It is commonly
used to simultaneously compute sin and cos, perform polar conversions etc.  It can
also be used to compute square roots, exponentials, logs, multiplication and
division, and hyperbolic trig functions.  Since it does a vector rotation, it can
also be used to replace complex multipliers and look up tables any where you
multiply by a complex exponential (as in modulation/demodulation, FFT's, DCTs
etc.)  I have a paper I presented discussing the CORDIC algorithm and FPGA
implementations available on my website too.  Once you understand the math (which
is not that difficult- just a bit of trig) the implementation is really pretty
easy, certainly no more difficult than a multiplier, and besides you'll learn
something you probably didn't know.  Oh, and the tie in to computer architecture?
Guess what the 8087 math coprocessor and the HP-45 calculator use.



leslie.yip@asmpt.com wrote:

> Hello
>
> I think that a 16-bit x 16-bit binary multiplier will be quite challenging.
> After you implemented your project, would you place on the web site or give me
> to have a look?
>
> Leslie Yip
>
> In article <3ej22.1081$4S.3996@weber.videotron.net>,
>   "Stephane Marcouiller" <mars02@gel.usherb.ca> wrote:
> > I have to find a suitable VHDL project for my course Computer Architecture
> > II
> > Suggestions are welcome
> >
> > Currently I have a couple of ideas like : branch prediction buffer,
> > pipelined CPU, L1 et L2 cache,...
> >
> > Do you have other ideas ?
> >
> > P.S. It must be possible to do it whitin 3 weeks * 5 hours/week = 15 hours
> > approx.
> >
> >     Thx
> >
> >
>
> -----------== Posted via Deja News, The Discussion Network ==----------
> http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 13054
Subject: Re: placement&routing problems
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Fri, 13 Nov 1998 08:50:42 -0500
Links: << >>  << T >>  << A >>


Phil Hays wrote:

> Philip Freidin wrote:
> >
> > In article <NRZz7CAfxKS2EwwE@edmoore.demon.co.uk> Edward Moore <edmoore@edmoore.demon.co.uk> writes:
> > > etc, etc..
> > >4. Contrary to popular belief, structured hierarchical relative
> > >placement is possible with VHDL too. In fact it's easier and quicker.
> > >Edward Moore
> >
> > This is an amazing (to me at least) claim. Please give an example of how
> > you do structured hierarchical relative placement in VHDL.

That's why I said "show me" in my post via deja news.  If there was any response, I unfortunately missed
it thanks to a disk crash on my ISPs newsreader.  As far as I know, no one has come forward with support
to this claim (I don't see anything on DejaNews except a comment about the VELAB 6200 flow.

>
>
> Synplicity has such a HDL floorplanner in the works.  I've played with
> it a little.  It is a cool idea, as a large part of making a fast design
> is controlling the placement of the parts of the design.
>
> I have no connection to Synplicity other than using their products.

That floorplanner is not Hierarchical.  The floorplanner has to be hierarchical to be of any real use.  If
I wanted to do flat floorplanning, I could use the xilinx floorplanner just as easily and not have to
learn yet another tool!

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 13055
Subject: Re: WorkView office Library files need
From: Chris Rottner <crottner@edasource.com>
Date: Fri, 13 Nov 1998 13:55:15 +0000
Links: << >>  << T >>  << A >>
In article <72g995$bui$1@news.seed.net.tw>, John Huang
<hungi@tpts4.seed.net.tw> writes
>
>Alex Protasiewicz g峹 <72f4l5$b6q@bgtnsc03.worldnet.att.net>...
>>There should be a 2nd CD in your jewel box that contain the library files.
>>
>>John Huang wrote in message <72dt1i$qm0$1@news.seed.net.tw>...
>>>Hi:
>>>    I need Workview office library files, such like viewdraw and viewsim
>But my version is signle Cd
>
>
>
If there is a single CD then I presume that it is a FPGA vendor locked
version. FPGA vendors who resell WVO restricted to their technology only
supply one CD.

The libraries for use with Viewdraw and ViewSim are available on the CD
with your vendors place and route software.


-- 
Chris Rottner                    <
 ---------------------------  <  <  <  --- mailto:crottner@edasource.com
| Direct Insight Ltd       <  <  <  <  >   Tel: +44 1280 700262         |
| http://www.edasource.com    <  <  <      Fax: +44 1280 700577         |
 ------------------------------  <  ------------------------------------
Article: 13056
Subject: Alternative to EPM5128 OTP
From: "Arnold Beland" <acbel@worldnet.att.net>
Date: 13 Nov 1998 13:55:48 GMT
Links: << >>  << T >>  << A >>
I have been using Altera's EPM5128 devices since they came out.  I am using
increasing quantities of them at $55 a pop.  Is there a cheaper alternative?


Article: 13057
Subject: Re: Affordable boundary scan (JTAG) interconnect testing software any
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Fri, 13 Nov 1998 08:57:32 -0500
Links: << >>  << T >>  << A >>
I don't really understand the motivation for using JTAG on an SRAM based FPGA.
With relatively little effort, you can design a test application for the FPGA
that tests the FPGA's interconnect and any memory connected to the FPGA at
system speeds.  If the intervening logic is surrounded by FPGAs you can test
that at speed with FPGA test programs too.  Reconfiguration is an extremely
powerful debug and test tool, so why not use it.  I discuss this test
philosophy and the benefits obtained in a paper I presented this fall.  That
paper, "An FPGA based processor yields a real time high fidelity radar
environment simulator" is available on my website in adobe acrobat format.

Jonathan Bromley wrote:

> Edward Wallington wrote:
> >
> > Hi,
> >
> > apologies if this is slightly off subject, but I figured we must all
> > have to do something about testing:
>
> > Has anybody found any affordable(?) JTAG interconnect testing > software?
>
> Interesting idea.  I sympathise strongly - about 12 months ago I did a
> board with a 208pin QFP CPU and two FPGAs all of which had JTAG,
> so I brought the TAP out to a connector but nobody ever got off their
> backside to do anything about test software.  I think there is
> probably a neat market niche here, but I'd be surprised if anyone
> could ever make money out of it.
>
> As I see it, small-volume system builders would find JTAG very useful
> and can see how easy it is: no fundamental reason why you shouldn't
> work it slowly off a PC parallel port, and for our sort of quantities
> a reliable but slow JTAG test taking 10 minutes or more would be
> time well spent.  But there are many obstacles:
> 1)
> low level driver software to shift bits through the TAP - this is
> dead easy
> 2)
> Interface from CAD PCB layout tools' netlists, so we can decide
> what tests to perform
> 3)
> Boundary-scan-description-language (BSDL) parser so that we can
> decide what bit patterns to shift in and out in order to test
> various nets
> 4)
> Getting BSDL files out of your device suppliers in machine-readable
> form rather than scribbled on the back of a cigarette packet
> 5)
> Test pattern generation software, driven by (2) and (3), to create
> an optimal set of tests that will exercise your PCB's netlist
>
> The laughable proliferation of obscure, proprietary, incompatible file
> formats for the various CAD data makes this surprisingly hard.  And
> that's why JTAG Technologies and so forth need to charge 20k per
> seat.  JTAG Technologies have some (yet again) proprietary file
> formats that they use for describing memory arrays that are attached
> to your JTAG-compliant parts, so that you can do memory tests too.
>
> The EDA companies will rot in purgatory for the hassle they have
> inflicted on us through their inability to settle on a simple,
> uniform, TEXT-BASED data interchange format IN THE PUBLIC DOMAIN.
> (Sorry, _which_ version of EDIF is it that you support?...)  But
> until the final day of judgment, it's the poor punters like you and
> me who suffer.
>
> Meanwhile, has any PERL guru out there got (a) a BDSL parser,
> (b) a universal netlist translator?
>
> frustratedly
>
> Jonathan Bromley



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 13058
Subject: Re: Alternative to EPM5128 OTP
From: "Steve" <reply.through.newsgroup@paranoid.com>
Date: Fri, 13 Nov 1998 14:54:52 GMT
Links: << >>  << T >>  << A >>
Can you relayout the board?
I assume you have the 68 pin PLCC?

Arnold Beland wrote in message <72hdp4$ib7@bgtnsc03.worldnet.att.net>...
>I have been using Altera's EPM5128 devices since they came out.  I am using
>increasing quantities of them at $55 a pop.  Is there a cheaper
alternative?
>
>


Article: 13059
Subject: Xilinx Core generator
From: "Fredj Rouatbi" <NOSPAM__frouatbi@nsicomm.com>
Date: Fri, 13 Nov 1998 11:11:42 -0500
Links: << >>  << T >>  << A >>
Hi,

I noticed that people in this newsgroup discuss subjects related
to fpga. I would like to participate with some issues I encounter
when doing FPGAs. you can reply to me without the NOSPAM__

issue:

Hi,

I'm using the core generator, to create multipliers 9x9. I created the
symbol
and the edn netlist. I imported them to the foundation 1.5.

The output of the multiplier is always 0 in functional simulation.

Can I run functional simulation with coregen blocks in the foundation tool ?
Or is only for timing simulation after implementation ?


Fredj Rouatbi
NSI communications
NOSPAM__frouatbi@nsicomm.com



Article: 13060
Subject: Re: hard macros design flow for XILINX Foundation Express
From: "Fredj Rouatbi" <NOSPAM__frouatbi@nsicomm.com>
Date: Fri, 13 Nov 1998 12:43:38 -0500
Links: << >>  << T >>  << A >>
Hi Andreas,

I encountered the same problem, as you do. I use an FPGA with
some models for external chips in schematics (memories, FIFO, other
chips).

Then I route the FPGA. When doing timing simulation, I can't mix rooted
netlist with schematic models.

This should be a nice feature.

NOSPAM_frouatbi@nsicomm.com
NSI communications

Andreas Doering wrote in message <36485B14.5B9521CE@iti.mu-luebeck.de>...
>Hello,
>we want to use hard macros (prorouted) with XILINX
>Foundation and Synopsys FPGA-Express (or XILINX Alliance
>and Synopsys FPGA-Compiler).
>As far we have searched it seemas to be hard to intergrate this
>into a reasonable design flow.
>Details:
>Assume I have already defined and routed a macro (with EPIC).
>I want to declare it as a component in VHDL and integrate
>it in the design flow. Therefore I have to run
>VHDL-Express, NGDBUILD and MAP with one undefined
>component. Of course for VHDL-Express this is no problem
>because this is the same as using LogiBlox components.
>But how do I pass NGDBUILD and MAP?
>(The rest of the design flow is clear:
>load unplaced/unrouted design into epic, add the macro,
>connect it, save it from EPIC go through PAR - done)
>I have to make sure that the signals/logic connected to
>my macro do not get optimized away.
>In the moment I have only two ideas:
>A) define some crazy component with flip-flops at the boundaries,
>protect them by dont-touch through Synopsys (possible at least with FPGA
>compiler), hope that the flip-flops are enough for XILINX tools to not
>fuzz around with it and remove this in EPIC.
>Problem: dirty solution, apears as a lot of hacking is necessary.
>B) create the complete netlist/components for the macro
>   and procede as in A, maybe then one does not really
>   use EPIC but uses the knowledge of the placement of the
>   individual CLBS and the routing between them for constraints.
>   I am afraid that this is very slow.
>Andreas
>--
>---------------------------------------------------------------
>                        Andreas Doering
>                        Medizinische Universitaet zu Luebeck
>                        Institut fuer Technische Informatik
>                        Ratzeburger Allee 160
>
>                        D-23538 Luebeck
>                        Germany
>
>         Tel.: +49 451 500-3741
>         Fax:  +49 451 500-3687
>         Email: doering@iti.mu-luebeck.de
>                        http://www.iti.mu-luebeck.de/~doering/
>----------------------------------------------------------------


Article: 13061
Subject: Re: Alternative to EPM5128 OTP
From: "Arnold Beland" <acbel@worldnet.att.net>
Date: 13 Nov 1998 18:22:44 GMT
Links: << >>  << T >>  << A >>
Yes, I have lots of practice with 68 pin PLCC's.  Altera's fitter likes to
choose different pins with even a minor change in logic.

Steve wrote in message <0LX22.286$2A1.253@typhoon.mbnet.mb.ca>...
>Can you relayout the board?
>I assume you have the 68 pin PLCC?
>
>Arnold Beland wrote in message <72hdp4$ib7@bgtnsc03.worldnet.att.net>...
>>I have been using Altera's EPM5128 devices since they came out.  I am
using
>>increasing quantities of them at $55 a pop.  Is there a cheaper
>alternative?
>>
>>
>
>


Article: 13062
Subject: Board for FPGA ?
From: p52mofej@uco.es
Date: Fri, 13 Nov 1998 19:54:28 GMT
Links: << >>  << T >>  << A >>


Where could I find information to make an experimental board for FPGA?
Thanks.

--
Jose Moreno
p52mofej@uco.es

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 13063
Subject: Re: Xilinx Core generator
From: "Fredj Rouatbi" <NOSPAM__frouatbi@nsicomm.com>
Date: Fri, 13 Nov 1998 15:00:16 -0500
Links: << >>  << T >>  << A >>
Hi,

I found my problem, This is a long counter and it needs a couple of clock
cycles
to produce an output. It generates an output after few clock cycles.

Please disregard,

Fredj Rouatbi
NSI communications
NOSPAM__frouatbi@nsicomm.com

Fredj Rouatbi wrote in message <72hlnk$v22$1@news.interlink.net>...
>Hi,
>
>I noticed that people in this newsgroup discuss subjects related
>to fpga. I would like to participate with some issues I encounter
>when doing FPGAs. you can reply to me without the NOSPAM__
>
>issue:
>
>Hi,
>
>I'm using the core generator, to create multipliers 9x9. I created the
>symbol
>and the edn netlist. I imported them to the foundation 1.5.
>
>The output of the multiplier is always 0 in functional simulation.
>
>Can I run functional simulation with coregen blocks in the foundation tool
?
>Or is only for timing simulation after implementation ?
>
>
>Fredj Rouatbi
>NSI communications
>NOSPAM__frouatbi@nsicomm.com
>
>
>


Article: 13064
Subject: Re: DES in VHDL?
From: christof@goya.WPI.EDU (Christof Paar)
Date: 14 Nov 1998 01:51:22 GMT
Links: << >>  << T >>  << A >>

We studied and optimized DES for the Xilinx XC4000 series
with -3 speed grade. Here are our main results:


#pipeline stages  Mb/sec  CLBs used  device 

1                 99      262        4008
2                 184     433        4013
4                 403     741        4028


We also compared loop unrolling vs. pipelingin and several 
other issues. More info is in our SAC '98 paper and in Jens 
Kaps' thesis, both of which can be found on our web page at

   http://ece.wpi.edu/Research/crypt

Regards,

Christof

-- 
***********************************************************************
                 Christof Paar,  Assistant Professor
          Cryptography and Information Security (CRIS) Group
      ECE Dept., WPI, 100 Institute Rd., Worcester, MA 01609, USA
fon: (508) 831 5061    email: christof@ece.wpi.edu   
fax: (508) 831 5491    www:   http://ee.wpi.edu/People/faculty/cxp.html
***********************************************************************

Article: 13065
Subject: Xilinx COREgen and Leonardo troubles...
From: janovetz@ews.uiuc.edu (Jacob W Janovetz)
Date: 14 Nov 1998 04:04:50 GMT
Links: << >>  << T >>  << A >>
Hello,

   I've "built" a multiplier (10-bit by 8-bit) component
from COREgen (for Solaris -- Linux would be preferred, by the way).
I get the component output as mult10x8.xnf.

   Now, I try to instantiate that in VHDL under Leonardo.  
I get the following error from 'ngdbuild':

WARNING:basnb:79 - Pin mismatch between block "themult", TYPE="mult10x8", and
   file "<MY_DIRECTORY>/mult10x8.ngo" at pin
   "prod(0)".  Please make sure that all pins on the instantiated component
   match pins in the lower-level design block.  (Pin-name matching is
   case-insensitive.)


prod(0) is the LSB of the product pin.  Now, I've read a few 
things about this error (namely solution 2234) in the help.  It
says to change the bus config under logiblox.ini.  However, I look
at the coregen.ini file under $COREGEN/wkg and there is nothing to
address this.  In addition, there are no setup menus in COREgen to
help me out.

   What needs to be done here?  If someone knows what's going on,
I can send my VHDL, XNF, EDIF files or what not to show how I'm 
doing things.  Thanks for any assistance.


    Cheers,
    Jake


--
   janovetz@uiuc.edu    | Once you have flown, you will walk the earth with
 University of Illinois | your eyes turned skyward, for there you have been,
                        | there you long to return.     -- da Vinci
        PP-ASEL         | http://www.ews.uiuc.edu/~janovetz/index.html
Article: 13066
Subject: Help! ViewSynther Error
From: "John Huang" <hungi@tpts4.seed.net.tw>
Date: Sat, 14 Nov 1998 13:26:29 +0800
Links: << >>  << T >>  << A >>
    Hi:
 I got Error Message from ViewSynthesis , but
I don't know what is it mean, the message is
stored in synth.err

---Terminating: slavs (slavs).

please tell me what happen!


John Huang


Article: 13067
Subject: Re: Problem with the ABEL to Macro convertion in XILINX FB1.3
From: "Manfred Kraus" <mkraus@xxcesys.com>
Date: Sat, 14 Nov 1998 12:21:45 +0100
Links: << >>  << T >>  << A >>
Hi Jaroslaw,
check your license, dongle, ...
I had the same prob
Manfred



Jaroslaw Cichorski Jr. schrieb in Nachricht
<36486f00.1268843@news.tpsa.pl>...
>Hi,
>I have following Problem with the HDL in Foundation 1.3.
>After I define ABEL code and try to convert it to Macro, the
>abl2edif.exe (called from HDL) reports following Error:
>
>quote
>Errors report not available
>Use Synthesis/View Report for detailed synthesis report
>/quote



Article: 13068
Subject: Re: placement&routing problems
From: Edward Moore <edmoore@edmoore.demon.co.uk>
Date: Sat, 14 Nov 1998 16:07:14 +0000
Links: << >>  << T >>  << A >>
In article <fliptronF2Bow1.30I@netcom.com>, Philip Freidin
<fliptron@netcom.com> writes
>In article <NRZz7CAfxKS2EwwE@edmoore.demon.co.uk> Edward Moore 
><edmoore@edmoore.demon.co.uk> writes:
>> etc, etc..
>>4. Contrary to popular belief, structured hierarchical relative
>>placement is possible with VHDL too. In fact it's easier and quicker.
>>Edward Moore
>
>This is an amazing (to me at least) claim. Please give an example of how 
>you do structured hierarchical relative placement in VHDL. 
>
>Philip Freidin
>

Sorry about the delay in replying to everyone. Where do i begin ?. Well,
firstly I don't think this is anything new. It is the mechanism used by
Exemplar Leonardo to generate what they call 'modgens' (carry chains and
ram blocks), which are created internally in VHDL (even for Verilog
synthesis). Other examples can be found in the vhdl source directories
for Xilinx LogiBlox. 

I should have left out the last comment in my orignal post about it
being quicker and easier in VHDL. It is once you have done all of the
ground work in creating parameterizable VHDL code, but thats not much
use to the original postee, who probably needed a quick fix, and was
using Verilg-XL anyway. (which i have absoloutely no experience with, so
the following may not be possible in Verilog, and perhaps that's why
Examplar use VHDL internally).

Relative placement in VHDL requires the following:

1. 'Black box' VHDL components (similar to schematic symbols) for the
Xilinx primitives, ie FD, LD, CY4, FMAP, HMAP, CY4, CY4_1-49 etc etc.
Also create underlying simulation models for all of these.

2.  The ability to pass attributes to these components so they will
appear in the XNF file, ie RLOC, HU_SET or U_SET, CYMODE etc. For
Leonardo, this kind of thing is done using:

        ATTRIBUTE u_set : STRING;
        ATTRIBUTE u_set of u1 : LABEL IS "whatever";

3. The ability to pass STRING's (for U_SETs) and INTEGERs (for RLOCs)
down through the VHDL hierarchy using GENERICs. I am told that this may
not be possible with some synthesizers, which only implement a small
sub-set of the VHDL language.

Structures created using this method can be parameterizable (is that a
real word?). A high level ram block can be passed:

                GENERIC MAP(
                        width           => 16,
                        depth           => 128,
                        use_tristates   => TRUE, -- as opposed to muxes'
                        x_rloc          => 0,
                        y_rloc          => 0,
                        huset_name      => "my_ram_block" )

Or you could have a high level CORDIC rotator component with
parameterized precision and pipeline delay.

Either the same huset_name is passed to several components with varying
x and y rloc's, or a unique huset name is passed to each instantiation
of the top-level block.

I hope this makes things a little clearer; the fine details can be
figured out for yourselves. (This stuff takes time to write, and I am a
litle uneasy about posting large sections of our source code).
                        
All of this stuff was created a few years back when the synthesizers and
Xilinx M1 tools were not so good, and we were worried that inferred
designs wouldn't run at the required 75 MHz. Ironically, since the tools
have improved so much relative placement is required less and less, and
our top-level entity often has the following line:

        CONSTANT use_rlocs : FALSE; -- let M1 choose placement

-- 
Edward Moore
Not speaking officially for Snell & Willcox Ltd.

Article: 13069
Subject: Re: Board for FPGA ?
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Sat, 14 Nov 1998 09:36:32 -0800
Links: << >>  << T >>  << A >>
There is a list of existing FPGA-based boards on The Programmable Logic Jump
Station at http://www.optimagic.com/boards.html.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

p52mofej@uco.es wrote in message <72i2pk$n1e$1@nnrp1.dejanews.com>...
>
>
>Where could I find information to make an experimental board for FPGA?
>Thanks.
>
>--
>Jose Moreno
>p52mofej@uco.es
>
>-----------== Posted via Deja News, The Discussion Network ==----------
>http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own


Article: 13070
Subject: Re: Looking for a good documentation on FPGA
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Sat, 14 Nov 1998 09:39:48 -0800
Links: << >>  << T >>  << A >>
You can find some tutorial information via The Programmable Logic Jump
Station at http://www.optimagic.com/tutorial.html.

Also, you may want to check out The Programmable Logic Bookstore at
http://www.optimagic.com/books.html#VHDL.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------



ovilup wrote in message <01be0d93$78946fa0$4162e2c1@timteh.dnttm.ro>...
>Dear all,
>
>I am looking for a good documentation on programming FPGA's and
>ASIC's in VHDL. I have good aknowledges of VHDL, and I intend to learn
>more about FPGA's and ASIC's.
>
>Thank you.
>


Article: 13071
Subject: Re: placement&routing problems
From: Edward Moore <edmoore@edmoore.demon.co.uk>
Date: Sat, 14 Nov 1998 17:58:14 +0000
Links: << >>  << T >>  << A >>
This might make things a little clearer:

Take for example a pipelined KCM, similar to the one created by Xilinx
LOGIBLOX.

The KCM multiplies an input vector by a constant. The input and constant
can have parameterized widths and sign, but lets assume they are both
unsigned 16.

The KCM produces a partial product from each 4 bit slice of the input
using a lookup table. The LUT outputs are shifted as appropiate summed
by two adders. 

For simplicities sake lets say that RLOC column is 20 bits or 10 CLB's
tall. The placement could look something like this.
                        
                                X RLOC

Y RLOC    0           1           2           3           4
  0   *********   *********   *********   *********   *********
  1   *       *   *       *   *       *   *       *   *       *
  2   *       *   *       *   *       *   *       *   *       *
  3   *       *   *       *   *       *   *       *   *       *
  4   * LUT A *   * LUT B *   * LUT C *   * ADDER *   * ADDER *
  5   *       *   *       *   *       *   *  A+B  *   *  A+B  *
  6   *       *   *       *   *       *   *       *   *  + C  *
  7   *       *   *       *   *       *   *       *   *       *
  8   *       *   *       *   *       *   *       *   *       *
  9   *********   *********   *********   *********   *********

(All LUT's and adders are clocked. The input slice for LUT C would be
delayed by one clock to make things line up).

If the hierarchy only applied to the KCM, it would be passed a unique
U_SET name which would be used by all lower-level components.

The VHDL code would instantiate three LUT components, and two adder
components. Each would be passed the U_SET string, an X RLOC of 0, and a
Y RLOC of 0, 1, 2, 3, and 4, as well as vector widths, LUT values, adder
shifts etc. Perhaps the adder's would be made from an adder_tree
component which would sum any number of input vectors.

The LUT component would instantiate 20 ROM16X1 and 20 FD xilinx
primitives in a column starting at the supplied X and Y RLOC.

The adder component would similarly instantiate FMAP and FD primitives,
and FORCE_F1, EXAMINE_CI, and ADD_xx carry chain mnuemonics.

The lowest level primitive components would apply the RLOC and U_SET
attributes, which would appear in the XNF file.

If models of the Xilinx primitives are created, (some synthesis tools
supply them) the design can be simulated with no other steps.

A higher level entity could instantiate 4 KCM components, all in the
same U_SET. Each KCM would be passed the starting X and Y RLOC's,
ie (0, 0), (5, 0), (0, 10), and (5, 10).

The top level entity might not know how big each lower level KCM is, 
so it would first call a get_kcm_size function, passing it the
multiplier and multiplicand widths, and getting back the max X and Y
dimensions that a KCM with these parameters would use.

-- 
Edward Moore
Not officially speaking for Snell & Willcox Ltd
Article: 13072
Subject: Re: placement&routing problems
From: Edward Moore <edmoore@edmoore.demon.co.uk>
Date: Sat, 14 Nov 1998 18:17:32 +0000
Links: << >>  << T >>  << A >>
In article <uXibKAA2ScT2Ew9Z@edmoore.demon.co.uk>, Edward Moore
<edmoore@edmoore.demon.co.uk> writes
>This might make things a little clearer:

Probably not with the obvious mistake: for a 16 by 16 muliplty with 4
bit slices, there would be 4 LUT's and three adders, with no delay
neccesary on any LUT input. The example was based on a 12 by 12, but
then of course the LUT output widths would be 16 bits not 20. 

I must have finally cracked. I am now replying to my own postings.
-- 
Edward Moore
Article: 13073
Subject: Low Cost FPGA Development Tools
From: Hlebasko@t-online.de
Date: 14 Nov 1998 18:29:49 GMT
Links: << >>  << T >>  << A >>
I am looking for information for some low cost FPGA development tools for
learning.  I am trying to improve my "skill set" on my own and I can't
afford multiple thousand dollar tool sets.

Thanks.

Joseph Hlebasko


Article: 13074
Subject: Re: Software tool
From: APS <resp@associatedpro.com>
Date: Sat, 14 Nov 1998 15:12:23 -0500
Links: << >>  << T >>  << A >>
Check out the PeakVHDL suite at http://www.associatedpro.com It can handle all
the major FPGA vendors, has synthesis and simulation, and is a bit less money
than the ALDEC suite.

Ido Kleinman wrote:

> Dear all,
>
> I am looking for a good VHDL development (compiling, simulation, gate-level
> sim/FSM support, Testbench generator) software tool. I need it to have a
> comfortable interface to maxplus2 for exporting compiled designs for
> synthesis in Altera's devices.
> I've been looking around lately and I've evaluated Aldec's "Active-VHDL" and
> quite happy with it, but I have a slow internet connection, therefore,
> before I start downloading tens of megabytes again, I would like to know if
> there are any other compact software tools worth looking at...?
>
> Anyone got any experience with Aldec's tool?
> Are the big ones (Synopsys, Examplar..) worth the investment?
>
> --
>
>  Ido Kleinman.
>  kleinn@mail.biu.ac.il

--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/




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