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Messages from 14825

Article: 14825
Subject: Re: P&R times for Altera10K200E and Virtex
From: "Edwin Grigorian" <edwin.grigorian@jpl.nasa.gov>
Date: Thu, 18 Feb 1999 13:54:32 -0800
Links: << >>  << T >>  << A >>
I have a design that utilizes over 90% of the LCs and 12% of the memory of a
10K200EBC600-3 device.  I did have to enable register packing to fit the
design into this device and typical place and route times are around 25
hours.  It's being run on a Compaq P-II PC running Win95 with 256Megs of
RAM.  The design has 19 input and 15 output pins so it's nowhere close to
being pin-limited.  I have not yet been able to successfully route this
design as the memory segmentation (by-64 dualport RAM) appears to create
long delay paths which violate the setup and hold requirements.

Edwin Grigorian
JPL


edwinpark@my-dejanews.com wrote in message
<7af9cb$lhv$1@nnrp1.dejanews.com>...
>Does anyone have any P&R times for these two devices.  Also, could you post
>some info about the design (% utilization, # of registers, # I/Os, computer
>used to P&R, etc).
>
>I am going to start a design that needs many iterations and am very worried
>about P&R times.
>
>-Edwin
>
>-----------== Posted via Deja News, The Discussion Network ==----------
>http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own


Article: 14826
Subject: Re: P&R times for Altera10K200E and Virtex
From: "Edwin Grigorian" <edwin.grigorian@jpl.nasa.gov>
Date: Thu, 18 Feb 1999 14:07:19 -0800
Links: << >>  << T >>  << A >>
Forgot to mention below that the PCs CPU speed is 333MHz.

Edwin Grigorian
JPL


Edwin Grigorian wrote in message <7ai28e$r7o@netline.jpl.nasa.gov>...
>I have a design that utilizes over 90% of the LCs and 12% of the memory of
a
>10K200EBC600-3 device.  I did have to enable register packing to fit the
>design into this device and typical place and route times are around 25
>hours.  It's being run on a Compaq P-II PC running Win95 with 256Megs of
>RAM.  The design has 19 input and 15 output pins so it's nowhere close to
>being pin-limited.  I have not yet been able to successfully route this
>design as the memory segmentation (by-64 dualport RAM) appears to create
>long delay paths which violate the setup and hold requirements.
>
>Edwin Grigorian
>JPL
>
>
>edwinpark@my-dejanews.com wrote in message
><7af9cb$lhv$1@nnrp1.dejanews.com>...
>>Does anyone have any P&R times for these two devices.  Also, could you
post
>>some info about the design (% utilization, # of registers, # I/Os,
computer
>>used to P&R, etc).
>>
>>I am going to start a design that needs many iterations and am very
worried
>>about P&R times.
>>
>>-Edwin
>>
>>-----------== Posted via Deja News, The Discussion Network ==----------
>>http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own
>
>


Article: 14827
Subject: Re: Xilinx Foundation V1.5
From: Cameron Watt <cwatt@one.net.au>
Date: Fri, 19 Feb 1999 15:53:02 +1100
Links: << >>  << T >>  << A >>
I have been reliably informed (from Xilinx) that it will be available from
Prentice Hall Feb 28th. However the timing is always subject to change.

Cheers,

Cameron Watt.

EKC wrote:

> Does anyone here know when version 1.5 of the Xilinx student edition
> foundation package will be available? I had been told that it would be
> available by February 1st, however it is nowhere to be seen.
>
> Thanks,
> -EKC

Article: 14828
Subject: Xilinx Programming via a Processor
From: Rinzai Bell <bellr@r-systems.com>
Date: Thu, 18 Feb 1999 21:04:31 -0800
Links: << >>  << T >>  << A >>
Has any body seen tools to store Xilinx FPGA configuration files in the
uP's ROM/FLASH and the necessary code to initialize the FPGA's with the
code. This would allow for truly field up-gradable hardware!

Thanks,

RinziaJ. Bell

Article: 14829
Subject: multiple clock domain problem
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Fri, 19 Feb 1999 09:36:58 +0200
Links: << >>  << T >>  << A >>
I am using Xilinx M1.5 and target is XC40150XV/-0.9. We have a
local pipelining which has 2 stages and each stage is running at
12.5 MHz and 25 MHz respectively. 2nd stage is connected to an
internal Dual Port RAM. 12.5 MHz stage accepts one-shot pulses and
this block gives the pulses to 25 MHz stage.
     __________      _________
    |          |    |         |
    | Logic A  |    | Logic B |
--->| 12.5 MHz |--->| 25 MHz  |---> Dual Port RAM
    |__________|    |_________|

Functional simulations are as we expected, the pulses are on the
clock period and time as we want. But postlayout simulations show
that the pulse at the output 25 MHz logic only is always assigned
two clocks later.

I am using Verilog-XL, Synplify and Design Manager M1.5.
Synplify produces NCF file which only includes clock constraints
and we created UCF file which only includes pin constraints.
Design Manager reads the design and these files w/o any problem.
But postlayout Verilog netlist behaves weird as told above.

Post synthesis simulation is exactly the same as the functional.

If there are multiple clocks, is it enough to define clock constraints?
Shall we use special UCF commands to define multiple clock domain?

Utku
Article: 14830
Subject: Just Texting
From: htytus@shell1.iglou.com (Hul Tytus)
Date: 19 Feb 1999 05:22:19 -0500
Links: << >>  << T >>  << A >>
Just TextingNewsgroups: comp.arch.fpga
Article: 14831
Subject: just testing
From: htytus@shell1.iglou.com (Hul Tytus)
Date: 19 Feb 1999 05:27:24 -0500
Links: << >>  << T >>  << A >>
Just TextingThis is just a testPath: ix.netcom.com!news-peer.gip.net!news.gsl.net!gip.net!sunqbc.risq.qc.ca!torn!qcarh002.nortelnetworks.com!bcarh189.ca.nortel.com!bmerhc5e.ca.nortel.com!bcrkh13.ca.nortel.com!not-for-mail
Article: 14832
Subject: testing, just testing
From: ggg fff <htytus@erols.com>
Date: 19 Feb 1999 10:31:22 GMT
Links: << >>  << T >>  << A >>
just testing here

Article: 14833
Subject: Re: multiple clock domain problem
From: "Jamie Sanderson" <jamie@nortelnetworks.com>
Date: Fri, 19 Feb 1999 08:43:41 -0500
Links: << >>  << T >>  << A >>
This may be a foolish question, but what simulator are you using for
post-PAR? One thing to watch out for is how you define your clocks. For
example, I use ViewSim (Viewlogic) to simulate the timing-annotated EDIF
that M1 produces. If you just use the simple command-line interface to
generate clocks (e.g. clock 1 0), your signal transitions will occur at
exactly the clock transition time. That is obviously a violation of the
setup and hold times. While it may be fine for functional simulation, it
creates false results later. Instead, you need to use their waveform command
to generate a custom clock signal.

I would check that sort of situation to see if it applies to your simulator.
You may need to use some more advanced commands, or modify your testbench,
to ensure you meet setup and hold times.

If that isn't the problem, then all I can say if I follow the same flow you
do. I tend to put clock constraints into the UCF, but they're just redundant
to what Synplify produces. That seems to work fine.

Regards,
Jamie

Utku Ozcan wrote in message <36CD149A.2D172EBD@netas.com.tr>...
>Functional simulations are as we expected, the pulses are on the
>clock period and time as we want. But postlayout simulations show
>that the pulse at the output 25 MHz logic only is always assigned
>two clocks later.



Article: 14834
Subject: DPLL&ADPLL tutorials needed.
From: apodgorny@my-dejanews.com
Date: Fri, 19 Feb 1999 13:45:39 GMT
Links: << >>  << T >>  << A >>
Hi.
Could anybody tell where one can find some tutorials on DPLL and ADPLL.

Thanks.

With best regards,
Alexander M.Podgorny
E-Mail: apodgorny@my-dejanews.com

-----------== Posted via Deja News, The Discussion Network ==----------
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Article: 14835
Subject: Re: Xilinx Programming via a Processor
From: "Rudolf Mühlenbein" <rudolf.muehlenbein@gmx.de>
Date: Fri, 19 Feb 1999 15:31:11 +0100
Links: << >>  << T >>  << A >>
connect a 8 bit flash PROM to the Xilinx FPGA, see the Xilinx data-book. Do
prom a bootstrap in this flash that implement a communication port to your
uP, seriell or paralell. Do implement an interface to read and write to the
flash. Do implement a software restart. This is all avalible on XC4000.
Write this bootstrap at the 2. sector of the flash. The 1. sector is empty.
If you will up-grade the application, write this in the 1. sector and make a
soft reset. Then the FPGA boot the 1. sector application. This application
must include the elements from the bootstrap.

I self have made this functions with XC4005 and AMD flash PROMs. We can
update the application in the low level IO-hardware via remote controll
world wide.

best regards,
Rudolf Muehlenbein

Rinzai Bell schrieb in Nachricht <36CCF0DF.F49877D2@r-systems.com>...
>Has any body seen tools to store Xilinx FPGA configuration files in the
>uP's ROM/FLASH and the necessary code to initialize the FPGA's with the
>code. This would allow for truly field up-gradable hardware!
>
>Thanks,
>
>RinziaJ. Bell
>


Article: 14836
Subject: Power estimation on FLEX10K applications
From: Andres David Garcia Garcia <garcia@elec.enst.fr>
Date: Fri, 19 Feb 1999 15:40:26 +0100
Links: << >>  << T >>  << A >>


Somebody sent me an example of an applications that uses
severals FLEX10K, The estimation using the Altera's Data Book
is wrong (that doesn't surprise me), unfortunatelly I lost this e-mail
This mail was sent to Altera's hot line also, and it contains some
usefull data, ie average toggling rate, Frequency and percentage of
used ressources, please, send me this example again because it could
validate the model that we have obtained based on reel measurements.

The model porpose five elements and we've indentified the percentage
of power for each one, the most critical elements is the interconnect,
maybe VPR could be a solution, if time delay is optimize, power will
be optimized also.

thank you



Article: 14837
Subject: Re: P&R times for Altera10K200E and Virtex
From: Andres David Garcia Garcia <garcia@elec.enst.fr>
Date: Fri, 19 Feb 1999 15:45:05 +0100
Links: << >>  << T >>  << A >>


Good morning,

I'm looking for an engineer that is working in applications using FLEX10K as you
do.
this guy sent me a mail to indicates me some characteristics of his system to
estimate
the power consumption, I losted this message because a network error, He has
problems
to obtain some information about his desing like you, and I think that this
engineer is you,
if don't, I'm sorry to disturb you.

Thank you





Article: 14838
Subject: Jobs in Silicon DSP IP - any takers?
From: idr@iss-dsp.com
Date: Fri, 19 Feb 1999 15:52:18 GMT
Links: << >>  << T >>  << A >>
Interested in a job in DSP Silicon IP,
then have a look at

http://www.iss-dsp.com/job.htm

NOTE: Strictly no agencies!!!!

-----------== Posted via Deja News, The Discussion Network ==----------
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Article: 14839
Subject: Re: P&R times for Altera10K200E and Virtex
From: Jamie Lokier <spamfilter.feb1999@tantalophile.demon.co.uk>
Date: 19 Feb 1999 15:55:26 +0000
Links: << >>  << T >>  << A >>
I've been doing P&R profiling on a 10K50GC403-3 recently.  I varied the
size of a register FIFO in part of a larger (complex) design, making the
LC utilisation range from 62% to 99%.  P&R is using Maxplus2 9.11.  A
program is coded in AHDL, and an equivalent in Handel-C.

One of the most interesting results is that turning off your clock
frequency constraint is often a big win.  Compilation is much faster,
and sometimes gives a better fit.

Some nets will fail to fit with a frequency constraint, and fit just
fine without one.  The failure is often a fitting failure (can't find
LCs or Pins), not a timing constraint failure.  When those nets are
fitted without a frequency constraint, they fit fine and the max
frequency is suitably fast after all!  Sometimes the resulting circuit
will even run at a higher frequency than with the constraint.

If your circuit is parameterised (such as mine with the FIFO length), it
is quicker to do several compiles without a frequency constraint and
pick the best parameter, than it is to pick one parameter and see if it
fits.  You are also likely to get a higher operating frequency this way.
(See table below -- this method gets 17.30MHz which is higher than the
best I get with a frequency constraint).

And there's the thing above, that some nets won't fit with a frequency
constraint even though they fit fine and run at the desired frequency
without the constraint.

The point is, that because compilation is _so_ much faster without a
frequency constraint, you have time to experiment with the logic.

Example times, Pentium II 300MHz, 128MB RAM, Maxplus2 9.11,
10K50GC403-3, program written in Handel-C, no cliques etc., no timing
constraints other than fmax:

61% LCs, fmax = 16.5MHz:	286.0 minutes (4.75 hours)	freq = 16.61MHz
75% LCs, fmax = 16.5MHz:	362.5 minutes (6 hours)		freq = 14.53MHz
77% LCs, fmax = 16.5MHz:	no fit (routing failure)

61% LCs, no fmax:		  3.5 minutes			freq = 16.80Mhz
75% LCs, no fmax:		  8.3 minutes			freq = 16.47MHz
77% LCs, no fmax:		  7.7 minutes			freq = 17.30Mhz
92% LCs, no fmax:		 28.3 minutes			freq = 16.50MHz
93% LCs, no fmax:		 12.3 minutes			freq = 14.28MHz

Note that fitting times, and max frequency after fitting, vary
considerably as the net is changed.  (In this case, by simple varying a
FIFO length).  For any given combination of parameters and netlist,
Maxplus2 produces deterministic output.  That is, rerunning the P&R will
give you the same output, and take about the same time.  So there's no
point trying several times to get a better fit.

I was also very surprised to find I can get 99% LC utilisation compiled
in <1 hour using netlists written in AHDL, using cliques.  Same program
as above.  Maxplus2 9.11 seems to be better than 8.3 for maximum
utilisation.

You can have other, individual timing constraints -- they slow down the
compiler too, but not as much as a global frequency constraint.  If
you're using timing constraints for I/O signals, I'd advise using the
Fast I/O logic option instead for deterministic I/O timing.  The fitter
isn't slowed down by that.  When to use Fast I/O, and which flip-flops to
use it on for bidirectional & tri-state signals... well, that I'll write
about another day.

The above table was produced using Fast I/O logic options in all the
right places, and no timing constraints at all.  There were no cliques.

An equivalent program in AHDL, using cliques and a few individual I/O
timing constraints takes between 20 minutes and 300 minutes to fit,
according to your luck at the time.  Removing the cliques makes it take
40 minutes upwards.  So it is still better to avoid any timing
constraints at all.

Enjoy,
-- Jamie
Article: 14840
Subject: US-CA jobs/ASIC-SCSI engineer
From: reginaht@aol.com (ReginaHT)
Date: 19 Feb 1999 16:13:24 GMT
Links: << >>  << T >>  << A >>
We are looking for ASIC engineers with
SCSI and/or Fibre Channel knowledge.
Hard disk technology knowledge a plus.
Position is in Irvine, California. Senior and staff level.

US work visa provided.
Pls contact us for detailed job descriprion.
Regina
Article: 14841
Subject: Xilinx config from MC68332
From: John Larkin <jjlarkin@highlandtechnology.com>
Date: Fri, 19 Feb 1999 10:08:14 -0800
Links: << >>  << T >>  << A >>
Hi,

in an earlier thread, there was discussion of how to configure Xilinx
FPGAs from a microprocessor. I have recently completed a product which
uses a Motorola MC68332 processor and two Xilinx 4010XLs, with a single
EPROM holding the uP code and the Xilinx config tables. We had, of
course, the usual agonizing difficulties getting this to work, so I'm
offering it to others so that the sum total of worldwide suffering may
be slightly reduced.

I have zipped up a summary of the project, including...

68332 assembly source code
schematic fragments
ROM image builder program
S28 file unbuilder program
sundry notes

I will e-mail this to anybody who is interested; the files are
accompanied by a not-too-onerous copyright and usage agreement that
allows use by the recipient provided that our copyright notice is
retained and any improvements be forewarded to us for future release. If
you want to contribute to the Highland Engineers Doughnut Fund, or send
dark Swiss cholcolates, that's OK too.

John

--
******************************************************************

John Larkin, President           phone 415 753-5814   fax 753-3301
Highland Technology, Inc
320 Judah Street                 jjlarkin@highlandtechnology.com
San Francisco, CA 94122          http://www.highlandtechnology.com


Article: 14842
Subject: Re: multiple clock domain problem
From: frannhagen@my-dejanews.com
Date: Fri, 19 Feb 1999 18:46:18 GMT
Links: << >>  << T >>  << A >>
In article <36CD149A.2D172EBD@netas.com.tr>,
  Utku Ozcan <ozcan@netas.com.tr> wrote:

> Functional simulations are as we expected, the pulses are on the
> clock period and time as we want. But postlayout simulations show
> that the pulse at the output 25 MHz logic only is always assigned
> two clocks later.

I might be totally wrong but when I have dealt with multiple clock
domain designs I have needed to be very careful when defining the
clocks in the functional simulation to match the reality. Depending on
how you create the clocks and how you use them you might need to add
a small phase differance in the functional simulation to avoid that data
is clocked faster or slower between the two domains. This has been the
case for me when designing in VHDL and creating the clocks seperatly.

I find it tricky sometimes to deal with the unpredictable process execution
in VHDL. Adding a small phase differance (i.e. 1ns) could help. If your
flow of data is in one direction (i.e. 12.5 -> 25) only this works.

So you might want to go back to your functional simulation and verify
that there isn't any "clocking" problem. But I'm not sure how it works in
Verilog.

Regards,

Mats Frannhagen

-----------== Posted via Deja News, The Discussion Network ==----------
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Article: 14843
Subject: Inferring IOFFs with FPGA Express 3.x and Foundation 1.5i
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Fri, 19 Feb 1999 12:32:13 -0700
Links: << >>  << T >>  << A >>
I think Xilinx and/or Synopsys broke something that used to work.

I'm trying to finish a small new design (XC4005E, if you must know...) and
I'm using FPGA Express v3.1 (brand new) and F1.5i w/Service Pack 1
installed.  (I had the same problem without the service pack and the
previous version of FPGA Express.)

What's happening is that FPGA Express is not inferring IOFFs properly.  I
have a process in my top-level module that uses the clock's falling edge to
register the input (the input in question is driven by a signal clocked on
the same clock's rising edge on another board), and that register should be
in an input flip flop.  That flop's output drives another FF which is
clocked on the rising edge.  The code looks like this, where inpin_fe and
inpin_re are signals and inpin is an input port:

    fe : process (sysclk)
    begin
        if sysclk'event and sysclk = '0' then
            inpin_fe <= inpin;
        end if;
    end process fe;

    re : process (sysclk, mreset)
    begin
        if mreset = '1' then
            inpin_re <= '0';
        elsif sysclk'event and sysclk = '1' then
            inpin_re <= inpin_fe;
        end if;
    end process re;

I didn't put a reset clause in the fe process because some Xilinx
documentation I've read says that you shouldn't use the reset if you want to
infer an input FF.  This is probably because FFs in the 4000E IOBs don't
have asynch set/reset inputs.

Now, I know this worked in F1.4 because I looked through the .XNFs of a
couple of designs I did with 1.4 - using the same code as above - and sure
enough, there are the INFFs.

I've tried telling the FPGA Express constraint editor spreadsheet that I
REALLY wanted I/O registers (even though "Use I/O Reg defaults to "true," I
specified "true" in the appropriate places); that made no difference -
regular CLB DFFs are used.

I guess I could hand-instantiate INFFs where needed, but that seems silly,
especially because this used to work.

Has anyone else noticed this little problem, and is there a fix (short of
going back to 1.4)?

-- andy

PS: In Synopsys's favor, they've managed to fix an annoying "feature" in
FPGA Express 3.1; namely, it handles false paths through tristate pins much
better.  Previously, if you had a tristateable pin with input and output
registers, FPGA Express would give you bogus timing from the output flop to
the input flop through the pin - the false path - and of course the timing
would be bleeding red.  In 3.1, I believe it's smart enough to ignore that
path when it does its thing.

------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

Don't waste apostrophes!  The plural of the acronym for "personal computers"
is PCs, NOT PC's.


Article: 14844
Subject: Re: P&R times for Altera10K200E and Virtex
From: Ray Andraka <randraka@ids.net>
Date: Fri, 19 Feb 1999 15:41:48 -0500
Links: << >>  << T >>  << A >>
Those are dismal clock rates for a 10K-3.  Typically arithmetic stuff slows it
down, but even there you should get about 40 MHz without cliques with 20 bit carry
chains in the logic.  Sounds like you have many layers of combinatorial stuff
between the registers.  Perhaps you should spend more time on designing to the
architecture than playing with the constraints.

Jamie Lokier wrote:

> I've been doing P&R profiling on a 10K50GC403-3 recently.  I varied the
> size of a register FIFO in part of a larger (complex) design, making the
> LC utilisation range from 62% to 99%.  P&R is using Maxplus2 9.11.  A
> program is coded in AHDL, and an equivalent in Handel-C.
>
> One of the most interesting results is that turning off your clock
> frequency constraint is often a big win.  Compilation is much faster,
> and sometimes gives a better fit.
>
> Some nets will fail to fit with a frequency constraint, and fit just
> fine without one.  The failure is often a fitting failure (can't find
> LCs or Pins), not a timing constraint failure.  When those nets are
> fitted without a frequency constraint, they fit fine and the max
> frequency is suitably fast after all!  Sometimes the resulting circuit
> will even run at a higher frequency than with the constraint.
>
> If your circuit is parameterised (such as mine with the FIFO length), it
> is quicker to do several compiles without a frequency constraint and
> pick the best parameter, than it is to pick one parameter and see if it
> fits.  You are also likely to get a higher operating frequency this way.
> (See table below -- this method gets 17.30MHz which is higher than the
> best I get with a frequency constraint).
>
> And there's the thing above, that some nets won't fit with a frequency
> constraint even though they fit fine and run at the desired frequency
> without the constraint.
>
> The point is, that because compilation is _so_ much faster without a
> frequency constraint, you have time to experiment with the logic.
>
> Example times, Pentium II 300MHz, 128MB RAM, Maxplus2 9.11,
> 10K50GC403-3, program written in Handel-C, no cliques etc., no timing
> constraints other than fmax:
>
> 61% LCs, fmax = 16.5MHz:        286.0 minutes (4.75 hours)      freq = 16.61MHz
> 75% LCs, fmax = 16.5MHz:        362.5 minutes (6 hours)         freq = 14.53MHz
> 77% LCs, fmax = 16.5MHz:        no fit (routing failure)
>
> 61% LCs, no fmax:                 3.5 minutes                   freq = 16.80Mhz
> 75% LCs, no fmax:                 8.3 minutes                   freq = 16.47MHz
> 77% LCs, no fmax:                 7.7 minutes                   freq = 17.30Mhz
> 92% LCs, no fmax:                28.3 minutes                   freq = 16.50MHz
> 93% LCs, no fmax:                12.3 minutes                   freq = 14.28MHz
>
> Note that fitting times, and max frequency after fitting, vary
> considerably as the net is changed.  (In this case, by simple varying a
> FIFO length).  For any given combination of parameters and netlist,
> Maxplus2 produces deterministic output.  That is, rerunning the P&R will
> give you the same output, and take about the same time.  So there's no
> point trying several times to get a better fit.
>
> I was also very surprised to find I can get 99% LC utilisation compiled
> in <1 hour using netlists written in AHDL, using cliques.  Same program
> as above.  Maxplus2 9.11 seems to be better than 8.3 for maximum
> utilisation.
>
> You can have other, individual timing constraints -- they slow down the
> compiler too, but not as much as a global frequency constraint.  If
> you're using timing constraints for I/O signals, I'd advise using the
> Fast I/O logic option instead for deterministic I/O timing.  The fitter
> isn't slowed down by that.  When to use Fast I/O, and which flip-flops to
> use it on for bidirectional & tri-state signals... well, that I'll write
> about another day.
>
> The above table was produced using Fast I/O logic options in all the
> right places, and no timing constraints at all.  There were no cliques.
>
> An equivalent program in AHDL, using cliques and a few individual I/O
> timing constraints takes between 20 minutes and 300 minutes to fit,
> according to your luck at the time.  Removing the cliques makes it take
> 40 minutes upwards.  So it is still better to avoid any timing
> constraints at all.
>
> Enjoy,
> -- Jamie



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 14845
Subject: Final CP Reconfigurable Technology: FPGAs for Computing and Applications
From: John Schewel <jas@vcc.com>
Date: Fri, 19 Feb 1999 13:58:03 -0800
Links: << >>  << T >>  << A >>


ABSTRACT SUBMISSION DATE EXTENDED TO MARCH 10,1999


CALL FOR PAPERS  

SPIE's International Symposium on Voice, Video & Data Communications
19-22 Septmber 1999 - Hynes Convention Center -- Boston Massachusetts
USA

Reconfigurable Technology: FPGAs for Computing and Applications (VV03)

                         This is the Fourth Year of this Conference

On-site Proceedings.  Abstracts for this conference are due by 10 March
1999. Manuscripts are due by 28 June 1999.

Conference Chairs: John Schewel, Virtual Computer Corp.; Peter M.
Athanas,
Virginia Polytechnic Institute and State Univ.; Steven A. Guccione,
Xilinx
Inc.; Stefan Ludwig, Compaq Computer Corp.; John T. McHenry, National
Security Agency

Many systems engineers are using reconfigurable device technologies,
such
as Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic
Devices (CPLDs), to overcome computation and product development
bottlenecks.  In recent years, these devices have been incorporated into
computing systems for the purpose of providing a reconfigurable
environment
for high-performance applications.  This conference focuses on two areas
of
reconfigurable technology:

                1) systems, tools and techniques
                2) high-performance applications

Today's reconfigurable devices can be used for datapath and data
processing
applications, as well as for general logic replacement.Processors built
from reconfigurable logic devices are being applied to a wide range of
computationally-intensive tasks. 

The conference will present papers that illustrate applications and
techniques for using reconfigurable technology in both the design cycle
and
in production systems.  Papers relating to the following areas are
solicited:

* digital and analog reconfigurable components
* programming tools and methodologies for configurable computing systems 
* applications and platforms utilizing configurable technology for: 
        - hardware/software codesign 
        - rapid product development 
        - high-performance computing
        - image, signal, and communication processing 
          intelligent systems, robotics, and evolvable algorithms


Abstract Due Date: 8 February 1999
Manuscript Due Date Date: 28 June 1999

Abstract Information Required:
1. Submit To: VV03 Schewel ET AL
2. Abstract Title
3. Author Listing (Principle Author First)
    First Name, Last NAme, Affliation, Mailing Address,
    Telephone, Fax, Email
4. Presentation: "Oral" or "Poster"
5. Abstract Text (Aproximately 250 Words) English
6. Keywords: Five Max.
7. Brief Bio of Principle Author

You may submit Abstracts in ONE of the following options:

SPIE WEB --- Form to be found on SPIE Website
                         www.spie.org/forms/pe99_submission_form.html
EMAIL      --- To: abstracts@spie.org ; in ASCII Text Only
                         Subject:  VV03, Schewel
MAIL         --- Three copies of abstract to: 
	         Voice, Video & Data Communications
	         SPIE PO Box 10, Bellingham WA 98227-0010 USA
                        or Shipping Address / 1000 20th St. Bellingham
WA 98225 USA
FAX           --- one copy top SPIE at   (1) 360-647-1445


ALSO SEE: http://www.spie.org/web/meetings/calls/pe99/confs/VV03.html
               
-- 

Best Regards,
John Schewel, VP Marketing & Sales
Virtual Computer Corp.
http://www.vcc.com


Article: 14846
Subject: Re: Inferring IOFFs with FPGA Express 3.x and Foundation 1.5i
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Fri, 19 Feb 1999 15:09:50 -0700
Links: << >>  << T >>  << A >>
Andy Peters wrote in message <7akeat$kq5$1@noao.tuc.noao.edu>...
>I think Xilinx and/or Synopsys broke something that used to work.

[snip]

Call me a liar.

It's working now.  Not sure why.

The new schematic viewer in FPGA Express is nice; it shows you what the
synthesizer creates.

Now if I could only get the mapper to run without having to reinstall NT...

-- andy
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

Don't waste apostrophes!  The plural of the acronym for "personal computers"
is PCs, NOT PC's.



Article: 14847
Subject: Re: four signals into array?
From: jamie morken <foster@uvic.ca>
Date: Fri, 19 Feb 1999 14:51:01 -0800
Links: << >>  << T >>  << A >>

Thanks for the help, now on to my next question..   :)

Jamie Morken

Article: 14848
Subject: variable assignment in process or outside of process
From: jamie morken <foster@uvic.ca>
Date: Fri, 19 Feb 1999 15:09:35 -0800
Links: << >>  << T >>  << A >>
Hi all,

I am modelling a processor and I have a processes which add, subtract,
increment PC etc - should I set flags (ie. do_add, do_subt, inc_pc) in
the process which then cause code outside of the process to add or
subtract (CASE1) or should I add, subtract, inc_pc inside the process
(CASE 2)?  Thanks for your time.

Jamie Morken

CASE 1:  flags in process
--------------------------

next_pc <=  curr_pc + '1' WHEN inc_pc = '1' ELSE

               --or else don't change the PC
              curr_pc;

PROCESS (fetch_ready)
BEGIN

 IF  (fetch_ready) THEN
  inc_pc <= '1'; -- inc PC control (next_pc <= curr_pc)

 ELSE

  inc_pc <= '0';

 END IF;

END PROCESS;


CASE 2: All work done in process
-----------------------------------

PROCESS (fetch_ready)
BEGIN

 IF  (fetch_ready) THEN
  next_pc <= curr_pc + '1';

 ELSE

  next_pc <= curr_pc;

 END IF;

END PROCESS;


Article: 14849
Subject: Anyone done any GPS designs?
From: thor@sm.luth.se (Jonas Thor)
Date: Sat, 20 Feb 1999 00:24:08 GMT
Links: << >>  << T >>  << A >>
Hello,

I am working on my master thesis and the main part with the thesis is
to implement a multichannel GPS digital correlator in a Xilinx FPGA
(XC4036XL or smaller). The correlator does the usual CDMA stuff,
downmixing, despreading, acummulation etc. We have a PCI FPGA board
(Wild-One) that will serve as a protyping platform.

I am wondering if anyone has done some similar work in a FPGA or if
you have some references about such work?

Thanks!

Jonas Thor
Lulea Technical University
Sweden


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