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Messages from 14875

Article: 14875
Subject: Re: connecting 2 FPGA
From: "Steve" <reply.through.newsgroup@paranoid.com>
Date: Mon, 22 Feb 1999 15:18:19 GMT
Links: << >>  << T >>  << A >>

>Problems are as follows :
>=========================
>when I test both chip separately, they works fine. However, if I connect
>them together using 2 flat cables. There are lots of glitches appear on
>the clocks. I suspect that the glithes are induced in the flat cables but
>it is only part of the story.



How far apart are the two chips?  How have you tried to connect them?
ie are you using alternate grounds on your ribbon cable?
    are you providing series terminations at the source???


>I use a logic analyzer to look at at A, A', B & C, find out that glitches
>appear on A', B & C but not in A. However, B and C can no longer keep
>there shape.

Make sure your ground is referenced as closely as possible to the receiving
chip.  The signal can look much different at different points on the cable,
but all you really care about is what the receiving chip "sees" across its
TWO (ground is very important) input pins.


Steve




Article: 14876
Subject: Houston - Need FPGA Work
From: "Marty Stan" <samaritan@staffing.net>
Date: Mon, 22 Feb 1999 11:28:07 -0500
Links: << >>  << T >>  << A >>
Does anyone know any companies in Houston, TX that need FPGA designers?

Background:
Extensive designe and board development experience with FPGA designs,
specializing in Xilinx FPGAs. Specialized in data flow and high-speed
digital design. Extremely experienced with optimizing Xilinx placement and
routing for high speed data flow.

Schematic and VHDL based design entry, OrCad, ModelTech simulation, Xilinx
Alliance and Foundation packages, Exemplar synthesis, Altera FPGAs, more!

Marty Stan




Article: 14877
Subject: Re: Eval Activ-VHDL only for 30 day :(
From: "Gary Seely" <garys@aldec.com>
Date: Mon, 22 Feb 1999 17:14:15 GMT
Links: << >>  << T >>  << A >>
Aldec has an excellent University Program providing free software to the
school.  For details see www.aldec.com.  Continue to check the website from
time to time.  A student version is being developed.
Krzycho wrote in message <36D03CAB.B84AC6E5@friko3.onet.pl>...
>Hello
>I'm an electronics and telecomunications student. I'm interested in VHDL
>and I've got an evaluation version of Activ-VHDL (for Windows) tools
>(from Aldec www).


Article: 14878
Subject: Problem with xilinx M1
From: "Sergio A. Cuenca Asensi" <sergio@dtic.ua.es>
Date: Mon, 22 Feb 1999 18:55:04 +0100
Links: << >>  << T >>  << A >>
Hello,
I am trying to implement a tiny circuit with a bidirectional data bus
(8bits) and a addres bus (16 bits) connected to a external SRAM memory.
In the implementation stage the M1 tool stop in the Map process and it
produces the follow error:

Design Information
------------------
Command Line   : map -p xc4010xl-09-pc84 -o map.ncd ../xc4000xl.ngd
rwmem.pcf
Target Device  : x4010xl
Target Package : pc84
Target Speed   : -09
Mapper Version : xc4000xl -- M1.4.12p
Mapped Date    : Mon Feb 22 17:48:48 1999

Design Summary
--------------
   Number of errors:        1
   Number of warnings:      5
   Number of CLBs:             42 out of   400   10%
      CLB Flip Flops:      46
      CLB Latches:          0
      4 input LUTs:        79
      3 input LUTs:         3 (2 used as route-throughs)
   Number of bonded IOBs:      39 out of    63   61%
      IOB Flops:            0
      IOB Latches:          0
   Number of BUFGs:             1 out of     8   12%
   Number of BUFGLSs:           4 out of     8   50%
   Number of RPM macros:        3
   Number of STARTUPs:          3
Total equivalent gate count for design: 1013
Additional JTAG gate count for IOBs:    1872


Section 1 - Errors
------------------
ERROR:x4kma:253 - The design is too large for the given device and
package.
   Please check the Design Summary section to see which resource
requirement for
   your design exceeds the resources available in the device.


NOTE: An NCD file will still be generated to allow you to examine the
mapped
   design.  This file is intended for evaluation use only, and will not
process
   successfully though PAR.  The mapped NCD file can be used to evaluate
how the
   design's logic has been mapped into FPGA logic resources.  It can
also be
   used to analyze preliminary, logic-level (pre-route) timing with one
of the
   Xilinx static timing analysis tools (TRCE or Timing Analyzer).

I donīt understand what resouce is overcome, any idea?
TIA

===================================================================
Sergio A. Cuenca Asensi
Dept. Tecnologia Informatica y Computacion (TIC)
Escuela Politecnica Superior, Campus de San Vicente
Universidad de Alicante
Ap. Correos 99, E-03080 ALICANTE
ESPAŅA (SPAIN)
email   : sergio@dtic.ua.es
Phone : +34 96 590 39 34
Fax     : +34 96 590 39 02
===================================================================


Article: 14879
Subject: Re: Inferring IOFFs with FPGA Express 3.x and Foundation 1.5i
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Mon, 22 Feb 1999 12:28:36 -0700
Links: << >>  << T >>  << A >>
Andy Peters wrote in message <7aknih$ebj$1@noao.tuc.noao.edu>...

Replying to myself again:

>>I think Xilinx and/or Synopsys broke something that used to work.
>
>[snip]
>
>Call me a liar.
>
>It's working now.  Not sure why.


I got a helpful note from a Synopsys person who wishes to remain anonymous,
and it appears my question has been answered:

------------------------------------------------------------------------
I saw your post on the News group and I'd like to help you resolve
the problem you are having. The problem comes from minor mismatch in the
documentation:

>> you shouldn't use the reset if you want to infer an input FF.

Should have really said:

>> you absolutely have to always use the reset (or set) if you want
>> the GSR (STARTUP) to be inferred and/or the IO register to be used!

Here's how FE thinks:

- if there is a flop with no set/reset in the design, I'm not going to infer
  the GSR (Global Set/Reset)

- if there is no GSR in the design, I'm not going to infer IO flops, because
  IO flops can only be set/reset by GSR.

In summary: no GSR => no IO flop!

Not describing a reset for a flop is a design mistake for both synthesis and
simulation (and for the final design). Please ignore what the documentation
says.

You can try it: if you are using the same set/reset all over the chip -> the
GSR will be infered and the IO flop as well...
-------------------------------------------------------------------------

What happened was that I forgot to instantiate the STARTUP block in my
top-level module code.  The code, however, does have reset clauses for all
of the flipflops.  However, FPGA Express was giving me a weird complaint:

Dpm : Warning: No global set / reset (GSR) net could be used in the design
because there is not a unique net that sets or resets all the sequential
cells. (FE-GSRMAP-5)

In this case, FPGA Express didn't use IOFFs; they're all in the CLBs.  It's
weird because EVERY flipflop DOES have the SAME reset signal going to it.  I
 wonder if this is a function of the design being hierarchical?

OK, instantiating the STARTUP fixes that warning, *and* now puts the input
flipflops into the IOBs, but introduces a new (and conflicting!) warning:

Dpm : The net 'idbxctrl-Optimized/mreset' had an implicit connection to the
on-chip global set / reset (GSR) net.  This connection has been made
explicit.  (FE-GSRMAP-9)

mreset is the reset signal.  Again, no change other than instantiating
STARTUP.

So, if you explicitly instantiate the STARTUP, the flipflops get put into
IOBs and Bob's your uncle.  If you don't explicitly instantiate the STARTUP,
the flops are put into CLBs.  This explains why my other designs had the FFs
in the IOBs; the STARTUP was used in those designs.

I think this would be more fun if all I did was FPGA design, but I really
have to check this PCB artwork today and I've been putting it off...


-- andy
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

Don't waste apostrophes!  The plural of the acronym for "personal computers"
is PCs, NOT PC's.



Article: 14880
Subject: Re: virtex vs apex ?
From: Nick <"nick[nospam]hartl"@earthlink.net>
Date: Mon, 22 Feb 1999 16:32:16 -0600
Links: << >>  << T >>  << A >>
One you can buy one, you can read some nice glossy prints about.

Have FUN!!
Nick

muzo wrote:

> hi,
> has anyone done any comparative analysis of these two news families ? Would you
> like to share ?
>
> muzo
>
> Verilog, ASIC/FPGA and NT Driver Development Consulting (remove nospam from email)


Article: 14881
Subject: Re: Altera freecore library ?
From: "Frank A. Vorstenbosch" <frank@falstaff.demon.co.uk>
Date: Mon, 22 Feb 1999 23:16:47 +0000
Links: << >>  << T >>  << A >>
Rune Baeverrud wrote:
> 
> Hello Steven,  Hello All,
> 
> I'm still with you :)
> 
> Actually - I left my old company to start working with Xilinx. It's obvious
> that I cannot actively support Altera anymore.

Hmmm,

How about porting the freecore stuff to Xilinx, then?  Or Verilog?

Frank
------------------------------------------------------------------------
Frank A. Vorstenbosch    <SPAM_ACCEPT="NONE">   Mobile:  +44-976-430 569
Wimbledon, London SW19                          Home:   +44-181-544 1865
frank@falstaff.demon.co.uk                      Office: +44-181-636 3391
Article: 14882
Subject: Re: Inferring IOFFs with FPGA Express 3.x and Foundation 1.5i
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Mon, 22 Feb 1999 16:59:49 -0700
Links: << >>  << T >>  << A >>
Andy Peters wrote in message <7asb82$7t8$1@noao.tuc.noao.edu>...

One more time for the world:

Ooops, I missed a reset on a single flipflop in one of my VHDL source files.

When ALL flipflops have the SAME reset line, Foundation Express will infer
the STARTUP (hence, GSR) as well as putting any flop that could be in an IOB
into an IOB.

Quite simple, really!

Good luck out there.


-- a
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

Don't waste apostrophes!  The plural of the acronym for "personal computers"
is PCs, NOT PC's.



Article: 14883
Subject: High Fanout Signals
From: Khaled benkrid <k.benkrid@qub.ac.uk>
Date: Tue, 23 Feb 1999 04:33:04 +0000
Links: << >>  << T >>  << A >>
Hi All,

I am implemeting shift registers in Xilinx 4kE using a LFSR counter and
Synchronous RAMs. I need a big shift (256*16 bits) which requires 128
CLBs for the RAMs. I need high fanout signals to address the RAM's from
the counter outputs in order to get high speed. What is the best
solution ( I am thinking about using BUFG to derive these signals).  Any
ideas????.

Cheers.

Article: 14884
Subject: Re: Xilinx/VHDL query - two clocks in one CLB
From: SimonBacon@NOTtile.demon.co.uk (Simon)
Date: Tue, 23 Feb 99 04:33:45 GMT
Links: << >>  << T >>  << A >>
Concerning using an inverted clock for just one of the FFs in a
Xilinx CLB, evan wrote, inter alia, as follows:

> this is possible in principle - there are two separate configuration
> bits, one for each clock (try it in EPIC - you can change them
> individually).
> 
> hi simon - are you sure that this can be done with a schematic (have
> you tried it)? my guess is that this can be done with XNF, but not
> with EDIF, so the first thing to do would be to try this with XNF
> output from your synthesiser.

I have only tried the schematic route with the XACT tools, but in that
case it works OK.  If I use the FD_1 part, as another poster suggested,
XNFMERGE brings in the following FD_1.XNF file

  LCANET, 6
  PROG, INF2XNF, 5.2.2, "Created from: fd_1.inf, Created time: 1999/02/23 03:37:07"
  PART, 4005EPC84
  PWR, 0, $U2_G,
  PWR, 1, $U1_P,
  SYM, U3, INV, SCHNM=INV, LIBVER=2.0.0
  PIN, I, I, C
  PIN, O, O, CB
  END
  SYM, U4, DFF, SCHNM=FDCE, LIBVER=2.0.0, INIT=R, RLOC=R0C0
  PIN, CE, I, $U1_P
  PIN, D, I, D
  PIN, Q, O, Q
  PIN, C, I, CB
  PIN, CLR, I, $U2_G
  END
  EOF

As you can see, the clock pin is inverted via a separate net which is
sourced by an inverter.  As you might expect, this inverter survives
XNFMERGE, but is absorbed in XNFPREP, after which the XTF file
drives the clock pin with "PIN, C, I, C, , INV".  PPR then has no
problems with the XTF file and pairs this flip-flop with a companion
flip-flop which is clocked with "PIN, C, I, C".

Naturally enought, this reduction is also exactly what we see if I use
an explicit FD and inverter in a schematic.

> my reasoning is:
> 
> 1) an EDIF netlist, from any source, would have different names for
> the two clock nets.
> 
> 2) an XNF netlist, i think, contains a lot less naming information,
> and so a single signal could source both nets.
> 
> if this is the case, then the problem is actually with the EDIF-input
> option on the mapper, and so this would be a problem for xilinx.

I think this is essentially correct.  The EDIF output from VHDL looks
fundamentally like the scrap of XNF reproduced above.  I would expect
that EDIF output from a schematic would look similar.  There is no way of
knowing (is there?) what is inside the NGD file which NGDBUILD sends
to MAP, but it looks as if MAP does not carry out the reduction which
is inside XNFPREP.

I will run a test case with XNF->MAP, but this is not a good solution
because XNF does not carry along all the attributes which we can attach
to EDIF files.  And XNF is under a death sentence.

So, unless someone has a better idea, the best flow is to generate
(in VHDL or in schematic) two flip-flops clocked on the rising edge,
run the (XNF or) EDIF through the tools, then fire up EPIC and flip
one of the clock polarity bits.  Always taking care to choose the
correct FF.

--
Simon


Article: 14885
Subject: Re: Problem with xilinx M1
From: fliptron@netcom.com (Philip Freidin)
Date: Tue, 23 Feb 1999 04:54:00 GMT
Links: << >>  << T >>  << A >>

How many tristateable buffers are you using inside your design?
Ummmm, Startups = 3 seems a little on the high side. 

In article <36D199F8.CC7375DA@dtic.ua.es> "Sergio A. Cuenca Asensi" <sergio@dtic.ua.es> writes:
>Hello,
>I am trying to implement a tiny circuit with a bidirectional data bus
>(8bits) and a addres bus (16 bits) connected to a external SRAM memory.
>In the implementation stage the M1 tool stop in the Map process and it
>produces the follow error:
>
>Design Information
>------------------
>Command Line   : map -p xc4010xl-09-pc84 -o map.ncd ../xc4000xl.ngd
>rwmem.pcf
>Target Device  : x4010xl
>Target Package : pc84
>Target Speed   : -09
>Mapper Version : xc4000xl -- M1.4.12p
>Mapped Date    : Mon Feb 22 17:48:48 1999
>
>Design Summary
>--------------
>   Number of errors:        1
>   Number of warnings:      5
>   Number of CLBs:             42 out of   400   10%
>      CLB Flip Flops:      46
>      CLB Latches:          0
>      4 input LUTs:        79
>      3 input LUTs:         3 (2 used as route-throughs)
>   Number of bonded IOBs:      39 out of    63   61%
>      IOB Flops:            0
>      IOB Latches:          0
>   Number of BUFGs:             1 out of     8   12%
>   Number of BUFGLSs:           4 out of     8   50%
>   Number of RPM macros:        3
>   Number of STARTUPs:          3
>Total equivalent gate count for design: 1013
>Additional JTAG gate count for IOBs:    1872
>
>
>Section 1 - Errors
>------------------
>ERROR:x4kma:253 - The design is too large for the given device and
>package.
>   Please check the Design Summary section to see which resource
>requirement for
>   your design exceeds the resources available in the device.
>
>
Article: 14886
Subject: Re: High Fanout Signals
From: fliptron@netcom.com (Philip Freidin)
Date: Tue, 23 Feb 1999 04:57:16 GMT
Links: << >>  << T >>  << A >>

Break the RAM into several blocks (maybe 256 by 4) and give each one its
own set of pipeline registers for address, we, and data.

Floorplan carefully and thoroughly.


In article <36D22F80.31506EEA@qub.ac.uk> Khaled benkrid <k.benkrid@qub.ac.uk> writes:
>Hi All,
>
>I am implemeting shift registers in Xilinx 4kE using a LFSR counter and
>Synchronous RAMs. I need a big shift (256*16 bits) which requires 128
>CLBs for the RAMs. I need high fanout signals to address the RAM's from
>the counter outputs in order to get high speed. What is the best
>solution ( I am thinking about using BUFG to derive these signals).  Any
>ideas????.
>
>Cheers.
>


Article: 14887
Subject: Re: Problem with xilinx M1
From: "Sergio A. Cuenca Asensi" <sergio@dtic.ua.es>
Date: Tue, 23 Feb 1999 08:40:54 +0100
Links: << >>  << T >>  << A >>


Jonas Thor wrote:

> On Mon, 22 Feb 1999 18:55:04 +0100, "Sergio A. Cuenca Asensi"
> <sergio@dtic.ua.es> wrote:
>
> <snip>
> >   Number of STARTUPs:          3
> <snip>
> >I donīt understand what resouce is overcome, any idea?
>
> Hmm... 3 startups? I suppose there should be only one. Did you
> instantiate too many?
>
> / Jonas Thor

Hi,
you are right, the number of startups is the reason. I created three
vhdl modules, one fsm and two for datapath, all three with asynchronous
reset and connected in the schematic to the same ipad (rst), so I donīt
understand why it produces three startup.

--
===================================================================
Sergio A. Cuenca Asensi
Dept. Tecnologia Informatica y Computacion (TIC)
Escuela Politecnica Superior, Campus de San Vicente
Universidad de Alicante
Ap. Correos 99, E-03080 ALICANTE
ESPAŅA (SPAIN)
email   : sergio@dtic.ua.es
Phone : +34 96 590 39 34
Fax     : +34 96 590 39 02
===================================================================


Article: 14888
Subject: Re: Problem with xilinx M1
From: tryggvem@my-dejanews.com
Date: Tue, 23 Feb 1999 08:52:50 GMT
Links: << >>  << T >>  << A >>
In article <36D199F8.CC7375DA@dtic.ua.es>,
  "Sergio A. Cuenca Asensi" <sergio@dtic.ua.es> wrote:
> Hello,
> I am trying to implement a tiny circuit with a bidirectional data bus
> (8bits) and a addres bus (16 bits) connected to a external SRAM memory.
> In the implementation stage the M1 tool stop in the Map process and it
> produces the follow error:
....
>    Number of STARTUPs:          3
....
> Section 1 - Errors
> ------------------
> ERROR:x4kma:253 - The design is too large for the given device and
> package.
>    Please check the Design Summary section to see which resource
> requirement for
>    your design exceeds the resources available in the device.
>
...

Hello, it seems like that the rather small design will fit well in our device.
But the problem migth be that you by some reasons have _3_ startup block,
each Xilinx device can only have one, therefore you are overconstraining the
placer in the M1 tool.

Try to find the origin to this errror (in schematics instansiate only ONE, or
if you are using VHDL/Verilog and Synthesis the insertion of the Startup
block is normally done automatic, but investigate the situation in the
Synthesis tool.)

// Tryggve Mathiesen

-----------== Posted via Deja News, The Discussion Network ==----------
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Article: 14889
Subject: Re: High Fanout Signals
From: tryggvem@my-dejanews.com
Date: Tue, 23 Feb 1999 09:23:19 GMT
Links: << >>  << T >>  << A >>
In article <36D22F80.31506EEA@qub.ac.uk>,
  Khaled benkrid <k.benkrid@qub.ac.uk> wrote:
> Hi All,
>
> I am implemeting shift registers in Xilinx 4kE using a LFSR counter and
> Synchronous RAMs. I need a big shift (256*16 bits) which requires 128
> CLBs for the RAMs. I need high fanout signals to address the RAM's from
> the counter outputs in order to get high speed. What is the best
> solution ( I am thinking about using BUFG to derive these signals).  Any
> ideas????.

I've been working with these structures for some times now.
For smaller blocks (like yours) my suggestion is to avoid BUFG usage (shall be
spared to clocks and possible global clockenables).

There are some possible solutions:

1) Usage of LFSR counter replication (each address counter shall only drive
~32 inputs) as they are compact.

2) The address counter bits can be driven via a TBUF over longlines, this
implies better driving and less routing, but it also affects the M1 tools
capability to the handle the shift register as a regular RAM structure.

3) For larger structures a combination of above is possible.

4) Avoid the problem by using the COREGEN tool to implement our shift
register, this method will give you a garanteed performance and is the best
if you are _not_ expert enough to handle the drawbacks with the other
solutions.

The COREGEN tool will be given to you by your Xilinix supplier.

For very large shift register, my suggestion is to use the VIRTEX family,
the selcect ram block can be configured as a shift register and have build in
capability to handle high load nets (with new low skew nets) automatic.

Regards,

Tryggve Mathiesen

====================================================================
 Enator Elektoniksystem AB
 BOX 5347                         Message by:   Tryggve Mathiesen
 Visit address Vädursgatan 6      Telephone:    +46-31-3533600
 SE-417 55 Göteborg  SWEDEN

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 14890
Subject: Re: Problem with xilinx M1
From: thor@sm.luth.se.NoSpam (Jonas Thor)
Date: Tue, 23 Feb 1999 09:52:28 GMT
Links: << >>  << T >>  << A >>
On Tue, 23 Feb 1999 08:40:54 +0100, "Sergio A. Cuenca Asensi"
<sergio@dtic.ua.es> wrote:

>
>
>Jonas Thor wrote:
>
>> On Mon, 22 Feb 1999 18:55:04 +0100, "Sergio A. Cuenca Asensi"
>> <sergio@dtic.ua.es> wrote:
>>
>> <snip>
>> >   Number of STARTUPs:          3
>> <snip>
>> >I donīt understand what resouce is overcome, any idea?
>>
>> Hmm... 3 startups? I suppose there should be only one. Did you
>> instantiate too many?
>>
>> / Jonas Thor
>
>Hi,
>you are right, the number of startups is the reason. I created three
>vhdl modules, one fsm and two for datapath, all three with asynchronous
>reset and connected in the schematic to the same ipad (rst), so I donīt
>understand why it produces three startup.

Did you synthesize the VHDL modules separately? If you did, turn the
"force global reset" option off and instantiate the startup symbol in
the schematics instead. I believe you have a startup symbol for each
VHDL module.

/ Jonas Thor  
Article: 14891
Subject: Re: Problem with xilinx M1
From: thor@sm.luth.se (Jonas Thor)
Date: Tue, 23 Feb 1999 14:47:15 GMT
Links: << >>  << T >>  << A >>
On Mon, 22 Feb 1999 18:55:04 +0100, "Sergio A. Cuenca Asensi"
<sergio@dtic.ua.es> wrote:

<snip>
>   Number of STARTUPs:          3
<snip>
>I donīt understand what resouce is overcome, any idea?

Hmm... 3 startups? I suppose there should be only one. Did you
instantiate too many?

/ Jonas Thor 
Article: 14892
Subject: test, ignore please
From: Valentin Serb <vali@thcomm.dnt.ro>
Date: Tue, 23 Feb 1999 19:39:49 +0200
Links: << >>  << T >>  << A >>
testez metoda de anti-spam. am modificat adresa de reply-to din mailer
si vreau sa vad daca un reply to sender pune in cimpul de adresa adresa
modificata.
Article: 14893
Subject: Replace an Intel 82380 or 8344 with a CPLD/FPGA
From: "Kevin Jennings" <Kevin.Jennings@Unisys.com>
Date: Tue, 23 Feb 1999 15:45:00 -0500
Links: << >>  << T >>  << A >>
Does anyone have a programmable logic core (preferably VHDL) that implements
an Intel 82380?

Does anyone have a programmable logic core (preferably VHDL) that implements
an Intel 8344?


Article: 14894
Subject: Re: Inferring IOFFs with FPGA Express 3.x and Foundation 1.5i
From: ems@riverside-machines.com.NOSPAM
Date: Tue, 23 Feb 1999 20:47:10 GMT
Links: << >>  << T >>  << A >>
On Mon, 22 Feb 1999 12:28:36 -0700, "Andy Peters"
<apeters@noao.edu.NOSPAM> wrote:

>Andy Peters wrote in message <7aknih$ebj$1@noao.tuc.noao.edu>...

>>mr. synopsys said (referring to an *asynchronous* reset):
>>Not describing a reset for a flop is a design mistake for both synthesis and
>>simulation (and for the final design). 

i think i know a lot of people who would disagree with this...
Article: 14895
Subject: Re: Xilinx de-compiler
From: Ian McLaren <imclaren@california.com>
Date: Tue, 23 Feb 1999 14:19:56 -0800
Links: << >>  << T >>  << A >>
John,

On Feb 6, John Larkin <jjlarkin@worldnet.att.net> wrote:
>>I think I've invented a neat circuit for a specialized digital PLL, and
>>of course I want to keep it proprietary. So if I make a product using a
>>Xilinx FPGA, the config bitstream can't be hidden from a competitor who
>>gets his greedy hands on one. I assume that an outright copy is a
>>copyright violation, so I'm not too worried about that. So here's the
>>issue: Is it feasible that someone could decompile the stream and
>>recover the circuit CONCEPT? Are there any tools to help them do this?
>>Would it be easy, or an enormous task?

Pretty much every FPGA designer faces the same problem at one time or
another, I think. My understanding is that it's very difficult to
decompile the Xilinx bitstream (unless one expends a huge amount of
resources, which is not worth it unless it's a very high volume / high
profit design in which case *you* could afford to use ASICs to protect
it!).  I would be more worried about unscrupulous competitors creating a
direct copy and using it in their products. Nailing transgressors on a
copyright violation can be costly and time-consuming (it's similar to
the situation with patents, but perhaps harder to document). If you sell
one device to an unscrupulous organization and they copy the design for
in-house use, you may never find out about it and you lose potential
sales.

My attempts to solve the problem have involved making the parts VERY
hard to copy. I design and build low-volume scientific instruments,
usually connected to a PC via the parallel port. I have successfully
used the following methods to prevent copying:

A) Put a CPLD (I usually use a Xilinx XC95108) on the same board, with a
few lines connected to the FPGA --- in my case, the data bus passes
through the CPLD on its way to the host PC. Implement a non-trivial
state machine in the CPLD, and a matching one in the FPGA. Use this as
an XOR mask for switching data (and even control signals, but be
careful) entering and leaving the FPGA. Because the two state machines
track, everything still works OK because it's XORed twice by the same
mask and every path switch is corrected  in the other chip. If your
competition tries to figure out the FPGA structure, or builds a copy, 
they will get garbage unless they can also replicate the CPLD, which is
MUCH harder. Reverse engineering a chip whose data and control lines
seem to wander among the pins at random will drive them to the brink of
insanity.

B) Put a Dallas DS2401 Silicon Serial Number chip next to the FPGA, and
have the latter read the 64-bit ID number after configuration. Use this
as a data or control line XOR mask as above, with a matching XOR mask as
part of the design. Once again, anyone copying the chip design will get
garbage unless they have the SSN also. This also IDs the board as well,
since Dallas guarantees that no two parts give the same 64-bit ID
number. This DOES require that each FPGA be programmed slightly
differently (it could be done as a RAM or ROM initialization value), so
only works really well for low volume products.  It also pays to hide
the SSN chip to confuse the opposition, since otherwise they can read
the 64-bit ID and possibly emulate it. A DS2401P (TSOC package) fits
quite nicely under a  PLCC FPGAsocket (if your FPGA design can possibly
stand using a socket, that is), or else you can hide it under a
convenient soldered-in component and they'll never guess it's there if
the traces are also well-disguised....

C) ID the board using either a DS2401 as above, or a CPLD with a few
macrocells programmed as an ID number, and match this with your
software. If you are loading the FPGA via an embedded microprocessor or
a host PC, the running software can require the ID number to agree. This
means that even if they copy the FPGA bitstream, the software that uses
the FPGA will not run without the correct ID.

Please feel free to contact me via E-mail if you would like more details
of any of the above methods. There IS a limit to what I will reveal in a
public forum!

If Xilinx et al would just put a small CPLD array on every FPGA die,
this problem could be solved using the above methods but without needing
a companion chip. 

Hope this has been of some interest to you,

Regards,

Ian McLaren
President 
McLaren Research
Mountain View, CA 94043
imclaren@california.com


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Article: 14896
Subject: Re: Problem with xilinx M1
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Tue, 23 Feb 1999 16:03:50 -0700
Links: << >>  << T >>  << A >>
Sergio A. Cuenca Asensi wrote in message <36D25B86.95C32125@dtic.ua.es>...
>
>
>Jonas Thor wrote:
>
>> On Mon, 22 Feb 1999 18:55:04 +0100, "Sergio A. Cuenca Asensi"
>> <sergio@dtic.ua.es> wrote:
>>
>> <snip>
>> >   Number of STARTUPs:          3
>> <snip>
>> >I donīt understand what resouce is overcome, any idea?
>>
>> Hmm... 3 startups? I suppose there should be only one. Did you
>> instantiate too many?
>>
>> / Jonas Thor
>
>Hi,
>you are right, the number of startups is the reason. I created three
>vhdl modules, one fsm and two for datapath, all three with asynchronous
>reset and connected in the schematic to the same ipad (rst), so I donīt
>understand why it produces three startup.


Do you have a top-level module that instantiates the three lower-level
modules?  It sounds like you've synthesized all three as top-level modules;
hence, three startup blocks.

-- a
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

Don't waste apostrophes!  The plural of the acronym for "personal computers"
is PCs, NOT PC's.



Article: 14897
Subject: FLEX PROBLEM
From: Chris Waterman <113625.2177@CompuServe.COM>
Date: Tue, 23 Feb 1999 18:28:29 -0500
Links: << >>  << T >>  << A >>
Help

I have designed a system around an EPF10K100ARC240-1 Flex device 
running off a 3.3v supply but interfacing direct with 5 volt 
logic. Is it possible to damage these devices if the 3.3V is 
removed but the 5V is left connected to the inputs. Having looked 
on the Altera web site, I can only find reference to these 
problems using 5V core devices. I have had several units fail 
(25%) and the fault is usually the device not driving one of its 
output pins which doesn't necessarily have to be one connected to 
this 5V interface. 
Has anyone else had similar problems with such failures. It does 
not appear to be static damage. 
Many Thanks,

Chris

-- 

Article: 14898
Subject: Re: Xilinx Virtex
From: "mark" <feydo@lcworkshop.com>
Date: Wed, 24 Feb 1999 00:07:49 GMT
Links: << >>  << T >>  << A >>
I've done one design in the XV300 part.  My design contains four 5 tap FIR
filters with loadable coefficients (10 bit input data and 10 bit
coefficients) and several adders to combind the output of the taps plus
some general decode logic.  All of this needs to run at 50MHz.

The Foundation tools are a real pain to deal with.  Many functions (ie.
library components / macros) either don't work at all or don't simulate
quite right.  But, after a bunch of help from our local FAE we got through
the issues.

Once past the design entry portion of the design things got much better. 
It was truly a push button implementation.  The design uses about 70% of
the part and will run at 58MHz (as reported by PPR).  Reality seems to
agree with this as everything is working on the bench at 50Mhz.

In my opinion the Foundation tools have a ways to go before they are solid,
but the Virtex part itself is great.

mark


Daryl Bradley <dwb105@ohm.york.ac.uk> wrote in article
<36D13540.3F98B5A8@ohm.york.ac.uk>...
> Anyone had any experience using the new Xilinx Virtex chips along with
> any of the development boards as yet?
> 
> Cheers
> 
> Daryl Bradley
> 
> --
> 
> Bio-Inspired Architectures
> Department of Electronics
> University of York, UK
> http://www-users.york.ac.uk/~dwb105
> 
> 
> 
Article: 14899
Subject: Your view on this article?
From: Zhen Luo <zhenluo@ee.princeton.edu>
Date: Tue, 23 Feb 1999 23:18:45 -0500
Links: << >>  << T >>  << A >>
Hi,

I read the following article on EE times today. What do you think about
it? I think the problems they mention in this article have always been
there, but it seems that this is the first time people really use the
word "dark future" for programmable logic. What do you think?

-- Zhen


                   FPGA'99: Panel glimpses dark future for
                   programmable silicon

                   By Ron Wilson
                   EE Times
                   (02/23/99, 11:19 a.m. EDT)

                   MONTEREY, Calif. — A panel at FPGA'99 here Monday
(Feb. 22)
                   peered into the future of FPGAs in the era of
system-level ICs and saw
                   deep shadows. While FPGA-vendor panel members touted
the ability of
                   huge new FPGAs to easily absorb large pieces of
intellectual property (IP),
                   or for hard IP macros to be integrated onto FPGA
dice, panelists from the
                   research and user communities saw things very
differently.

                   In opposition to the notion that you can simply put
an entire system-level
                   design into an FPGA, University of Washington
professor Carl Ebeling
                   warned, "If all you have is a hammer, everything
looks like a nail. But if we
                   keep thinking that everything looks like it has an
FPGA solution, we could
                   get screwed."

                   Beyond the initial levity, Ebeling warned that for
many applications, it is
                   simply not good enough for an FPGA to do tomorrow
what an ASIC can
                   do today. "The gaps in power consumption and
performance between
                   FPGAs and ASICs aren't narrowing, they are growing
wider," he said.
                   "And those gaps are pushing more and more high-end
applications not
                   toward FPGAs, but toward ASICs."

                   Admitting that not everything can be done well in an
FPGA, University of
                   California Los Angeles professor Jason Cong said even
adding some
                   diffused hard cores to a chip doesn't solve the
problems. Cong, whose
                   influential work produced some of the first tools
that could systematically
                   map logic into the SRAM blocks on Altera Corp.'s Flex
devices, warned
                   that "the devil is in the software."

                   "There are very substantial problems in creating
design software for devices
                   that include both FPGA and hard blocks," Cong said.
"Among them, it is
                   quite difficult to automatically partition an
algorithm among heterogeneous
                   resources, even such common resources as programmable
logic and
                   SRAM. If you can do the partitioning, it is difficult
to optimize the
                   implementation of parts of the algorithm on each kind
of resource. And if
                   you solve that problem, there are still very hard
problems involved in
                   run-time communication between different kinds of
blocks, scheduling and
                   the like."

                   But if the arguments against incorporating either
soft or hard IP into FPGAs
                   were strong, the most sobering statements of the
night came from a
                   customer — a very influential customer.

                   "We are a major consumer of FPGAs," said Bill Harris
of Cisco Systems
                   Inc. And Harris' data showed he was being modest.
Cisco claims to be
                   currently the largest single user of programmable
logic, shipping over one
                   million PLDs of various sorts per month.

                   Once he had the audience's attention, Harris lowered
the boom. "Despite
                   that, I have to say that for large systems our trend
is to ASICs, not to
                   programmable-logic devices. On the systems that make
up our platforms,
                   we will spin an ASIC rather than use an FPGA."

                   Harris explained that a major phase was over in the
halcyon relationship
                   between the networking industry and the FPGA
business. "In the beginning,
                   it was a small Cisco competing against other small
companies.
                   Time-to-market was everything, and cost wasn't an
issue. If we could get
                   the latest speed grade of an FPGA, we'd throw it in
just so we could start
                   shipping."

                   But times are very different now in the industry,
Harris said. "Now, we
                   have established market share and established
platforms. Customers aren't
                   going to pull out our gear just because it takes a
while for us to support a
                   new feature. But there is intense price competition.
We have the luxury of
                   longer development times, but not the luxury of
naming our own prices."

                   These factors, Harris said, were gradually weaning
Cisco from use of
                   programmable logic in complex or high-volume
applications. This, if it
                   proves generally true, could be an enormous challenge
to the growth of an
                   FPGA industry that has been feasting at the table of
the networking and
                   communications companies for several years.

                   But Harris wasn't through spoiling the evening for
the FPGA vendors. "We
                   have the resources and the tools now to do very
high-performance,
                   multi-million gate designs on single chips. One
design we have in progress is
                   approaching 20 million gates. FPGAs have neither the
speed nor the
                   density to approach this level.

                   "When we need field programmability, what we would
prefer is not to have
                   a huge programmable device, or even a programmable
device with a huge
                   piece of hardware set down beside it. We would prefer
to have an FPGA
                   core to drop into our ASIC. We typically need small
amounts of
                   reconfigurable logic beside the fixed hardware.

                   "Unfortunately, that doesn't seem to be the way the
industry is moving,"
                   Harris said. "I think first we will see FPGA vendors
try to provide IP on
                   their devices. But that's not what we'd like. If we
could get an FPGA core
                   for use in our ASICs today, we would be doing that
already."

                   The sum of the university and industry inputs from
this very small but
                   undeniably influential sample suggested bad news for
the FPGA business.
                   The strongest high-volume customers for FPGAs appear
to be changing
                   their buying habits. Increasingly, they are using
ASICs instead of FPGAs.
                   And when they need programmable logic, they intend to
get it, if not from
                   their ASIC vendor, at least as third-party IP, not as
silicon. If this
                   foreshadowing becomes a trend, it could force a major
shift in business
                   models for the largest programmable-logic vendors.



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