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Welcome to the club. Xilinx is not alone on this. A long time ago, I saw a study on quality of software. 90% of problems were with licensing. Better luck next time. PeteArticle: 148401
On Jul 17, 9:33=A0pm, Vips <thevipulsi...@gmail.com> wrote: > Hi All > > I am implementing an I2C slave and low level interface to interface it > to EEPROM. I am using I2c Master for verifying this module . The I2C > Master code is reused from some other module. He has implemented the > I2C in a fashion that the PULL up and the Pull Down is to be provided > from outside. It has SCL_IN,SCL_OUT, SDA_IN,SDA_OUT ports and some > other control signals. It doesnot generate a start and stop condition > inside i2c master block. I have seen the code it waits for the SDA to > go from LOW to HIGH .My question is > > 1. in I2C master do we have to make a separate module in verilog ( the > code is in verilog) to generate start and stop condition. or it is > expected to have this functionality inside the I2C master > controller. > 2. How do I connect for verifying the slave and the Interface . The > SDA_IN( master) is connected to SDA_OUT( slave) and SCL_IN( master) is > connects to SCL_GEN module ( as the I2C master takes SCL_IN as inut to > the master module . SCL_OUT(master) connects to SCL_IN (SLAVE), > SDA_OUT( master) to SDA_IN( slave) . =A0The confusion is the start and > stop generation /detection module as it is not inside the controller > has to be connected from outside. Will the START gen module just send > SCL and SDA to I2c Master for start operation and the the master will > take from there. > 3. In the initial state when it is reset under normal protocol > situation the SCL is Z and the SDA is Z both pulled up . To start the > operation for a start gen condition is there a separate module to do > so .How normally in I2C master it is done( someone who has already > done it. > 4. I have gone througn the standard but got confused as how the first > start and stop condition is generated and who will toggle the first > SDA low to high. > > I have googled also and looked for some reference designs but it is > not running well in sumulation to understand how the first start > operation is gereated as the slave is IDLE and waiting for the start > signal from the master. > > I would highly appreciate any suggestions on this issue. > > Thanks in advance > > Vipul Since the I2C Master generates the START and STOP commands it is very unusual that this is not part of the I2C Master that you are using. The START and STOP are integral parts of the communication protocol and it isn't clear to me how you could add this in parallel to the Master. Your description of using SDA_IN, SDA_OUT, SCL_IN and SCL_OUT for connections between the Master and Slave is also very unusual. Both of these cores should simple have a SDA and SCL bi-directional port that are connected with a weak PULLUP. The likely cause is that the author intended for a user add the bi-dir IO buffer in the top level, but there should also be able a SDA_TRI and SCL_TRI ports as well to control the direction. Ed McGettigan -- Xilinx Inc. EdArticle: 148402
On Jul 19, 7:31=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Jul 17, 9:33=A0pm, Vips <thevipulsi...@gmail.com> wrote: > > > > > > > Hi All > > > I am implementing an I2C slave and low level interface to interface it > > to EEPROM. I am using I2c Master for verifying this module . The I2C > > Master code is reused from some other module. He has implemented the > > I2C in a fashion that the PULL up and the Pull Down is to be provided > > from outside. It has SCL_IN,SCL_OUT, SDA_IN,SDA_OUT ports and some > > other control signals. It doesnot generate a start and stop condition > > inside i2c master block. I have seen the code it waits for the SDA to > > go from LOW to HIGH .My question is > > > 1. in I2C master do we have to make a separate module in verilog ( the > > code is in verilog) to generate start and stop condition. or it is > > expected to have this functionality inside the I2C master > > controller. > > 2. How do I connect for verifying the slave and the Interface . The > > SDA_IN( master) is connected to SDA_OUT( slave) and SCL_IN( master) is > > connects to SCL_GEN module ( as the I2C master takes SCL_IN as inut to > > the master module . SCL_OUT(master) connects to SCL_IN (SLAVE), > > SDA_OUT( master) to SDA_IN( slave) . =A0The confusion is the start and > > stop generation /detection module as it is not inside the controller > > has to be connected from outside. Will the START gen module just send > > SCL and SDA to I2c Master for start operation and the the master will > > take from there. > > 3. In the initial state when it is reset under normal protocol > > situation the SCL is Z and the SDA is Z both pulled up . To start the > > operation for a start gen condition is there a separate module to do > > so .How normally in I2C master it is done( someone who has already > > done it. > > 4. I have gone througn the standard but got confused as how the first > > start and stop condition is generated and who will toggle the first > > SDA low to high. > > > I have googled also and looked for some reference designs but it is > > not running well in sumulation to understand how the first start > > operation is gereated as the slave is IDLE and waiting for the start > > signal from the master. > > > I would highly appreciate any suggestions on this issue. > > > Thanks in advance > > > Vipul > > Since the I2C Master generates the START and STOP commands it is very > unusual that this is not part of the I2C Master that you are using. > The START and STOP are integral parts of the communication protocol > and it isn't clear to me how you could add this in parallel to the > Master. > > Your description of using SDA_IN, SDA_OUT, SCL_IN and SCL_OUT for > connections between the Master and Slave is also very unusual. =A0Both > of these cores should simple have a SDA and SCL bi-directional port > that are connected with a weak PULLUP. =A0The likely cause is that the > author intended for a user add the bi-dir IO buffer in the top level, > but there should also be able a SDA_TRI and SCL_TRI ports as well to > control the direction. > > Ed McGettigan > -- > Xilinx Inc. > > Ed- Hide quoted text - > > - Show quoted text - Thanks for the reply.. Let me add that the Master has SDA_IN( input) SDA_TRISTATE( output) this is a simple output with no tristate. SCL_IN (input) SCL_TRISTATE(OUTPUT). Now I am confused as How the first start will be generated as who will toggle the SDA_IN line which is the input to the master for the START generation while the SCK_IN is high ....Article: 148403
On Sun, 18 Jul 2010 21:11:18 -0700 (PDT), Vips <thevipulsinha@gmail.com> wrote: >Thanks for the reply.. Let me add that the Master has SDA_IN( input) >SDA_TRISTATE( output) this is a simple output with no tristate. SCL_IN >(input) SCL_TRISTATE(OUTPUT). Now I am confused as How the first start >will be generated as who will toggle the SDA_IN line which is the >input to the master for the START generation while the SCK_IN is >high .... Because I2C is an open-drain (open collector) interface it doesn't need to drive any of the outputs high ie high level generation is done by the external pullup. This can be accomplished with a push-pull IO by driving a strong zero and tri-state for one. So you need a regular tri-state IO and drive zero when tri-state is inactive and tri-state when it is active ie (assuming active high tri-state IOPAD): IOPAD master_sda(.IN(sda_in), .OUT(sda_tristate), .OE(sda_tristate), .PAD(sda_wire)); -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 148404
Hi all Has any one used Virtex 4 FX12 minimodule along with any ADC(analog to digital converter) IC for sending digitiized data on ethernet? If someone has any experience on FX12 mini module kindly share it. THANKS --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148405
On 16 juil, 21:10, Gabor <gabor@alacron.com> wrote: > 3664 x 2748 x 12 x 9 =3D 1,087,416,576 bits. =A0That won't quite fit into > 1 gigabit > or 1,073,741,824 bits. The memory is 1 Gigabyte =3D 8,589,934,592 bits, it could fit about 70 frames of images. I want to use SDRAM as circular buffer to store images. there should be at least 9 frames to meet system requirement. > > Is this the Spartan 6 memory controller? =A0You need to select the size > and number of ports based on your system requirements. =A0How fast > is the pixel data coming in? =A0Is the readout required to run at the > same > rate or possibly even faster (as with image averaging).? > yes, it's Spartan 6, the max pixel data in rate is 80MegaPixel/sec at 80MHz, the max input bandwidth is 0.9375gigabits/sec. The output of SDRAM is connected with a DSP, the read data rate is about 8 time slower than write rate. (the write rate could be slower as needed ) > > Again this depends on your required bandwidth. =A0Obviously you > can't run the memory faster than the chip allows (your part > number should have a speed grage at the end like -5 or -3. > you would need the -3 speed grade to run 333 MHz). > On the other hand why waste extra power and make it > harder to meet timing constraints if you don't really need > to run effectively 1.33 gigabytes per second total memory > bandwidth? > the Spartan6 has a speed of -3, what I need is on one hand, SDRAM stores frames of images at a pixel clock rate, on the other hand, the GPIO could access to read out image for DSP at a much slower rate to avoid glitch. > Not if you want to fit 9 frames in memory. =A0You'll need to pack > your data 4 pixels to every three words of memory, and even then > there will not quire be enough unless you reduce the image size > slightly. > I don't quite understand what does it mean "You'll need to pack > your data 4 pixels to every three words of memory" > > When you have extra memory to waste you can use nice binary > powers to store lines and frames. =A0In your case you don't have that > luxury and will need to keep track of the starting address of each > frame > buffer and the line stride within the frame. > As I have enough memory to store my images, could you please explain more? > Thanks again for your help! > > > GladysArticle: 148406
On Jul 17, 3:42=A0pm, Muzaffer Kal <k...@dspia.com> wrote: > On Sat, 17 Jul 2010 03:14:05 -0700 (PDT), Socrates <mail...@gmail.com> > wrote: > > >> I had similar results. =A0My thought was that it was a Java problem - > >> different browsers typically have different ways of dealing with > >> embedded Java. > > >> RK. > > >If there is a such need, I could mirror the image somewhere. > > Because of copyright issues, it wouldn't be advisable for you to > distribute Xilinx files without explicit permission. The best case > would be for Xilinx to have multiple servers for their own files. > -- > Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Services > > http://www.dspia.com I found that if when on the following page: http://www.xilinx.com/support/download/index.htm If click the *WINDOWS 32/64 bit (2.81G)* button on the top, I can download the tar file with no problem. If I click the "version 12.1" under the design tools tab, it fails to download. Hope this helps. DaveArticle: 148407
On Jul 19, 8:45 am, Gladys <yuhu...@gmail.com> wrote: > On 16 juil, 21:10, Gabor <ga...@alacron.com> wrote:> 3664 x 2748 x 12 x 9 = 1,087,416,576 bits. That won't quite fit into > > 1 gigabit > > or 1,073,741,824 bits. > > The memory is 1 Gigabyte = 8,589,934,592 bits, it could fit about 70 > frames of images. > I want to use SDRAM as circular buffer to store images. there should > be at least 9 frames > to meet system requirement. > The chip you mentioned, MT47H64M16, is 1 gigabit, not 1 gigabyte. You need 8 of these chips for 1 gigabyte of memory. I don't think you'll be able to drive 8 chips with the Spartan 6 MIG controller. Check carefully in the customization screens for MIG to see what you can do. > > > > Is this the Spartan 6 memory controller? You need to select the size > > and number of ports based on your system requirements. How fast > > is the pixel data coming in? Is the readout required to run at the > > same > > rate or possibly even faster (as with image averaging).? > > yes, it's Spartan 6, the max pixel data in rate is 80MegaPixel/sec at > 80MHz, > the max input bandwidth is 0.9375gigabits/sec. The output of SDRAM is > connected > with a DSP, the read data rate is about 8 time slower than write rate. > (the write rate > could be slower as needed ) > So sticking to me original idea of a 16-bit wide interface, even if you wasted the upper 4 bits you could store and retrieve 600 million pixels per second at 300 MHz. I would consider running the interface at a more comfortable 200 MHz which still gives you a lot of extra bandwidth if all you need is a pixel buffer. > > > > Again this depends on your required bandwidth. Obviously you > > can't run the memory faster than the chip allows (your part > > number should have a speed grage at the end like -5 or -3. > > you would need the -3 speed grade to run 333 MHz). > > On the other hand why waste extra power and make it > > harder to meet timing constraints if you don't really need > > to run effectively 1.33 gigabytes per second total memory > > bandwidth? > > the Spartan6 has a speed of -3, what I need is on one hand, SDRAM > stores > frames of images at a pixel clock rate, on the other hand, the GPIO > could access > to read out image for DSP at a much slower rate to avoid glitch. > What is the speed grade of the MT47H64M16? That would need to be -3 for the 300 MHz interface. a -5 part would be good enough for 200 MHz. > > Not if you want to fit 9 frames in memory. You'll need to pack > > your data 4 pixels to every three words of memory, and even then > > there will not quire be enough unless you reduce the image size > > slightly. > > I don't quite understand what does it mean "You'll need to pack > > > your data 4 pixels to every three words of memory" > If your pixels are 12 bits and you want to store them in 16-bit wide memory, concatenate 4 of them to make 48 bits of pixel data which fit into three 16-bit words. > > When you have extra memory to waste you can use nice binary > > powers to store lines and frames. In your case you don't have that > > luxury and will need to keep track of the starting address of each > > frame > > buffer and the line stride within the frame. > > As I have enough memory to store my images, could you please explain > more? > I'm still not convinced you do have memory to waste, but the basic idea is to start a new image line on say a 4096-word boundary even though the actual line width is only 3664. This makes line addressing simpler. Do something similar by starting a new frame buffer at a 4096-line boundary even though the frame is only 2748 lines. This will mean that addressing within a frame buffer is a simpler function of pixel and line position. > > Thanks again for your help! > > > > GladysArticle: 148408
On 19 juil, 17:08, Gabor <ga...@alacron.com> wrote: > The chip you mentioned, MT47H64M16, is 1 gigabit, not 1 gigabyte. =A0You > need 8 of these chips for 1 gigabyte of memory. =A0I don't think you'll > be able > to drive 8 chips with the Spartan 6 MIG controller. =A0Check carefully > in the > customization screens for MIG to see what you can do. Yes you are right, it's 1Gigabit and there's only 1 memory chip in my implementation, I think in this case I will scale down the image resolution to 3000x2748, then it could fit 9 frames of images. > So sticking to me original idea of a 16-bit wide interface, even if > you > wasted the upper 4 bits you could store and retrieve 600 million > pixels per second at 300 MHz. =A0I would consider running the > interface at a more comfortable 200 MHz which still gives you > a lot of extra bandwidth if all you need is a pixel buffer. I am quite confused with the 4, 8, 16 width mamory data bus and the 32, 64, 128 port configuation width, is there any documents which explain the architecture? Should I just use two 32bits bidirectional ports and disable the others in the MIG configuration depends on my system requirement? I still don't know how to implement the memory controller interface using MIG. > What is the speed grade of the MT47H64M16? =A0That would need to > be -3 for the 300 MHz interface. =A0a -5 part would be good enough > for 200 MHz. the speed grade of MT47H64M16 is -3. Then should I use 200MHz? > If your pixels are 12 bits and you want to store them in 16-bit wide > memory, concatenate 4 of them to make 48 bits of pixel data > which fit into three 16-bit words. So is this concatenation performed in the memory controller while writing the data? > I'm still not convinced you do have memory to waste, but the basic > idea is > to start a new image line on say a 4096-word boundary even though the > actual line width is only 3664. =A0This makes line addressing simpler. > Do > something similar by starting a new frame buffer at a 4096-line > boundary > even though the frame is only 2748 lines. =A0This will mean that > addressing > within a frame buffer is a simpler function of pixel and line > position. > If I do this, each frame of image will take 4096*4096*12=3D 201,326,592bits, I can olny store 5 image in the SDRAM, which doesn't meet the requirement, In this case, can I write images and meanwhile read them out, the SDRAM will perform as a large FIFO. Also to simplify the logic, I can leave the 4bits unused as I don't need to store as much images as before? Thanks again for your help! > > > > > GladysArticle: 148409
On Jul 18, 9:11=A0pm, Vips <thevipulsi...@gmail.com> wrote: > On Jul 19, 7:31=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > > > On Jul 17, 9:33=A0pm, Vips <thevipulsi...@gmail.com> wrote: > > > > Hi All > > > > I am implementing an I2C slave and low level interface to interface i= t > > > to EEPROM. I am using I2c Master for verifying this module . The I2C > > > Master code is reused from some other module. He has implemented the > > > I2C in a fashion that the PULL up and the Pull Down is to be provided > > > from outside. It has SCL_IN,SCL_OUT, SDA_IN,SDA_OUT ports and some > > > other control signals. It doesnot generate a start and stop condition > > > inside i2c master block. I have seen the code it waits for the SDA to > > > go from LOW to HIGH .My question is > > > > 1. in I2C master do we have to make a separate module in verilog ( th= e > > > code is in verilog) to generate start and stop condition. or it is > > > expected to have this functionality inside the I2C master > > > controller. > > > 2. How do I connect for verifying the slave and the Interface . The > > > SDA_IN( master) is connected to SDA_OUT( slave) and SCL_IN( master) i= s > > > connects to SCL_GEN module ( as the I2C master takes SCL_IN as inut t= o > > > the master module . SCL_OUT(master) connects to SCL_IN (SLAVE), > > > SDA_OUT( master) to SDA_IN( slave) . =A0The confusion is the start an= d > > > stop generation /detection module as it is not inside the controller > > > has to be connected from outside. Will the START gen module just send > > > SCL and SDA to I2c Master for start operation and the the master will > > > take from there. > > > 3. In the initial state when it is reset under normal protocol > > > situation the SCL is Z and the SDA is Z both pulled up . To start the > > > operation for a start gen condition is there a separate module to do > > > so .How normally in I2C master it is done( someone who has already > > > done it. > > > 4. I have gone througn the standard but got confused as how the first > > > start and stop condition is generated and who will toggle the first > > > SDA low to high. > > > > I have googled also and looked for some reference designs but it is > > > not running well in sumulation to understand how the first start > > > operation is gereated as the slave is IDLE and waiting for the start > > > signal from the master. > > > > I would highly appreciate any suggestions on this issue. > > > > Thanks in advance > > > > Vipul > > > Since the I2C Master generates the START and STOP commands it is very > > unusual that this is not part of the I2C Master that you are using. > > The START and STOP are integral parts of the communication protocol > > and it isn't clear to me how you could add this in parallel to the > > Master. > > > Your description of using SDA_IN, SDA_OUT, SCL_IN and SCL_OUT for > > connections between the Master and Slave is also very unusual. =A0Both > > of these cores should simple have a SDA and SCL bi-directional port > > that are connected with a weak PULLUP. =A0The likely cause is that the > > author intended for a user add the bi-dir IO buffer in the top level, > > but there should also be able a SDA_TRI and SCL_TRI ports as well to > > control the direction. > > > Ed McGettigan > > -- > > Xilinx Inc. > > > Ed- Hide quoted text - > > > - Show quoted text - > > Thanks for the reply.. Let me add that the Master has SDA_IN( input) > SDA_TRISTATE( output) this is a simple output with no tristate. SCL_IN > (input) SCL_TRISTATE(OUTPUT). Now I am confused as How the first start > will be generated as who will toggle the SDA_IN line which is the > input to the master for the START generation while the SCK_IN is > high ....- Hide quoted text - > > - Show quoted text - The I2C Master issues the START and STOP and these doesn't just happen at the beginning and end of an operation. If the operation includes register address in the slave device then there is a second START that is issued after the register address is written followed by the slave address and then either reading or writing of the slave data. I think that you need to go back to the place that you got the I2C Master from and ask them for help because either you are misunderstanding their documentation or they have created a design that won't work well if at all. Ed McGettigan -- Xilinx Inc.Article: 148410
On Jul 18, 10:37=A0pm, Muzaffer Kal <k...@dspia.com> wrote: > On Sun, 18 Jul 2010 21:11:18 -0700 (PDT), Vips > > <thevipulsi...@gmail.com> wrote: > >Thanks for the reply.. Let me add that the Master has SDA_IN( input) > >SDA_TRISTATE( output) this is a simple output with no tristate. SCL_IN > >(input) SCL_TRISTATE(OUTPUT). Now I am confused as How the first start > >will be generated as who will toggle the SDA_IN line which is the > >input to the master for the START generation while the SCK_IN is > >high .... > > Because I2C is an open-drain (open collector) interface it doesn't > need to drive any of the outputs high ie high level generation is done > by the external pullup. This can be accomplished with a push-pull IO > by driving a strong zero and tri-state for one. So you need a regular > tri-state IO and drive zero when tri-state is inactive and tri-state > when it is active ie (assuming active high tri-state IOPAD): > > IOPAD master_sda(.IN(sda_in), .OUT(sda_tristate), .OE(sda_tristate), > .PAD(sda_wire)); > -- > Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Services > > http://www.dspia.com Without knowing the functionality of the SDA_TRISTATE output (does 1=3DHiZ or does 1=3DDrive, my bet would be HiZ) and the functionality of the IOPAD OE pin (this isn't a Xilinx cell, but OE usually mean Output Enable/Drive) your code may not work.Article: 148411
On 7/18/2010 7:03 PM, self wrote: > Welcome to the club. Xilinx is not alone on this. > > A long time ago, I saw a study on quality of software. 90% of > problems were with licensing. > > Better luck next time. > > Pete > Tell me about it. A Windows box trying to run two different FlexLM licensed pieces of software is almost guaranteed to break at least one of them. God help you if you need three. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 148412
The information on types and conversions in Jim's paper is very good. The recommendations for coding style (based on limitations of synthesis tools) are a bit dated. Synth tools have come a long way in 7 years. I recommend using integer for arithmetic if your data paths are less than 32 bits. Mod has been well supported for quite a while (it was then if you used decent FPGA tools), and is very handy for making sure you don't have overflows (which do not go silently in the night in simulation with integers). For example: signal count: natural range 0 to max_count - 1; ... count <= (count + 1 ) mod max_count; -- assume max_count = 2**n will roll over automatically for both increment and decrement. Also since count - 1 is completely legal for count = 0 (so long as you don't try to store it back into count). Therefore, you can extract the carry bit like so: if count - 1 < 0 then -- carry bit set do_something; count <= max_count - 1; -- safe (BTW, constant arithmetic is free) else count <= count - 1; end if; This also works with "if count + 1 >= max_count then". Integer type arithmetic also automatically promotes natural - natural => integer (use mod to "resize" when necessary). You might look into the new fixed point package, which also can be used for arithmetic w/o fractional bits. It automatically promotes result size to accomodate largest possible result. Unfortunately, it does not promote ufixed - ufixed => sfixed. His recomendations for resource sharing and separation of computation from state logic are unnecessary now; code it so you know WHAT it is doing, and let the tool figure out HOW to do it. AndyArticle: 148413
"M.Randelzhofer" <techseller@gmx.de> wrote in message news:8ah8otFgh5U1@mid.individual.net... > I'm really pissed off. Its ironic. Like with the entertainment industry, it may be easier to get the pirated version. You can use your own license with it, as it often has the original files on and a license generator.Article: 148414
Hey Sean, Sorry for the late post and my guess is you have either given up or figured out how to do this. Unroutes should not be happening by just adding Partitions. If you want to try again, you might want to look at the number of INFO and WARNING messages about constants on inputs and/or outputs and also the number of unconnected outputs. The goal for Partitions is to keep the implementation results regardless of changes outside of the Partition. For that reason, we do not optimize any constants or unusued outputs across the Partition boundary. Often, this can cause more logic resulting in lower QoR. Sometimes this can cause unroutes. We are looking at changing this in the future. If you don't think this is the issue, I would really like to see the design so we can improve our flow. The best way to do this is to file a webcase so we can look at it. The best documentation for the 12.1 flow is the HD Methodology Guide. It is located at http://www.xilinx.com/support/documentation/sw_manuals/xilinx12_1/Hierarchical_Design_Methodology_Guide.pdf. Thanks, Kate --------------------------------------- Posted through http://www.FPGARelated.comArticle: 148415
On Jul 17, 8:17=A0pm, self <pete.dud...@comcast.net> wrote: > Hello All, > > I have a requirement to build a SOC design with two Arm cores along > with some standard and custom peripherals. =A0The Actel Cortex-M1 > enabled FPGA's appear to be ideal for my application because the > licensing fee is included in the price of the processor. > > I have started playing around with the Libero tools to see how > processor development is done with them. =A0The Libero environment comes > with a tool called SmartDesign for assembling a processor system. =A0It > seems to work reasonably well for creating an initial system. =A0You > connect the pieces with a graphical editor and the tool outputs VHDL > (or Verilog) for synthesis and simulation. > > Though fine for initial prototyping I do not like to use graphical > tools to maintain a delivered design. =A0It is just too likely that some > glitch will block me from doing what I want. =A0I prefer to enter and > maintain the design at the HDL level with just a text editor and > synthesis tool. > > I looked at the VHDL that comes out of SmartDesign and it is typical > machine generated code. =A0Just a bunch of block instantiations > connected by meaningless signal names. =A0Here comes my question. > > Using Actel tools can you work with the Arm/Amba processor IP directly > in HDL? =A0Is there a library of cores with documentation? =A0Any comment= s > are greatly appreciated. > > Best wishes, > > =A0 Pete NO NO NO the Actel cortex is preoptimized hard-macro block that can not be used with other tools or modified directly. you can of course use original arm cortex code if you have it (and license) AnttiArticle: 148416
Hi all, This is a post to announce the existence of the AjarDSP project, an attempt to design and implement an open source VLIW DSP with an open source tool chain (assembler, simulator/debugger and C compiler). Check out the details at: http://code.google.com/p/ajardsp/ regards MarkusArticle: 148417
On Jul 21, 3:27=A0am, Markus Lavin <markusl.se78pleasenos...@gmail.com> wrote: > Hi all, > > This is a post to announce the existence of the AjarDSP project, an > attempt to design and implement an open source VLIW DSP with an open > source tool chain (assembler, simulator/debugger and C compiler). > > Check out the details at:http://code.google.com/p/ajardsp/ > > regards > Markus Looks like a pretty ambitious project; good luck. It looks to me that your design was heavily influenced by TI's C55x family? It does appear to have a number of enhancements above any of those devices though (more registers, more parallelism). JasonArticle: 148418
On 19 juil, 17:08, Gabor <ga...@alacron.com> wrote: > The chip you mentioned, MT47H64M16, is 1 gigabit, not 1 gigabyte. =A0You > need 8 of these chips for 1 gigabyte of memory. =A0I don't think you'll > be able > to drive 8 chips with the Spartan 6 MIG controller. =A0Check carefully > in the > customization screens for MIG to see what you can do. > Yes you are right, it's 1Gigabit and there's only 1 memory chip in my implementation, I think in this case I will scale down the image resolution to 3000x2748, then it could fit 9 frames of images. > So sticking to me original idea of a 16-bit wide interface, even if > you > wasted the upper 4 bits you could store and retrieve 600 million > pixels per second at 300 MHz. =A0I would consider running the > interface at a more comfortable 200 MHz which still gives you > a lot of extra bandwidth if all you need is a pixel buffer. > > > What is the speed grade of the MT47H64M16? =A0That would need to > be -3 for the 300 MHz interface. =A0a -5 part would be good enough > for 200 MHz. the speed grade of MT47H64M16 is -3. > > If your pixels are 12 bits and you want to store them in 16-bit wide > memory, concatenate 4 of them to make 48 bits of pixel data > which fit into three 16-bit words. > How to implement this? If I choose the 128bit R/W port configuration, Should I pack 12bits pixel at the host side for the 128bits write data FIFO? > I'm still not convinced you do have memory to waste, but the basic > idea is > to start a new image line on say a 4096-word boundary even though the > actual line width is only 3664. =A0This makes line addressing simpler. > Do > something similar by starting a new frame buffer at a 4096-line > boundary > even though the frame is only 2748 lines. =A0This will mean that > addressing > within a frame buffer is a simpler function of pixel and line > position. > If I do this, each frame of image will take 4096*4096*12=3D 201,326,592bits, I can olny store 5 image in the SDRAM, which doesn't meet the requirement, In this case, can I store images and meanwhile read them out, the SDRAM will perform as a large FIFO. Also to simplify the logic, I can leave the 4bits unused as I don't need to store as much images as before? Thanks! > > > > > GladysArticle: 148419
I'm trying to create a LVPECL_25 differential output on a Spartan 3 (XC3S200 device in PQ208 package). I did this by selecting 'LVPECL_25' in the I/O Standard column in PACE (assign package pins). However, in 'Implement Design' I get the following error: Process "Translate" completed successfully Using target part "3s200pq208-5". Mapping design into LUTs... Running directed packing... ERROR:Pack:946 - The I/O component "q" has an illegal IOSTANDARD value. Components of type IOB do not support IOSTANDARD LVPECL_25. Please correct the IOSTANDARD property value. What am I doing wrong? I'm still using ISE 9.1.03i. Thanks, ThomasArticle: 148420
Is there any way to do this? Is there any way to do this without standing on my head? The last time I used ISE this was a Windows box. But I've evolved into a Higher Life Form*, and now I don't do Windows if I can help it**. I'd sidestep the whole problem by getting a USB JTAG cable and running Windows in a VirtualBox -- but Xilinx is out of USB cables right now, and Avnet is quoting a 6-week lead time. Xilinx -- perhaps wisely -- doesn't support many versions of Linux. So unless I can find someone in the Portland, Oregon area that has a USB JTAG cable for sale, rent, or beg, I need to either make what I have work under Ubuntu, I need to resurrect my dual-bootishness, or I need to run a Xilinx-approved Linux flavor. Ick, ick, and ick. * Or at least a highly irritating Linux Geek ** And I seem to have lost the recipe on my dual-boot system, 'cause it's been a long long time since I needed to. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 148421
According to Avnet, Xilinx is out of their USB JTAG cables for weeks. I need one (see post about Linux, Cables, woe, etc.). Anyone got one? Anyone close to Oregon City, Oregon got one? I'm willing to pay a fair price, particularly if it's within driving distance. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 148422
On Jul 21, 3:23=A0pm, Thomas Heller <thel...@python.net> wrote: > I'm trying to create a LVPECL_25 differential output on a Spartan 3 > (XC3S200 device in PQ208 package). =A0I did this by selecting 'LVPECL_25' > in the I/O Standard column in PACE (assign package pins). > > However, in 'Implement Design' I get the following error: > > Process "Translate" completed successfully > Using target part "3s200pq208-5". > Mapping design into LUTs... > Running directed packing... > ERROR:Pack:946 - The I/O component "q" has an illegal IOSTANDARD value. > =A0 =A0Components of type IOB do not support IOSTANDARD LVPECL_25. =A0Ple= ase correct > =A0 =A0the IOSTANDARD property value. > > What am I doing wrong? =A0I'm still using ISE 9.1.03i. > > Thanks, > Thomas Type IOB? Do you mean Type IOBUF? If it's the latter, the differential version might be IOBUFDS. I took a look at Table 10-3: Spartan-3 Generation I/O Components on page 321 of UG331 (v1.6) Spartan-3 Generation FPGA User Guide - http://www.xilinx.com/support/documentation/user_guides/u= g331.pdf - where some of the implementation details might be less murky.Article: 148423
On Wed, 21 Jul 2010 15:10:37 -0700, Tim Wescott <tim@seemywebsite.com> wrote: >Is there any way to do this? > >Is there any way to do this without standing on my head? > It doesn't quite involve standing on your head (at least in OpenSuse 11, I haven't tried it in Ubuntu) but it does involve finding a "usb-driver" library that also supports the parallel port. (The Xilinx-supported "libusb" is a different beast) I got it from http://rmdir.de/~michael/xilinx/ It uses the "ppdev" driver to communicate the parport, and only works at 200kHz (Par Cable 3 compatibility mode) but once I got ot going I haven't had any trouble with it. Better than the official Xilinx approach using Jungo Windriver, which won't even build on any post-2008 kernel, as far as I can tell... - BrianArticle: 148424
On 7/21/2010 11:10 PM, Tim Wescott wrote: > but Xilinx is out of USB cables right now, > and Avnet is quoting a 6-week lead time. > > I see several on our favourite tat bazaar. EBay... e.g. http://cgi.ebay.co.uk/Xilinx-Platform-Cable-USB-Programmer-FPGA-JTAG-DHL-/190412257236?cmd=ViewItem&pt=LH_DefaultDomain_0&hash=item2c557477d4 Genuine HK knockoffs.
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