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Messages from 149175

Article: 149175
Subject: Re: Starting a career with FPGAs
From: Sink0 <sink00@gmail.com>
Date: Wed, 6 Oct 2010 00:45:20 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 6, 7:19=A0am, "jt_eaton"
<z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
> >>2. Learn scripting to verify the FPGA and drivers at the system level.
> >> =A0 =A0Bash, python and tcl to s
>
> >Just a question... what kind of important tasks can be done with
> >script that the vendor synthesiser (as QUartus II or ISE) cant handle?
>
> The synthesizer simply compiles the rtl into gates. You still have to
> verify the gates.
>
> You never build production code using a gui. You always script it. That w=
ay
> you can start a job before leaving and it will be done when you come back
> tomorrow without you having to sit there and click a mouse every few hour=
s.
> It also means that you never have to worry that you forgot to check the
> "fix hold times" box on your final run. You will open a new design using =
a
> gui and from then on you take the command log and edit that if you need t=
o
> change anything.
>
> Your verification suite should also be scripted for the same reason.
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

Very interesting... can you point me any good tutorial or example on
how to use scripts to make this kind of task with FPGA? For now all i
know is a bit of Pearl.

Thank you!

Article: 149176
Subject: Re: Starting a career with FPGAs
From: "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Wed, 06 Oct 2010 03:48:48 -0500
Links: << >>  << T >>  << A >>

> For now all i know is a bit of Pearl.

But not quite enough to spell the name correctly...

As stated previously, you need to use scripts to ensure fully-reproducable
results for "production" purposes. For most FPGA tools, the scripting
lanuage supported by the tools is Tcl. Alternatively, you can often run
them from the "command line" using the OS-native scripting language. Good
luck with that if you are running Windoze. Or invoke a different command
interpreter from which to invoke the tools, such as Perl.

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 149177
Subject: Re: Starting a career with FPGAs
From: Sink0 <sink00@gmail.com>
Date: Wed, 6 Oct 2010 02:21:27 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 6, 10:48=A0am, "RCIngham"
<robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
> > For now all i know is a bit of Pearl.
>
> But not quite enough to spell the name correctly...
>
> As stated previously, you need to use scripts to ensure fully-reproducabl=
e
> results for "production" purposes. For most FPGA tools, the scripting
> lanuage supported by the tools is Tcl. Alternatively, you can often run
> them from the "command line" using the OS-native scripting language. Good
> luck with that if you are running Windoze. Or invoke a different command
> interpreter from which to invoke the tools, such as Perl.
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

Hmm ok, so i will start learning tcl. Thank you very much for the
help!!

Article: 149178
Subject: Re: Xilinx Artix 7 - When?
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Wed, 6 Oct 2010 10:56:27 +0000 (UTC)
Links: << >>  << T >>  << A >>
Ed McGettigan <ed.mcgettigan@xilinx.com> wrote:
> On Oct 5, 3:12 pm, Uwe Bonnes <b...@elektron.ikp.physik.tu-
> darmstadt.de> wrote:
> > Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
> >
> > ...
> >
> > > There is no announced date for Artix-7 device availability at this
> > > time.
> >
> > Is there something announced for S6?
> >

> With the exception of the XC6SLX4 and XC6SLX9 all devices are in
> production and in stock at Avnet for small quantities and 6-8 weeks
> times for larger quantities.

> http://avnetexpress.avnet.com/store/em/EMController?action=products&N=0&&term=XC6SLX

Any expected roll-out time for SLX4/SLX9? They are the only parts in QFP...

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 149179
Subject: Re: Starting a career with FPGAs
From: James Harris <james.harris.1@googlemail.com>
Date: Wed, 6 Oct 2010 06:27:38 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 4 Oct, 01:11, Alexander Kane <ajpk...@gmail.com> wrote:
> Hello.
> I'm currently coming to the end of my last semester of my four year
> engineering degree in electronics and computer systems engineering.
> I've really enjoyed working with FPGAs as part of my degree and am now
> tutoring the FPGA course. =A0Basically I want to start a career working
> with FPGAs, but am not sure how to go about it. =A0I live in New
> Zealand, but as the job market here is so small I'm looking at Europe
> (as I speak both English and German I figure that opens up several
> countries I could work in). =A0Does anyone have any suggestions or
> advice as to how I go about entering such a career, or what kind of
> options are out there, or even websites I can look for jobs on?

Take a look at

  http://www.jobserve.co.uk

I just tried a search for keyword fpga in IT jobs in UK, Europe etc
and more than 20 have come up. If you keep an eye on the site for a
few months you could find some jobs you like you'll see what other
skills and experience they are looking for.

James

Article: 149180
Subject: StratixII GX development board
From: axalay <axalay@gmail.com>
Date: Wed, 6 Oct 2010 07:00:42 -0700 (PDT)
Links: << >>  << T >>  << A >>
Good day!
In fitter I have some identical errors:

Error: Cannot place pin Ddr2SdramDq[28] to location AN17
	Error: Can't place VREF pin AR16 (VREFGROUP_B7_N1) for pin
Ddr2SdramDq[28] of type bi-directional with SSTL-18 Class II I/O
standard at location AN17
		Error: Too many output and bidirectional pins in I/O bank 7 assigned
near VREF pin AR16 (VREFGROUP_B7_N1) on device EP2SGX90FF1508C3 -- no
more than 20 output and bidirectional pins allowed near the VREF pin
when voltage referenced pins are driving in, but there are potentially
21 pins driving out

Help!!!

Article: 149181
Subject: Re: External Circuit to FPGA.
From: Santosh <santos2k7@gmail.com>
Date: Wed, 6 Oct 2010 07:06:02 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 5, 2:30=A0pm, Din=E7ay Ak=E7=F6ren <din...@gmail.com> wrote:
> On Oct 4, 4:13=A0pm, Santosh <santos...@gmail.com> wrote:
>
>
>
> > On Oct 4, 5:42=A0pm, Santosh <santos...@gmail.com> wrote:
>
> > > On Oct 4, 5:00=A0pm, Anssi Saari <a...@sci.fi> wrote:
>
> > > > radarman <jsham...@gmail.com> writes:
> > > > > Those boards are made by Digilent. You might check and see if the=
y
> > > > > have a breadboard with the Hirose connector on it.
>
> > > > They do, for $30. Also a wirewrap and module interface board (for
> > > > Pmods) which are both cheaper at $20.
>
> > > There are a lot of Pmods there. I need to input and output digital
> > > data from FPGA board. Please suggest me the exact name. Also, except
> > > Hirose port aren't there any ports to connect external circuit?
> > > San.
>
> > Hi,
> > I found this board. -- =A0http://www.digilentinc.com/Data/Products/FX2B=
B/FX2BB_%20rm.pdf
> > =A0Is it the same you people mentioned? And do I need a bus to connect
> > the board with FPGA? Or the Hirose in the daughter board directly
> > couples with the Hirose on FPGA? I didn't found any bus or cables in
> > their site.
>
> This board fits to your expansion connector on spartan 3e starter kit.
> You don't need any bus, cable etc.

Thanks! I got it!

Article: 149182
Subject: Driving a design via TCP/IP
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Wed, 6 Oct 2010 16:32:26 +0100
Links: << >>  << T >>  << A >>
Hello all,

I've had an enquiry in about a project that is mostly simple enough,
I'll be using an FPGA for what's required, the fly in the ointment is
the client wants the thing unit via TCP/IP.

All the ethernet interface is going to be used for is driving and reading
internal registers, it could very easily be done via RS-422 (which is an
option) but it looks like they definitely want TCP/IP.

One approach would be to implement a NIOS core with OS and network stacks,
I'd have to outsource setting this all up. This really does seem to be
a lot of added complexity required both in FPGA resource and external
components required to support the NIOS.

It would also require licensing the NIOS IPS-Embedded suite and an
OS (or does it?) which isn't cheap.

Another approach would be to use a microcontroler with embedded TCP/IP
stack and MAC and use this to drive the FPGA via an external bus,
although I think an SPI bus might be sufficient.

I have designed a couple of boards with an ethernet interface but this
was to an ARM device where a SW engineer had the responsibility of getting
it all set up and working.

Can anyone comment on the difficulty of implementing an ethernet interface
with a NIOS core, or advise on a small simple microcontroller that would
make this all much simpler.

Thanks in advance,

Nial.




Article: 149183
Subject: Re: Driving a design via TCP/IP
From: Rich Webb <bbew.ar@mapson.nozirev.ten>
Date: Wed, 06 Oct 2010 11:42:55 -0400
Links: << >>  << T >>  << A >>
On Wed, 6 Oct 2010 16:32:26 +0100, "Nial Stewart"
<nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote:

>Hello all,
>
>I've had an enquiry in about a project that is mostly simple enough,
>I'll be using an FPGA for what's required, the fly in the ointment is
>the client wants the thing unit via TCP/IP.
>
>All the ethernet interface is going to be used for is driving and reading
>internal registers, it could very easily be done via RS-422 (which is an
>option) but it looks like they definitely want TCP/IP.
>
>One approach would be to implement a NIOS core with OS and network stacks,
>I'd have to outsource setting this all up. This really does seem to be
>a lot of added complexity required both in FPGA resource and external
>components required to support the NIOS.
>
>It would also require licensing the NIOS IPS-Embedded suite and an
>OS (or does it?) which isn't cheap.
>
>Another approach would be to use a microcontroler with embedded TCP/IP
>stack and MAC and use this to drive the FPGA via an external bus,
>although I think an SPI bus might be sufficient.
>
>I have designed a couple of boards with an ethernet interface but this
>was to an ARM device where a SW engineer had the responsibility of getting
>it all set up and working.
>
>Can anyone comment on the difficulty of implementing an ethernet interface
>with a NIOS core, or advise on a small simple microcontroller that would
>make this all much simpler.

Depending on where you are on the build/buy curve, the little XPort
gizmos are often an easy answer. From the inside of the box, looking
out, it appears as a serial port. From the outside it handles UDP/IP or
TCP/IP (configurable). Could be a good fit for configuration & status.

<http://www.lantronix.com/device-networking/embedded-device-servers/xport.html>

-- 
Rich Webb     Norfolk, VA

Article: 149184
Subject: Re: Driving a design via TCP/IP
From: Symon <symon_brewer@hotmail.com>
Date: Wed, 06 Oct 2010 16:52:45 +0100
Links: << >>  << T >>  << A >>
On 10/6/2010 4:32 PM, Nial Stewart wrote:

>
> Can anyone comment on the difficulty of implementing an ethernet interface
> with a NIOS core, or advise on a small simple microcontroller that would
> make this all much simpler.
>
> Thanks in advance,
>
> Nial.
>
>


http://www.fpga4fun.com/10BASE-T.html

Any help?

Syms.

Article: 149185
Subject: Re: Driving a design via TCP/IP
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Wed, 6 Oct 2010 16:53:46 +0100
Links: << >>  << T >>  << A >>
> Depending on where you are on the build/buy curve, the little XPort
> gizmos are often an easy answer. From the inside of the box, looking
> out, it appears as a serial port. From the outside it handles UDP/IP or
> TCP/IP (configurable). Could be a good fit for configuration & status.
>
> <http://www.lantronix.com/device-networking/embedded-device-servers/xport.html>



Thanks Rich, I'm completely open to any solution which simply provides
TCP/IP access to the unit.

That looks like an ideal solution!


Nial. 



Article: 149186
Subject: Re: Driving a design via TCP/IP
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Wed, 6 Oct 2010 16:59:10 +0100
Links: << >>  << T >>  << A >>
> http://www.fpga4fun.com/10BASE-T.html
> Any help?
> Syms.


Aye possibly although I'd prefer a 'canned' solution where possible.

From what I've got so far the main portion of the design is a week
or two's work. I don't want to have to spend another month getting the
e'net connectivity working.


Nial. 



Article: 149187
Subject: Re: Driving a design via TCP/IP
From: Mel <mwilson@the-wire.com>
Date: Wed, 06 Oct 2010 12:03:10 -0400
Links: << >>  << T >>  << A >>
Rich Webb wrote:

> On Wed, 6 Oct 2010 16:32:26 +0100, "Nial Stewart"

>>Can anyone comment on the difficulty of implementing an ethernet interface
>>with a NIOS core, or advise on a small simple microcontroller that would
>>make this all much simpler.
> 
> Depending on where you are on the build/buy curve, the little XPort
> gizmos are often an easy answer. From the inside of the box, looking
> out, it appears as a serial port. From the outside it handles UDP/IP or
> TCP/IP (configurable). Could be a good fit for configuration & status.
> 
> <http://www.lantronix.com/device-networking/embedded-device-
servers/xport.html>

A similar device providing the equivalent of four AF_INET sockets on a chip 
and speaking SPI or memory-bus connection is

<http://www.wiznet.co.kr/Sub_Modules/en/product/Product_Detail.asp?cate1=5&cate2=7&cate3=26&pid=1011>

or a module based on it

<http://www.saelig.com/BRD/ETH027.htm>

These chips/boards are the ones I used.  There are probably more recent 
versions.

	Mel.


Article: 149188
Subject: Re: Driving a design via TCP/IP
From: Symon <symon_brewer@hotmail.com>
Date: Wed, 06 Oct 2010 17:24:21 +0100
Links: << >>  << T >>  << A >>
On 10/6/2010 4:59 PM, Nial Stewart wrote:
>> http://www.fpga4fun.com/10BASE-T.html
>> Any help?
>> Syms.
>
>
> Aye possibly although I'd prefer a 'canned' solution where possible.
>
>  From what I've got so far the main portion of the design is a week
> or two's work. I don't want to have to spend another month getting the
> e'net connectivity working.
>
>
> Nial.
>
>
Yep, the solutions from the other posts are much better. A bit like 
those USB thingies from FTDI.

Syms.

Article: 149189
Subject: Re: Driving a design via TCP/IP
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Wed, 6 Oct 2010 17:30:24 +0100
Links: << >>  << T >>  << A >>
> Yep, the solutions from the other posts are much better. A bit like those USB thingies from FTDI.


Aye that's what I'm looking for, I don't want to have to do anything
actually difficult!

:-)


Nial. 



Article: 149190
Subject: Re: Driving a design via TCP/IP
From: nico@puntnl.niks (Nico Coesel)
Date: Wed, 06 Oct 2010 17:09:02 GMT
Links: << >>  << T >>  << A >>
"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
wrote:

>Hello all,
>
>I've had an enquiry in about a project that is mostly simple enough,
>I'll be using an FPGA for what's required, the fly in the ointment is
>the client wants the thing unit via TCP/IP.
>
>All the ethernet interface is going to be used for is driving and reading
>internal registers, it could very easily be done via RS-422 (which is an
>option) but it looks like they definitely want TCP/IP.
>
>One approach would be to implement a NIOS core with OS and network stacks,
>I'd have to outsource setting this all up. This really does seem to be
>a lot of added complexity required both in FPGA resource and external
>components required to support the NIOS.
>
>It would also require licensing the NIOS IPS-Embedded suite and an
>OS (or does it?) which isn't cheap.
>
>Another approach would be to use a microcontroler with embedded TCP/IP
>stack and MAC and use this to drive the FPGA via an external bus,
>although I think an SPI bus might be sufficient.
>
>I have designed a couple of boards with an ethernet interface but this
>was to an ARM device where a SW engineer had the responsibility of getting
>it all set up and working.
>
>Can anyone comment on the difficulty of implementing an ethernet interface
>with a NIOS core, or advise on a small simple microcontroller that would
>make this all much simpler.

FreeRtos (freertos.org) + NXP LPC17xx.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

Article: 149191
Subject: Re: Driving a design via TCP/IP
From: Tauno Voipio <tauno.voipio@notused.fi.invalid>
Date: Wed, 06 Oct 2010 20:09:05 +0300
Links: << >>  << T >>  << A >>
Nial Stewart wrote:
> Hello all,
> 
> I've had an enquiry in about a project that is mostly simple enough,
> I'll be using an FPGA for what's required, the fly in the ointment is
> the client wants the thing unit via TCP/IP.
> 
> All the ethernet interface is going to be used for is driving and reading
> internal registers, it could very easily be done via RS-422 (which is an
> option) but it looks like they definitely want TCP/IP.

If it is not specified how the TCP/IP is to be used,
you can design a simple request-response exchange
based on simple UDP packets. It is not too tedious
to implement the protocol stack up to UDP even for
raw silicon. The difficult beast is TCP.

> Another approach would be to use a microcontroler with embedded TCP/IP
> stack and MAC and use this to drive the FPGA via an external bus,
> although I think an SPI bus might be sufficient.

Get a controller with Ethernet and SPI, e.g.
Stellaris LM3S6965. The dev board is pretty inexpensive
(less than 100 USD, IIRC) and you should be able to do
the required networking with it for testing.

-- 

Tauno Voipio
tauno voipio (at) iki fi


Article: 149192
Subject: Re: Xilinx Artix 7 - When?
From: Kolja Sulimma <ksulimma@googlemail.com>
Date: Wed, 6 Oct 2010 10:12:11 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 6 Okt., 07:06, rickman <gnu...@gmail.com> wrote:
=A0A
> lot of the presentation talked to the cost savings that was possible
> using PR. =A0But that only makes sense to me if it can be used with low
> cost parts. =A0Reducing the cost of using a more expensive part by using
> a complex process is a poor substitute to just using a part that costs
> less. =A0But if I can use the less expensive part and cut my costs
> further by using PR, that can make a number of projects practical that
> otherwise wouldn't be.

I completely disagree.
If you have a design that barely fits in a 6k$ part and can reduce the
LUT
count by a factor of 4 by using PR you save about 4k$ per chip
This is what happens for DNA pattern matching machines.

Try saving 4k$ with a spartan-3.

The volume where saving 10$ per chip justifies the more complex PR
design process
is rather high.

Kolja

Article: 149193
Subject: Re: Driving a design via TCP/IP
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Wed, 06 Oct 2010 19:17:43 +0200
Links: << >>  << T >>  << A >>
Tauno Voipio <tauno.voipio@notused.fi.invalid> writes:

> Get a controller with Ethernet and SPI, e.g.
> Stellaris LM3S6965. The dev board is pretty inexpensive
> (less than 100 USD, IIRC) and you should be able to do
> the required networking with it for testing.

Seem to be quite similar to the FreeScale MCF5223X. Are there any
other TCP/IP stacks other than Internice available for the LM3S6965?

Petter
-- 
.sig removed by request. 

Article: 149194
Subject: Re: Driving a design via TCP/IP
From: stephenXXX@mpeforth.com (Stephen Pelc)
Date: Wed, 06 Oct 2010 17:46:01 GMT
Links: << >>  << T >>  << A >>
On Wed, 6 Oct 2010 16:32:26 +0100, "Nial Stewart"
<nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote:

>Can anyone comment on the difficulty of implementing an ethernet interface
>with a NIOS core, or advise on a small simple microcontroller that would
>make this all much simpler.

There are any number of 32 bit single-chip controllers with enough
on-chip Flash and RAM to run a TCP/IP stack and a an application.
We've used plenty of NXP devices from the LPC23xx and LPC17xx 
families. There are also the Stellaris/TI devices LM3S9B9x.
Freescale have plenty of Coldfire devices, e.g. MCF52259.
Some of these have external bus interfaces if that makes
interfacing the FPGA any easier.

Stephen


-- 
Stephen Pelc, stephenXXX@mpeforth.com
MicroProcessor Engineering Ltd - More Real, Less Time
133 Hill Lane, Southampton SO15 5AF, England
tel: +44 (0)23 8063 1441, fax: +44 (0)23 8033 9691
web: http://www.mpeforth.com - free VFX Forth downloads

Article: 149195
Subject: Re: Driving a design via TCP/IP
From: "Paul E. Bennett" <Paul_E.Bennett@topmail.co.uk>
Date: Wed, 06 Oct 2010 18:56:30 +0100
Links: << >>  << T >>  << A >>
Nial Stewart wrote:

> Hello all,
> 
> I've had an enquiry in about a project that is mostly simple enough,
> I'll be using an FPGA for what's required, the fly in the ointment is
> the client wants the thing unit via TCP/IP.
> 
> All the ethernet interface is going to be used for is driving and reading
> internal registers, it could very easily be done via RS-422 (which is an
> option) but it looks like they definitely want TCP/IP.


Not the only place but if the RS422 option is what you feel comfortable with 
you could use one of these as the Ethernet interface.

<http://www1.shopping.com/physical-interface-module-ic485ip-1/products> 

Might save you some work if the network speed you require is not that fast.

-- 
********************************************************************
Paul E. Bennett...............<email://Paul_E.Bennett@topmail.co.uk>
Forth based HIDECS Consultancy
Mob: +44 (0)7811-639972
Tel: +44 (0)1235-510979
Going Forth Safely ..... EBA. www.electric-boat-association.org.uk..
********************************************************************


Article: 149196
Subject: Re: Driving a design via TCP/IP
From: Tauno Voipio <tauno.voipio@notused.fi.invalid>
Date: Wed, 06 Oct 2010 21:21:04 +0300
Links: << >>  << T >>  << A >>
Petter Gustad wrote:
> Tauno Voipio <tauno.voipio@notused.fi.invalid> writes:
> 
>> Get a controller with Ethernet and SPI, e.g.
>> Stellaris LM3S6965. The dev board is pretty inexpensive
>> (less than 100 USD, IIRC) and you should be able to do
>> the required networking with it for testing.
> 
> Seem to be quite similar to the FreeScale MCF5223X. Are there any
> other TCP/IP stacks other than Internice available for the LM3S6965?

There are uIP and LwIP with the dev kit. I'm running my own.

-- 

Tauno Voipio

Article: 149197
Subject: Re: Add custom Ip to EDK - No result from sw registers
From: Firoz <user@compgroups.net/>
Date: Thu, 07 Oct 2010 01:24:27 -0500
Links: << >>  << T >>  << A >>
did you got the solution, I am also facing the same type of problem, can you plz help.



Article: 149198
Subject: question when using asmi_parallel ip core
From: "PaulHam" <hamsdeji@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Thu, 07 Oct 2010 03:50:08 -0500
Links: << >>  << T >>  << A >>
Hi,all

I'm Paul Ham in Korea and have some difficulties in using ASMI_PARALLEL
altera ip core.
Anyone who knows well this problem could advice to me.

I've used both single-byte write and page write.
My problem is on "busy" signal after write operation.
First, when I used page write(256 bytes) operation, the "busy" signal from
ip core kept "high" during 30 us.
Second I tried to use single byte write operation, however, the ip core
gave me the "busy" signal during 300 us !!

It's unbelievable and different from the asmi_parallel data sheet.
The data sheet shows that only 3 us is needed after single byte write
operation.

So, I'd like to get some advice here what makes unexpected result.
The signals I give asmi_parallel ip core, the write/wren/addr/data are
exact.

Thanks in advanced
Regards
Paul	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 149199
Subject: Re: Driving a design via TCP/IP
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Thu, 7 Oct 2010 10:10:45 +0100
Links: << >>  << T >>  << A >>
> FreeRtos (freertos.org) + NXP LPC17xx.


Thanks Nico but this isn't much simpler than implementing an OS & TCP/IP
on a NIOS (I presume).


Nial. 





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