Messages from 153125

Article: 153125
Subject: Re: Horsepower On Tap
From: Michael Laajanen <michael_laajanen@yahoo.com>
Date: Thu, 08 Dec 2011 10:41:24 +0100
Links: << >> << T >> << A >>

HI,

Rob Gaddi skrev 2011-12-07 18:54:
> I was waiting for Quartus to finish crunching my latest build, and poking
> around idly on NewEgg trying to see what it would cost to get a machine
> with a little more juice to it.  I started thinking what a shame it was to
> have to keep upgrading to the latest and greatest machine in order to
> squeeze out some more clock cycles for big builds.  And then I started
> thinking about Amazon EC2.
>
> The idea behind EC2 is that Amazon runs virtual machines for you, and you
> pay them by the hour for their use.  Use of an "Extra Large High-Memory
> Instance" running RHEL would run $0.63 an hour.  It's the new spin on the
> old "timeshare the supercomputer" concept.  This seems like a handy way to
> get a beast of a computer when I need to do big builds and/or long
> simulation runs without having to keep upgrading my core machine.
>
> Has anyone tried this out to see if it works in practice?  http://
> moxielogic.org/blog/?p=450 says he had serious trouble with it, but that's
> from a year ago.  Ideally, anyone with experience trying this with Quartus,
> but ISE, Modelsim, Rivera, etc would all be interesting.
>
Sun tried that for a number of years ago in their huge build/simulation 
center, but I think it failed when you need licensed software.


/michael

Article: 153126
Subject: Re: DDR2 read interface
From: "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Thu, 08 Dec 2011 04:28:34 -0600
Links: << >> << T >> << A >>

>Hello,
>I have a question regarding DDR2 memory controller. In a read operation
>from DDR2 based on strobe, do one need to shift the strobe by 90' in
order
>to capture the valid data, or is there any pther way for it ?
>

The optimal phase shift will depend on the 2-way track delay between the
Controller IC (e.g. your FPGA) and the SDRAM (clock out, data back).

Taking the DDR2 SDRAM Controllers generated by the Xilinx MIG tool as an
example, they go through a training period working out the best phase shift
relative to the FPGA-internal clock to sample the read data.

Alternatively, you could route the SDRAM clock back to the FPGA, and use
that.

Neither is easy. Therefore use your FPGA vendor's IP if at all possible.

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 153127
Subject: Re: Horsepower On Tap
From: Christopher Felton <nospam@nowhere.com>
Date: Thu, 08 Dec 2011 08:35:35 -0600
Links: << >> << T >> << A >>

On 12/7/2011 11:54 AM, Rob Gaddi wrote:
> I was waiting for Quartus to finish crunching my latest build, and poking
> around idly on NewEgg trying to see what it would cost to get a machine
> with a little more juice to it.  I started thinking what a shame it was to
> have to keep upgrading to the latest and greatest machine in order to
> squeeze out some more clock cycles for big builds.  And then I started
> thinking about Amazon EC2.
>
> The idea behind EC2 is that Amazon runs virtual machines for you, and you
> pay them by the hour for their use.  Use of an "Extra Large High-Memory
> Instance" running RHEL would run $0.63 an hour.  It's the new spin on the
> old "timeshare the supercomputer" concept.  This seems like a handy way to
> get a beast of a computer when I need to do big builds and/or long
> simulation runs without having to keep upgrading my core machine.
>
> Has anyone tried this out to see if it works in practice?  http://
> moxielogic.org/blog/?p=450 says he had serious trouble with it, but that's
> from a year ago.  Ideally, anyone with experience trying this with Quartus,
> but ISE, Modelsim, Rivera, etc would all be interesting.
>

You can provide some feedback here, http://bit.ly/rFONhB, that you would 
like cloud FPGA P&R.

Article: 153128
Subject: Re: Xilinx 7 series PCIe core models vs. Icarus Verilog
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Thu, 8 Dec 2011 08:26:15 -0800 (PST)
Links: << >> << T >> << A >>

On Dec 7, 10:43=A0pm, Michael Laajanen <michael_laaja...@yahoo.com>
wrote:
> HI,
> Stephen Williams skrev 2011-12-07 21:19:
>
>
>
> > On 12/07/2011 09:17 AM, Ed McGettigan wrote:
> >> On Dec 7, 8:49 am, Stephen Williams<spamt...@icarus.com> =A0wrote:
> >>> We are looking for simulation models for the Xilinx 7 series
> >>> FPGA PCIe core. We use Icarus Verilog models extensively, but
> >>> the models that Xilinx provides are encrypted, so locked in to
> >>> a small set of other simulators. We are hoping that we are not
> >>> the only ones with this problem and we can share simulation
> >>> models for their core.
> >>> --
> >>> Steve Williams =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"The woods are lovely, =
dark and deep.
> >>> steve at icarus.com =A0 =A0 =A0 =A0 =A0 But I have promises to keep,h=
ttp://www.icarus.com=A0 =A0 =A0 =A0and lines to code before I sleep,http://=
www.picturel.com=A0 =A0 =A0And lines to code before I sleep."
>
> >> The PCIe embedded hard block is a very complicated design and the
> >> simulation models are released as encrypted models to protect the IP.
> >> Simulation is supported in the free Xilinx iSim simulator as well as
> >> ModelTech and I belive VCS simulators.
>
> >> There is no support for Icarus.
>
> > That is very awkward for us since we use a fair amount of VPI
> > code in our system level simulations. We are basically being forced
> > to either come up with our own simulation of the PCIe hard core,
> > or port our simulation environment to a "blessed" simulator.
>
> > At one time I talked with some of your engineers about adding the
> > necessary encryption support into Icarus Verilog, but it was not
> > clear to me which encryption method you used, and whether it would
> > have been viable to have an open source implementation of it. I
> > think we concluded no.
>
> Synopsys have their own smartmodels but Xilinx moved to SecureIP for
> some reasons, more open?
>
> http://www.xilinx.com/support/answers/33275.htm
>
> /michael
>
> /michael- Hide quoted text -
>
> - Show quoted text -

Move away from SmartModels was primarily due to a lack of continuing
support from Synopsys for the latest OS and simulator versions.

The SecureIP models are supported in a wide range of simulators as the
answer record shows.

Ed McGettigan
--
Xilinx Inc.

Article: 153129
Subject: Re: Horsepower On Tap
From: Michael Laajanen <michael_laajanen@yahoo.com>
Date: Thu, 08 Dec 2011 17:29:12 +0100
Links: << >> << T >> << A >>

Hi,

Rob Gaddi skrev 2011-12-07 18:54:
> I was waiting for Quartus to finish crunching my latest build, and poking
> around idly on NewEgg trying to see what it would cost to get a machine
> with a little more juice to it.  I started thinking what a shame it was to
> have to keep upgrading to the latest and greatest machine in order to
> squeeze out some more clock cycles for big builds.  And then I started
> thinking about Amazon EC2.
>
> The idea behind EC2 is that Amazon runs virtual machines for you, and you
> pay them by the hour for their use.  Use of an "Extra Large High-Memory
> Instance" running RHEL would run $0.63 an hour.  It's the new spin on the
> old "timeshare the supercomputer" concept.  This seems like a handy way to
> get a beast of a computer when I need to do big builds and/or long
> simulation runs without having to keep upgrading my core machine.
>
> Has anyone tried this out to see if it works in practice?  http://
> moxielogic.org/blog/?p=450 says he had serious trouble with it, but that's
> from a year ago.  Ideally, anyone with experience trying this with Quartus,
> but ISE, Modelsim, Rivera, etc would all be interesting.
>
One other drawback is that you will have to pay per P&R or simulation 
run, this was how it was in the minicomputer era(VAX and more) then came 
Unix workstations suddenly you did not have to think about the cost for 
a simulation run it was your own desktop workstation.

No, I think flatrate(you pay for your own box and run) is best, you will 
not have flat rate in a elastic clound :)

You can pay on demand for licenses but that is not nice either!

Just my experiences

/michael

Article: 153130
Subject: Re: Xilinx 7 series PCIe core models vs. Icarus Verilog
From: Michael Laajanen <michael_laajanen@yahoo.com>
Date: Thu, 08 Dec 2011 18:54:45 +0100
Links: << >> << T >> << A >>

Hi,
Ed McGettigan skrev 2011-12-08 17:26:
> On Dec 7, 10:43 pm, Michael Laajanen<michael_laaja...@yahoo.com>
> wrote:
>> HI,
>> Stephen Williams skrev 2011-12-07 21:19:
>>
>>
>>
>>> On 12/07/2011 09:17 AM, Ed McGettigan wrote:
>>>> On Dec 7, 8:49 am, Stephen Williams<spamt...@icarus.com>    wrote:
>>>>> We are looking for simulation models for the Xilinx 7 series
>>>>> FPGA PCIe core. We use Icarus Verilog models extensively, but
>>>>> the models that Xilinx provides are encrypted, so locked in to
>>>>> a small set of other simulators. We are hoping that we are not
>>>>> the only ones with this problem and we can share simulation
>>>>> models for their core.
>>>>> --
>>>>> Steve Williams                "The woods are lovely, dark and deep.
>>>>> steve at icarus.com           But I have promises to keep,http://www.icarus.com       and lines to code before I sleep,http://www.picturel.com     And lines to code before I sleep."
>>
>>>> The PCIe embedded hard block is a very complicated design and the
>>>> simulation models are released as encrypted models to protect the IP.
>>>> Simulation is supported in the free Xilinx iSim simulator as well as
>>>> ModelTech and I belive VCS simulators.
>>
>>>> There is no support for Icarus.
>>
>>> That is very awkward for us since we use a fair amount of VPI
>>> code in our system level simulations. We are basically being forced
>>> to either come up with our own simulation of the PCIe hard core,
>>> or port our simulation environment to a "blessed" simulator.
>>
>>> At one time I talked with some of your engineers about adding the
>>> necessary encryption support into Icarus Verilog, but it was not
>>> clear to me which encryption method you used, and whether it would
>>> have been viable to have an open source implementation of it. I
>>> think we concluded no.
>>
>> Synopsys have their own smartmodels but Xilinx moved to SecureIP for
>> some reasons, more open?
>>
>> http://www.xilinx.com/support/answers/33275.htm
>>
>> /michael
>>
>> /michael- Hide quoted text -
>>
>> - Show quoted text -
>
> Move away from SmartModels was primarily due to a lack of continuing
> support from Synopsys for the latest OS and simulator versions.
>
> The SecureIP models are supported in a wide range of simulators as the
> answer record shows.
>
> Ed McGettigan
> --
> Xilinx Inc.
Speaking of Synopsys, since they now since a couple of years fully 
supports Solaris on x64 has Xilinx any plans/discussions about that to?

/michael

Article: 153131
Subject: Re: Xilinx 7 series PCIe core models vs. Icarus Verilog
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Thu, 8 Dec 2011 17:33:29 -0800 (PST)
Links: << >> << T >> << A >>

On Dec 8, 9:54=A0am, Michael Laajanen <michael_laaja...@yahoo.com>
wrote:
> Hi,
> Ed McGettigan skrev 2011-12-08 17:26:
>
>
>
> > On Dec 7, 10:43 pm, Michael Laajanen<michael_laaja...@yahoo.com>
> > wrote:
> >> HI,
> >> Stephen Williams skrev 2011-12-07 21:19:
>
> >>> On 12/07/2011 09:17 AM, Ed McGettigan wrote:
> >>>> On Dec 7, 8:49 am, Stephen Williams<spamt...@icarus.com> =A0 =A0wrot=
e:
> >>>>> We are looking for simulation models for the Xilinx 7 series
> >>>>> FPGA PCIe core. We use Icarus Verilog models extensively, but
> >>>>> the models that Xilinx provides are encrypted, so locked in to
> >>>>> a small set of other simulators. We are hoping that we are not
> >>>>> the only ones with this problem and we can share simulation
> >>>>> models for their core.
> >>>>> --
> >>>>> Steve Williams =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"The woods are lovely=
, dark and deep.
> >>>>> steve at icarus.com =A0 =A0 =A0 =A0 =A0 But I have promises to keep=
,http://www.icarus.com=A0 =A0 =A0 and lines to code before I sleep,http://w=
ww.picturel.com=A0 =A0 And lines to code before I sleep."
>
> >>>> The PCIe embedded hard block is a very complicated design and the
> >>>> simulation models are released as encrypted models to protect the IP=
.
> >>>> Simulation is supported in the free Xilinx iSim simulator as well as
> >>>> ModelTech and I belive VCS simulators.
>
> >>>> There is no support for Icarus.
>
> >>> That is very awkward for us since we use a fair amount of VPI
> >>> code in our system level simulations. We are basically being forced
> >>> to either come up with our own simulation of the PCIe hard core,
> >>> or port our simulation environment to a "blessed" simulator.
>
> >>> At one time I talked with some of your engineers about adding the
> >>> necessary encryption support into Icarus Verilog, but it was not
> >>> clear to me which encryption method you used, and whether it would
> >>> have been viable to have an open source implementation of it. I
> >>> think we concluded no.
>
> >> Synopsys have their own smartmodels but Xilinx moved to SecureIP for
> >> some reasons, more open?
>
> >>http://www.xilinx.com/support/answers/33275.htm
>
> >> /michael
>
> >> /michael- Hide quoted text -
>
> >> - Show quoted text -
>
> > Move away from SmartModels was primarily due to a lack of continuing
> > support from Synopsys for the latest OS and simulator versions.
>
> > The SecureIP models are supported in a wide range of simulators as the
> > answer record shows.
>
> > Ed McGettigan
> > --
> > Xilinx Inc.
>
> Speaking of Synopsys, since they now since a couple of years fully
> supports Solaris on x64 has Xilinx any plans/discussions about that to?
>
> /michael- Hide quoted text -
>
> - Show quoted text -

Support for operating systems beyond Linux and Windows are not on our
product roadmaps.

Ed McGettigan
--
Xilinx Inc.

Article: 153132
Subject: Re: Horsepower On Tap
From: "John Speth" <johnspeth@yahoo.com>
Date: Thu, 8 Dec 2011 17:48:26 -0800
Links: << >> << T >> << A >>

Wasn't there a short lived push by EDA companies about 10 years ago to 
provide internet services in which the number crunching was done by their 
server while you entered and submitted your design using their software?  I 
seem to remember that it was back in the day when we paid huge amounts of 
money for complete design and build tools and did it all ourselves.  It was 
the pay as you go model. Perhaps the need has resurfaced.  It seems to me if 
you can get a build 10 times faster for a buck or two a run, it'll be cost 
effective.

JJS

"Rob Gaddi"  wrote in message news:jbo99g$652$1@dont-email.me...

I was waiting for Quartus to finish crunching my latest build, and poking
around idly on NewEgg trying to see what it would cost to get a machine
with a little more juice to it.  I started thinking what a shame it was to
have to keep upgrading to the latest and greatest machine in order to
squeeze out some more clock cycles for big builds.  And then I started
thinking about Amazon EC2.

The idea behind EC2 is that Amazon runs virtual machines for you, and you
pay them by the hour for their use.  Use of an "Extra Large High-Memory
Instance" running RHEL would run $0.63 an hour.  It's the new spin on the
old "timeshare the supercomputer" concept.  This seems like a handy way to
get a beast of a computer when I need to do big builds and/or long
simulation runs without having to keep upgrading my core machine.

Has anyone tried this out to see if it works in practice?  http://
moxielogic.org/blog/?p=450 says he had serious trouble with it, but that's
from a year ago.  Ideally, anyone with experience trying this with Quartus,
but ISE, Modelsim, Rivera, etc would all be interesting.

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

Article: 153133
Subject: Re: Horsepower On Tap
From: "jt_eaton" <z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Thu, 08 Dec 2011 22:46:00 -0600
Links: << >> << T >> << A >>

>Wasn't there a short lived push by EDA companies about 10 years ago to 
>provide internet services in which the number crunching was done by their

>server while you entered and submitted your design using their software? 
I 
>seem to remember that it was back in the day when we paid huge amounts of

>money for complete design and build tools and did it all ourselves.  It
was 
>the pay as you go model. Perhaps the need has resurfaced.  It seems to me
if 
>you can get a build 10 times faster for a buck or two a run, it'll be cost

>effective.
>
>JJS
>
>

Yes, It ended when all of their customers told them that they would would 
never let them see any of their IP.

The problem with running in the cloud is that they have to create a image
and
run it with root access open to the world so that the customer can control
it.

Well so can anyone else who can guess it's password. It's really nice if
root
has to be sitting by the box in order to get it.


John Eaton
	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 153134
Subject: Re: Horsepower On Tap
From: Michael Laajanen <michael_laajanen@yahoo.com>
Date: Fri, 09 Dec 2011 09:43:17 +0100
Links: << >> << T >> << A >>

Hi,

jt_eaton skrev 2011-12-09 05:46:
>> Wasn't there a short lived push by EDA companies about 10 years ago to
>> provide internet services in which the number crunching was done by their
>
>> server while you entered and submitted your design using their software?
> I
>> seem to remember that it was back in the day when we paid huge amounts of
>
>> money for complete design and build tools and did it all ourselves.  It
> was
>> the pay as you go model. Perhaps the need has resurfaced.  It seems to me
> if
>> you can get a build 10 times faster for a buck or two a run, it'll be cost
>
>> effective.
>>
>> JJS
>>
>>
>
> Yes, It ended when all of their customers told them that they would would
> never let them see any of their IP.
>
> The problem with running in the cloud is that they have to create a image
> and
> run it with root access open to the world so that the customer can control
> it.
>
> Well so can anyone else who can guess it's password. It's really nice if
> root
> has to be sitting by the box in order to get it.
>
>
> John Eaton
> 	
That you dont have to do, why do you say so?


/michael

Article: 153135
Subject: Need Clocked 1.5+Ghz LVDS buffer. Or bright ideas!
From: cwthomas@bittware.com
Date: Fri, 9 Dec 2011 11:18:47 -0800 (PST)
Links: << >> << T >> << A >>


HI Folks;


I've been asked to design a VITA57 board. I need to loop back all LA
and HA signals as 2.5 volt LVDS.


My customer has given me the following requirements:

Carrier board has 144 bidirectional signals configurable as both LVDS
xmitters and LVDS receivers.
They want to loop  back 72 signals as Soource synch. xmitters tied to
the other 72 as receivers.Then they want to flip the whole
works and flow the data in the opposite direction to validate that all
signals will function both as receivers or transmitters.
Unfortunately this thing needs to operate at 1.6Ghz clock rate.
Flipping the direction must be done via signal, since I cant touch the
board because it will be in an environmental chamber. Also making 2
versions to cover both directions is undesirable.
Other encouraging goodies:

1) I can not use an FPGA.

2) This thing has to fit on a 2.4 * 2.7 inch board

3) the signals already have to go thru a connector and have stubs,
some as long as 16mm on the carrier side.
 so I'm looking to keep any stubs down.


Ive been looking at Crosspoint switches but am concerned that I really
should reclock the data, not just hope the cross point switch cleans
it up.


Any Ideas (any) are greatly appreciated.


Thanks Folks;


C.W. Thomas

Article: 153136
Subject: Lattice buys SiBlue for $62 million
From: rickman <gnuarm@gmail.com>
Date: Fri, 9 Dec 2011 16:30:48 -0800 (PST)
Links: << >> << T >> << A >>

I think this will be one of the more significant semiconductor
acquisitions of the year.

http://www.fpgagurus.edn.com/blog/fpga-gurus-blog/lattice-picks-siliconblue-62-million

I've been using Lattice parts for the last few years and I plan to be
using SiBlue parts this coming year.

I see that a SiBlue part is being used in a watch by Citizen.

http://www.embedded.com/electronics-blogs/other/4231148/Cool-Beans--First-FPGA-in-a-watch-

I believe the ultimate market for FPGAs will be low cost, high volume
devices like this.  Sooner or later this low power technology will be
combined with the analog functionality of the Cypress and Actel
devices.

Rick

Article: 153137
Subject: Re: Lattice buys SiBlue for $62 million
From: Jim Granville <j.m.granville@gmail.com>
Date: Fri, 9 Dec 2011 21:15:21 -0800 (PST)
Links: << >> << T >> << A >>

On Dec 10, 1:30=A0pm, rickman <gnu...@gmail.com> wrote:
> I think this will be one of the more significant semiconductor
> acquisitions of the year.
>
> http://www.fpgagurus.edn.com/blog/fpga-gurus-blog/lattice-picks-silic...
>
> I've been using Lattice parts for the last few years and I plan to be
> using SiBlue parts this coming year.
>
> I see that a SiBlue part is being used in a watch by Citizen.
>
> http://www.embedded.com/electronics-blogs/other/4231148/Cool-Beans--F...
>
> I believe the ultimate market for FPGAs will be low cost, high volume
> devices like this. =A0Sooner or later this low power technology will be
> combined with the analog functionality of the Cypress and Actel
> devices.
>
> Rick

Certainly an Interesting move.
Lattice have been slow releasing their MachXO2 family, and have just
added one MLF package.
Their smallest MachXO2 BGA package certainly indicates a small die, so
we would like to see more MLF packages.
Prices indicated on the smaller siblings of the MachXo2 are also
higher than the Logic ratio would infer

Could take a while to merge the two offerings, and quite a but of
overlap.

-jg

Article: 153138
Subject: Re: Lattice buys SiBlue for $62 million
From: rickman <gnuarm@gmail.com>
Date: Sat, 10 Dec 2011 16:52:42 -0800 (PST)
Links: << >> << T >> << A >>

On Dec 10, 12:15=A0am, Jim Granville <j.m.granvi...@gmail.com> wrote:
> On Dec 10, 1:30=A0pm, rickman <gnu...@gmail.com> wrote:
>
>
>
>
>
>
>
>
>
> > I think this will be one of the more significant semiconductor
> > acquisitions of the year.
>
> >http://www.fpgagurus.edn.com/blog/fpga-gurus-blog/lattice-picks-silic...
>
> > I've been using Lattice parts for the last few years and I plan to be
> > using SiBlue parts this coming year.
>
> > I see that a SiBlue part is being used in a watch by Citizen.
>
> >http://www.embedded.com/electronics-blogs/other/4231148/Cool-Beans--F...
>
> > I believe the ultimate market for FPGAs will be low cost, high volume
> > devices like this. =A0Sooner or later this low power technology will be
> > combined with the analog functionality of the Cypress and Actel
> > devices.
>
> > Rick
>
> Certainly an Interesting move.
> Lattice have been slow releasing their MachXO2 family, and have just
> added one MLF package.
> Their smallest MachXO2 BGA package certainly indicates a small die, so
> we would like to see more MLF packages.
> Prices indicated on the smaller siblings of the MachXo2 are also
> higher than the Logic ratio would infer
>
> Could take a while to merge the two offerings, and quite a but of
> overlap.
>
> -jg

I don't expect they will push to merge product lines.  Those products
were conceived as viable products competing with the market as a whole
and I expect they will continue them as such.  I guess you are really
suggesting that the next generation might be a combined family
combining the best features of each.  That may be.  I don't know what
compromises SiBlue had to make to get the low power.  I know their
part is ram backed up with one time programmable memory rather than
flash.  That certainly has good utility, but flash is always better.
Any board I design with the SiBlue part will have an SPI flash on it
while my designs with the Lattice XP parts don't.

Otherwise I don't know what shortcomings the SiBlue parts have.

Rick

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