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Messages from 154175

Article: 154175
Subject: fractional radix agnostic calculator tool?
From: "Morten Leikvoll" <mleikvol@yahoo.nospam>
Date: Tue, 28 Aug 2012 10:36:02 +0200
Links: << >>  << T >>  << A >>
Im looking for a desktop (win) traditional freeware caclulator that can also 
convert and handle fractional numbers across different radixes.
The builtin winxp and win7 tools are great, but have no support for 
fractional numbers on non radix10. Any suggestions?


Article: 154176
Subject: Re: recruit FPGA design engineer in Scotland
From: Brian Drummond <brian@shapes.demon.co.uk>
Date: Tue, 28 Aug 2012 10:30:13 +0000 (UTC)
Links: << >>  << T >>  << A >>
On Mon, 27 Aug 2012 23:45:55 +0000, glen herrmannsfeldt wrote:

> All the TV ads about government bureaucrats making health care
> decisions, (to convince people that government is bad), but I would
> rather that than some corporate CEO whose year end bonus depends on how
> many patients' claims were denied.

I suppose it depends who the bureaucrats are!
I looked into one example during all that shouting how bad the NHS was as 
an example of public healthcare. The bureaucrats (aka "NICE") published 
the names on the panel deciding the merits of the treatment concerned... 
Leading doctors and surgeons, research chemists, professors of medicine. 
Not a beancounter or (as far as I could see) paper pusher among them.

Can your health insurance companies say as much?

From this side of the water, it's difficult to see what all the Obamacare 
fuss is about. 

- Brian

Article: 154177
Subject: Re: recruit FPGA design engineer in Scotland
From: Mike Perkins <spam@spam.com>
Date: Tue, 28 Aug 2012 12:12:12 +0100
Links: << >>  << T >>  << A >>
On 28/08/2012 11:30, Brian Drummond wrote:
> On Mon, 27 Aug 2012 23:45:55 +0000, glen herrmannsfeldt wrote:
>
>> All the TV ads about government bureaucrats making health care
>> decisions, (to convince people that government is bad), but I would
>> rather that than some corporate CEO whose year end bonus depends on how
>> many patients' claims were denied.
>
> I suppose it depends who the bureaucrats are!
> I looked into one example during all that shouting how bad the NHS was as
> an example of public healthcare. The bureaucrats (aka "NICE") published
> the names on the panel deciding the merits of the treatment concerned...
> Leading doctors and surgeons, research chemists, professors of medicine.
> Not a beancounter or (as far as I could see) paper pusher among them.
>
> Can your health insurance companies say as much?
>
>  From this side of the water, it's difficult to see what all the Obamacare
> fuss is about.
>
> - Brian
>

I think this might give a clue:

According to a report by Health Care for America Now, America's five 
biggest for-profit health insurance companies ended 2009 with a combined 
profit of $12.2 billion

That can pay for a lot of opposition!!

-- 
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk

Article: 154178
Subject: Re: recruit FPGA design engineer in Scotland
From: rickman <gnuarm@gmail.com>
Date: Tue, 28 Aug 2012 11:55:23 -0400
Links: << >>  << T >>  << A >>
On 8/27/2012 7:45 PM, glen herrmannsfeldt wrote:
> rickman<gnuarm@gmail.com>  wrote:
>
> (snip)
>> "Careful"?  I'm not sure what that means.  I can't even get insurance
>> here except for Maryland offering the new "Affordable Healthcare Act"
>> policy.  In the neighboring Virginia and West Virginia you can't get
>> insurance at all if you have pre-existing conditions.
>
>> I don't want to turn this into an insurance debate, but the difficulty
>> of finding health insurance outside of an employment group is the single
>> biggest failing of this government in the last forty years. Well, except
>> for a war or two we never needed.
>
> I don't want a health care debate either, but it doesn't seem
> fair to blame the government. Well, we will have to see how
> Obamacare works out, but before that there was pretty much no
> government in healthcare. (Not counting Medicare and such.)
>
> Most likely it will still need some adjusting, but it seems to
> me that Obamacare is a step in the right direction.
>
> All the TV ads about government bureaucrats making health care
> decisions, (to convince people that government is bad), but I
> would rather that than some corporate CEO whose year end
> bonus depends on how many patients' claims were denied.
>
> Note that Obamacare was modeled after the system that Romney
> started in MA, and yet he is against it!
>
> -- glen

As we tread further into a discussion we both acknowledge we don't 
want... the reason we need the government to get involved in healthcare 
is because that is the only way this country will ever be able to 
provide healthcare to the full population rather than just those who 
have the sort of jobs that provide insurance or those who can pay for 
healthcare out of pocket.  That latter group includes Bill Gates and 
Warren Buffet and that may be the full list. <g>

I firmly believe that the real reason healthcare is not available to 
many is because it is for-profit based.  That goes directly against the 
goals of universal healthcare because it goes against maximizing profit. 
  The only way this country will ever be able to afford universal 
healthcare is to adopt a national healthcare system like so many other 
countries have.  But this will be fought tooth and nail by everyone who 
has a profit motive in healthcare, doctors, other caregivers, insurance 
companies, drug companies, etc.

Of course all the associated rhetoric will polarize the voters and widen 
the schism already existing in politics.  I don't relish the future.

Rick

Article: 154179
Subject: Cross-vendor firmware design management environment
From: Jaco Naude <naude.jaco@gmail.com>
Date: Wed, 29 Aug 2012 08:58:40 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi

We have developed a cross-vendor firmware design management environment in =
our team. It integrates and sync's with many design environments (Sigasi, M=
entor Graphics HDL Author etc) and takes care of the full implementation pr=
ocesses for multiple back-ends (Xilinx, Altera, Plunify etc.). It operates =
on something we call "file association databases". These databases are simp=
le XML files containing details about file types used in the firmware world=
. The idea is that they can evolve over time through knowledge added to the=
m by experts in the field. At present, they cover Xilinx, Altera and Mentor=
 Graphics tools.=20

The knowledge contained in these databases allows us to perform advanced op=
erations on the files in a design. It knows which files are generated etc, =
allowing you to for example clean designs. Furthermore it can enforce direc=
tory structures and along with this it knows what needs to end up in versio=
n controlled repositories and what needs to stay out. This is very powerful=
, for example it allows you to do version control consistently across teams=
. If you are an IP core provider, it will for example allows you to package=
 your cores in a consistent way with little effort.

We've been using and tweaking it for about 2 years now so the result is a l=
ong list of features that is really useful to a firmware designer and we th=
ink that it will be useful to other firmware designers out there. At the mo=
ment we are not sure if we are going to open source it, or if we are going =
to take a different route.=20

We would like your feedback to help us determine if there is a need for suc=
h a tool externally.
More information about the project can be found at: http://scineric.csir.co=
.za.
A detailed blog post about the file association database solution can be fo=
und here: http://scineric.csir.co.za/?p=3D1083

Thanks,
Jaco

Article: 154180
Subject: =?UTF-8?Q?Simulating_fixed_point_multiplica=E2=80=8Btion_using_float?=
From: Vivek Menon <vivek.menon79@gmail.com>
Date: Wed, 29 Aug 2012 10:39:12 -0700 (PDT)
Links: << >>  << T >>  << A >>
I am prototyping an algorithm using floating point and fixed point precisio=
n. I used the floating point core v 5.0 to generate a multiplier for single=
 precision multiplication and fixed point multiplication (custom width 16 b=
its with 11 bits fraction). I am able to successfully simulate and synthesi=
ze the floating point multiplier, but the fixed point core just fails. I am=
 using ISIM to simulate the fixed point core.

I verified my input and output values in Matlab using quantizer function to=
 select the Q point (11 bits fraction).

e.g. I apply x01C9 (0.2232) and x06ED (0.8660) to my fixed point multiplier=
, and I see my output as x0000, whereas I am supposed to see x018B (0.1933)=
. I don't see the overflow or underflow signal going high.


Any suggestions??

Thanks in advance

Article: 154181
Subject: Re: Simulating fixed point =?windows-1252?Q?multiplication_usi?=
From: Gabor <gabor@szakacs.invalid>
Date: Wed, 29 Aug 2012 13:44:49 -0400
Links: << >>  << T >>  << A >>
Vivek Menon wrote:
> I am prototyping an algorithm using floating point and fixed point precision. I used the floating point core v 5.0 to generate a multiplier for single precision multiplication and fixed point multiplication (custom width 16 bits with 11 bits fraction). I am able to successfully simulate and synthesize the floating point multiplier, but the fixed point core just fails. I am using ISIM to simulate the fixed point core.
> 
> I verified my input and output values in Matlab using quantizer function to select the Q point (11 bits fraction).
> 
> e.g. I apply x01C9 (0.2232) and x06ED (0.8660) to my fixed point multiplier, and I see my output as x0000, whereas I am supposed to see x018B (0.1933). I don't see the overflow or underflow signal going high.
> 
> 
> Any suggestions??
> 
> Thanks in advance

It sounds like you may be looking at the wrong output bits of your
multiplier.  If you add something to the left of the radix point do
you get a non-zero output?

-- Gabor

Article: 154182
Subject: Re: Simulating fixed point multiplica???tion using floating point core v5.0 on Virtex-6 LX75T ISE 13.4
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Wed, 29 Aug 2012 18:47:37 +0000 (UTC)
Links: << >>  << T >>  << A >>
Vivek Menon <vivek.menon79@gmail.com> wrote:
> I am prototyping an algorithm using floating point and fixed 
> point precision. I used the floating point core v 5.0 to 
> generate a multiplier for single precision multiplication and 
> fixed point multiplication (custom width 16 bits with 11 bits 
> fraction). I am able to successfully simulate and synthesize 
> the floating point multiplier, but the fixed point core just 
> fails. I am using ISIM to simulate the fixed point core.

> I verified my input and output values in Matlab using quantizer 
> function to select the Q point (11 bits fraction).

A multiplier with 16 bit inputs should generate a 32 bit product.

For addition, you likely would be adding two numbers with
the same number of fractions bits, but for multiply they are
often different. You have to select the appropriate fraction
bits based on the fraction bits of the inputs.

> e.g. I apply x01C9 (0.2232) and x06ED (0.8660) to my fixed point 
> multiplier, and I see my output as x0000, whereas I am 
> supposed to see x018B (0.1933). I don't see the overflow or 
> underflow signal going high.

-- glen

Article: 154183
Subject: General Build Question
From: Rob Gaddi <rgaddi@technologyhighland.invalid>
Date: Thu, 30 Aug 2012 09:59:44 -0700
Links: << >>  << T >>  << A >>
Here's a sort of a general toss-out.  When I'm writing code in C, one
of my rules is that I turn on -Wall (and a mess of other warnings) and
I won't ship until I've got 0 warnings in the build.

I've never managed to follow a similar pattern on my FPGA designs.  Both
on Xilinx and Altera I always get 4 gillion warnings, all of
them trivial.  So I glance through the list, looking for anything that
looks serious, but that process is both exhausting and not rigorous.
Does anyone actually manage to get their FPGA builds to a zero warning
state?  Or is that yet another way in which FPGA design
tools get circles run around them by software design tools?

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

Article: 154184
Subject: Re: General Build Question
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Thu, 30 Aug 2012 19:33:35 +0000 (UTC)
Links: << >>  << T >>  << A >>
Rob Gaddi <rgaddi@technologyhighland.invalid> wrote:
> Here's a sort of a general toss-out.  When I'm writing code in C, one
> of my rules is that I turn on -Wall (and a mess of other warnings) and
> I won't ship until I've got 0 warnings in the build.

People keep adding more warnings, just in case.

Enough that I have found rules like yours to be too strict.

> I've never managed to follow a similar pattern on my FPGA designs.  
> Both on Xilinx and Altera I always get 4 gillion warnings, all of
> them trivial.  So I glance through the list, looking for anything that
> looks serious, but that process is both exhausting and not rigorous.
> Does anyone actually manage to get their FPGA builds to a zero warning
> state?  Or is that yet another way in which FPGA design
> tools get circles run around them by software design tools?

One difference with the usual FPGA tools is that they do the
processiing in stages. Some of the warnigns might complain about
effects due to processing in earlier stages. 

If there are some warnings that you know that you don't need
to worry about, then I would use "grep -v" on the file before
looking, so that I wouldn't see useless ones.

-- glen

Article: 154185
Subject: Re: General Build Question
From: Gabor <gabor@szakacs.invalid>
Date: Thu, 30 Aug 2012 17:11:34 -0400
Links: << >>  << T >>  << A >>
glen herrmannsfeldt wrote:
> Rob Gaddi <rgaddi@technologyhighland.invalid> wrote:
>> Here's a sort of a general toss-out.  When I'm writing code in C, one
>> of my rules is that I turn on -Wall (and a mess of other warnings) and
>> I won't ship until I've got 0 warnings in the build.
> 
> People keep adding more warnings, just in case.
> 
> Enough that I have found rules like yours to be too strict.
> 
>> I've never managed to follow a similar pattern on my FPGA designs.  
>> Both on Xilinx and Altera I always get 4 gillion warnings, all of
>> them trivial.  So I glance through the list, looking for anything that
>> looks serious, but that process is both exhausting and not rigorous.
>> Does anyone actually manage to get their FPGA builds to a zero warning
>> state?  Or is that yet another way in which FPGA design
>> tools get circles run around them by software design tools?
> 
> One difference with the usual FPGA tools is that they do the
> processiing in stages. Some of the warnigns might complain about
> effects due to processing in earlier stages. 
> 
> If there are some warnings that you know that you don't need
> to worry about, then I would use "grep -v" on the file before
> looking, so that I wouldn't see useless ones.
> 
> -- glen

At least for Xilinx, the grep feature is built-in as "Message Filtering"
which helps you to ignore warnings you consider trivial.  I find that
warnings in behavioral simulation - whether ModelSim or ISIM - are
generally of the type you should not ignore.  So I make sure I don't
have warnings when I compile for simulation, then look through the
filtered warnings for synthesis.

Another thing I do, since I use Verilog, is to always use:
`default_nettype none
which promotes a lot of connectivity warnings to errors.

-- Gabor

Article: 154186
Subject: Problem using virtex 4 and virtex 6 ibis models
From: "firefly" <3615@embeddedrelated>
Date: Fri, 31 Aug 2012 11:30:23 -0500
Links: << >>  << T >>  << A >>
 I am facing some problems while using IBIS models in hyperlynx. I have to
analyze a clock signal coming from 60MHz crystal oscillator and going to
virtex 4 FPGA with part number (XC4VLX60-11FF1148) at pins AD17 and AE17
and then from vertix 4 the signal is going to Virtex 6 FPGA with part
number (XC6VLX365T-FF1156) at pins G9 and H9. I downloaded IBIS models of
virtex 4 and virtex 6 from the xilinx website. Now I am facing problem
which pin of IBIS model I should assign. The pins given in IBIS model files
are different from these part number which I am using. I want to know
either these models are correct for these part number? what should I do
now?

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 154187
Subject: Delay in Verilog for Asics design which is synthesizable
From: "mike12" <3623@embeddedrelated>
Date: Fri, 31 Aug 2012 11:30:36 -0500
Links: << >>  << T >>  << A >>
Can any help me for adding a simple delay of 10ns or more in verilog code
which is synthesizable for asics design......
As #10ns etc are not synthesizable.. 

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 154188
Subject: Unconnected Done pin Virtex 6
From: "frapa" <3669@embeddedrelated>
Date: Fri, 31 Aug 2012 11:30:51 -0500
Links: << >>  << T >>  << A >>
Hello,

I just received my first FPGA board designed for work, and we have an issue
regarding configuration of FPGA.

The JTAG chain passed all tests, and the programming proccess starts well
(iMPACT)
The issue is an error in status register at the end of programming  is
returned by iMPACT. Done signal is not high, and I remember now we missed
to connect this pin. Actually, on my board, Done pin is floatting..... 

Is there a link between these two thinks?

What is the workaround? hard / soft

Thanks for your help.

frapa

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 154189
Subject: Re: Delay in Verilog for Asics design which is synthesizable
From: Rob Gaddi <rgaddi@technologyhighland.invalid>
Date: Fri, 31 Aug 2012 09:58:22 -0700
Links: << >>  << T >>  << A >>
On Fri, 31 Aug 2012 11:30:36 -0500
"mike12" <3623@embeddedrelated> wrote:

> Can any help me for adding a simple delay of 10ns or more in verilog code
> which is synthesizable for asics design......
> As #10ns etc are not synthesizable.. 
> 
> 	   
> 					
> ---------------------------------------		
> Posted through http://www.FPGARelated.com

Can you use a chain of flip-flops, or some other digitally quantized
thing?  If not, then the answer is that you'll have to engage in analog
trickery; VCC servoed inverter chains or the like.

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

Article: 154190
Subject: Re: Unconnected Done pin Virtex 6
From: Gabor <gabor@szakacs.invalid>
Date: Fri, 31 Aug 2012 13:54:25 -0400
Links: << >>  << T >>  << A >>
frapa wrote:
> Hello,
> 
> I just received my first FPGA board designed for work, and we have an issue
> regarding configuration of FPGA.
> 
> The JTAG chain passed all tests, and the programming proccess starts well
> (iMPACT)
> The issue is an error in status register at the end of programming  is
> returned by iMPACT. Done signal is not high, and I remember now we missed
> to connect this pin. Actually, on my board, Done pin is floatting..... 
> 
> Is there a link between these two thinks?
> 
> What is the workaround? hard / soft
> 
> Thanks for your help.
> 
> frapa
> 
> 	   
> 					
> ---------------------------------------		
> Posted through http://www.FPGARelated.com

Looks similar to this thread on the Xilinx forums:

http://forums.xilinx.com/t5/General-Technical-Discussion/Virtex-6-programming-issue-Done-pin/m-p/257564

If it's really just the DONE pin, you can drive the DONE pin high
by setting the "-g DriveDone" option for bitgen (From the GUI
go to "Generate Programming File" properties, Startup Options,
Drive Done Pin High).

Unfortunately any failure in configuration results in DONE not
going high, so you may find that this is only a small part of your
problems.

-- Gabor

Article: 154191
Subject: Re: General Build Question
From: Christopher Felton <abc@def.org>
Date: Fri, 31 Aug 2012 20:44:36 -0500
Links: << >>  << T >>  << A >>
<snip>
 >>
 >> At least for Xilinx, the grep feature is built-in as "Message
 >> Filtering"
 >> which helps you to ignore warnings you consider trivial.  I find that
 >> warnings in behavioral simulation - whether ModelSim or ISIM - are
 >> generally of the type you should not ignore.  So I make sure I don't
 >> have warnings when I compile for simulation, then look through the
 >> filtered warnings for synthesis.

I agree, I follow the same, 0 warnings for simulation.  Some
simulators have -lint for extra warnings as well.

 >>
 >> Another thing I do, since I use Verilog, is to always use:
 >> `default_nettype none
 >> which promotes a lot of connectivity warnings to errors.
 >>
 >> -- Gabor

Yup, that is another good habit that we use as well.

Chris


Article: 154192
Subject: Re: General Build Question
From: "Andrew Holme" <ah@nospam.com>
Date: Sun, 2 Sep 2012 13:53:39 +0100
Links: << >>  << T >>  << A >>
"Rob Gaddi"  wrote in message 
news:20120830095944.3105154b@rg.highlandtechnology.com...

>Here's a sort of a general toss-out.  When I'm writing code in C, one
>of my rules is that I turn on -Wall (and a mess of other warnings) and
>I won't ship until I've got 0 warnings in the build.

>I've never managed to follow a similar pattern on my FPGA designs.  Both
>on Xilinx and Altera I always get 4 gillion warnings, all of them trivial.

I was just thinking about this recently myself.  I got my latest Xilinx FPGA 
project down to 23 warnings but I can't shift any more.



Article: 154193
Subject: Re: Delay in Verilog for Asics design which is synthesizable
From: "Morten Leikvoll" <mleikvol@yahoo.nospam>
Date: Mon, 3 Sep 2012 08:37:22 +0200
Links: << >>  << T >>  << A >>
>Can any help me for adding a simple delay of 10ns or more in verilog code
>which is synthesizable for asics design......
>As #10ns etc are not synthesizable..

First answer is just "NO". There is no way to do it, and there should be no 
need for it on a proper synchronous design.
Using combinatorical delays is a really bad solution because it will be 
dependant on fpga batch, environment (temperature, voltages), and internal 
routing. You simply have very low guarantee that it will work on your next 
design, or even tomorrow, when the wind has turned.

Second answer is "maybe".. if you have a DLL and a known clock available, 
you may use the DLL's delay taps to generate it, but there should still be 
no need for it.

Maybe you should explain why you need it? If its for i/o timing adjustments 
of very few signals, I would recommend external passive delay lines, like 
http://www.digikey.com/product-detail/en/DS1L5VJA00S-C/408-1122-ND/966403 . 
As you see, they are not cheap. Also you need to be extra careful with 
impedance matching on your pcb.

I have used with success a similar (but smd from Murata) 1.0ns delay on the 
clock to get timing right for an external DVI transmitter chip.


Article: 154194
Subject: Re: Delay in Verilog for Asics design which is synthesizable
From: hal-usenet@ip-64-139-1-69.sjc.megapath.net (Hal Murray)
Date: Mon, 03 Sep 2012 03:40:21 -0500
Links: << >>  << T >>  << A >>
In article <na2dnSGNAKG8zdnNnZ2dnUVZ8hmdnZ2d@lyse.net>,

>I have used with success a similar (but smd from Murata) 1.0ns delay on the 
>clock to get timing right for an external DVI transmitter chip.

1 ns is only 6 inches of routing.

-- 
These are my opinions.  I hate spam.


Article: 154195
Subject: Re: Delay in Verilog for Asics design which is synthesizable
From: "Morten Leikvoll" <mleikvol@yahoo.nospam>
Date: Mon, 3 Sep 2012 13:30:43 +0200
Links: << >>  << T >>  << A >>
>>I have used with success a similar (but smd from Murata) 1.0ns delay on 
>>the
>>clock to get timing right for an external DVI transmitter chip.

>1 ns is only 6 inches of routing.

True, but to be honest I didnt know the delay when pcb routing so I added 
this general delay device and experimented.. (The chips datasheet does not 
come with timing(!), only a reference to the SDVO (Intel) spec wich is not 
public. Also, this carries up to 165Mhz clk, so I didn't want antenna 
problems. At that specific design I didnt have a DLL available to tune it 
either.


Article: 154196
Subject: Re: Delay in Verilog for Asics design which is synthesizable
From: "Morten Leikvoll" <mleikvol@yahoo.nospam>
Date: Mon, 3 Sep 2012 13:37:47 +0200
Links: << >>  << T >>  << A >>
>>>I have used with success a similar (but smd from Murata) 1.0ns delay on 
>>>the
>>>clock to get timing right for an external DVI transmitter chip.

>>1 ns is only 6 inches of routing.

>True, but to be honest I didnt know the delay when pcb routing so I added 
>this general delay device and experimented.. (The chips datasheet does not 
>come with timing(!), only a reference to the SDVO (Intel) spec wich is not 
>public. Also, this carries up to 165Mhz clk, so I didn't want antenna 
>problems. At that specific design I didnt have a DLL available to tune it 
>either.

Correction.. If any interest, it was the DVO spec, not SDVO.. And the chip 
was the Sii 1178 in low swing mode.


Article: 154197
Subject: Re: Delay in Verilog for Asics design which is synthesizable
From: Jon <jon@beniston.com>
Date: Wed, 5 Sep 2012 15:08:53 -0700 (PDT)
Links: << >>  << T >>  << A >>
> First answer is just "NO". There is no way to do it, and there should be =
no=20
>=20
> need for it on a proper synchronous design.

But if you really need to...

Instantiate a chain of buffers or delay cells. You wont be able to get a fi=
xed delay of 10ns, but you maybe able to get at least 10ns (but it will mos=
t likely be more). The exact cell name will depend upon the cell library yo=
u are using. (For ARM libs, you'd want BUFXN or DLYXN).

For the instance names of the cells, add a pattern such as dont_touch to th=
e instance name. E.g.

BUFX4 u_buf_1_dont_touch (.Y(t), .A(in));
BUFX4 u_buf_2_dont_touch (.Y(out), .A(t));

If you are using Design Compiler for synthesis, execute the following comma=
nd after elaboration to prevent it from modifying them during synthesis:

set_dont_touch [get_cells -hier *dont_touch*]

If using RTL Compiler, you need to use set_attribute preserve.

Cheers,
Jon

Article: 154198
Subject: Verilog file operations
From: "maxascent" <56@embeddedrelated>
Date: Fri, 07 Sep 2012 07:21:47 -0500
Links: << >>  << T >>  << A >>
Hi

I want to write some data to a file using Verilog. This file will be a JPEG
file so the data in the file needs to be the actual data I write. I have
tried using $fwrite but the data ends up as ASCII when I look at it in a
hex editor. So if I write 0xFF it ends up as 66 66 in the file. Can anyone
tell me how to do this?

Thanks

Jon	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 154199
Subject: Re: Verilog file operations
From: "Morten Leikvoll" <mleikvol@yahoo.nospam>
Date: Fri, 7 Sep 2012 14:42:27 +0200
Links: << >>  << T >>  << A >>
>I want to write some data to a file using Verilog. This file will be a JPEG
>file so the data in the file needs to be the actual data I write. I have
>tried using $fwrite but the data ends up as ASCII when I look at it in a
>hex editor. So if I write 0xFF it ends up as 66 66 in the file. Can anyone
>tell me how to do this?

Try google.. here is what I found (last post using character binary mode)
http://www.velocityreviews.com/forums/t22651-binary-file-io-in-modelsim.html




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