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Messages from 156325

Article: 156325
Subject: Re: Oberon Operating System + Compiler + Graphic on a Spartan 3 FPGA
From: "MGreim" <99555@embeddedrelated>
Date: Fri, 07 Mar 2014 11:28:47 -0600
Links: << >>  << T >>  << A >>
>If you manage to get this running on a more modern Xilinx Eval board, 
>please let us know -- I would love to try it out.  Everything that I 
>have every seen from Niklaus Wirth has been excellent.
>
>On 03/05/2014 01:04 AM, rupertlssmith@googlemail.com wrote:
>> On Sunday, March 2, 2014 1:51:06 PM UTC, MGreim wrote:
>>> http://www.projectoberon.com/
>>> Its a complete computer including a graphical operating system in a
small
>>> FPGA.
>>
>> Very cool. What is the daughter board for? If its just PS/2 mouse and SD
card connector, I have some more sophisticated Xilinx eval boards with
those already on them. It might not be too hard to get it running on one of
them.
>>
>> Rupert
>>
>

Rupert,
yes the daugtherboard has only a connector for the Mouse and a SD card
holder with a SD for the file system. 

Markus 	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 156326
Subject: license server
From: alb <al.basili@gmail.com>
Date: Mon, 10 Mar 2014 14:30:27 +0100
Links: << >>  << T >>  << A >>
Hi everyone,

is there any license server out there providing licenses on a 'per-use' 
base?

<background>
we have several licenses in house, mostly node-locked, some floating but 
in our FPGA design flow a great deal of the time is spent on a stupid 
editor (vhdl/verilog) with very little use of the license itself.
</background>

We were wondering whether exists some services which 'lend' the license 
on a 'per-use' base and is charged for the amount of *actual* time the 
license is used.

Any comment/idea/suggestion is appreciated.

Al

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 156327
Subject: cloud design flow
From: alb <al.basili@gmail.com>
Date: Mon, 10 Mar 2014 14:48:52 +0100
Links: << >>  << T >>  << A >>
Hi there,

I was wondering if there's any one out there working with a cloud design 
flow which is tool agnostic.

The reason for asking is that I'm trying to evaluate if there's a way to 
integrate the benefits of a cloud service (with more hardware resources 
than our inhouse ones) into our design flow.

We clearly noticed that several times our simulations would take too much 
time and we prefer to go directly to the bench in order to verify a 
specific function. This approach forces us to rely on the bench 
availability (which is not always granted) and may not always be efficient 
(we need to set up special configurations which gives us greater 
observability/controllability on the bench).

Another main advantage is the design space exploration: having much more 
power available would result in the possibility to throw more cpus at a 
specific problem, hence addressing the issue faster.

Last but not least, regression testing and automated testing can be a 
great advantage of moving to the cloud. Any new module/component which is 
ready to be integrated in the overall design can be automatically included 
in the regression suite which is regularly running and can spot early 
integration issues.

So far I've heard/read about 'Plunify', which supports the Quartus 
software in the cloud, but we are working with Microsemi (former Actel) 
devices and there's nothing available out of the box.

Should we set up the environment the hard way, i.e. a set of scripts to 
handle the flow remotely? This might require a great initial effort but it 
has the benefit that we know what we are doing and we can fix it anytime 
an issue arises (provided that the share of time devoted to fixing 
problems doesn't eat designing time!). Or maybe there are tools out there, 
or services, which are already providing such environments?

Ideas/comments/suggestions are more than welcome.
Cheers,

Al

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 156328
Subject: Re: license server
From: HT-Lab <hans64@htminuslab.com>
Date: Mon, 10 Mar 2014 14:17:00 +0000
Links: << >>  << T >>  << A >>
On 10/03/2014 13:30, alb wrote:
> Hi everyone,
>
> is there any license server out there providing licenses on a 'per-use'
> base?
>
> <background>
> we have several licenses in house, mostly node-locked, some floating but
> in our FPGA design flow a great deal of the time is spent on a stupid
> editor (vhdl/verilog) with very little use of the license itself.
> </background>
>
> We were wondering whether exists some services which 'lend' the license
> on a 'per-use' base and is charged for the amount of *actual* time the
> license is used.
>
> Any comment/idea/suggestion is appreciated.
>
> Al
>

Most vendors have a so called term license, that is you purchase a 
license for several month. This is relative expensive but might be a 
solution for you.

If you spend most of your time with an editor then get 1 license and 
share it amongst your engineers. You can install the license on a server 
and VNC into it, share a dongle etc.

Hans
www.ht-lab.com


Article: 156329
Subject: Re: license server
From: alb <al.basili@gmail.com>
Date: Mon, 10 Mar 2014 17:17:20 +0100
Links: << >>  << T >>  << A >>
On Mon, 10 Mar 2014, HT-Lab wrote:
Hi Hans,

> On 10/03/2014 13:30, alb wrote:
>> We were wondering whether exists some services which 'lend' the license
>> on a 'per-use' base and is charged for the amount of *actual* time the
>> license is used.
>
> Most vendors have a so called term license, that is you purchase a license 
> for several month. This is relative expensive but might be a solution for 
> you.

I was aware about this, but it does not solve the issue. The amount of 
projects we work on is sufficient to require a 'continuous' access to the 
licenses. Nevertheless the amount of sharing can be greatly optimized if 
there was a service which charged on per-use base.

>
> If you spend most of your time with an editor then get 1 license and share it 
> amongst your engineers. You can install the license on a server and VNC into 
> it, share a dongle etc.

sharing a dongle is something we do already (manually). Even if this is 
the case and the users were using it throughout the whole working day 
(which is not true) a dongle is grossly underused.

Maybe we should think about lending *our* licenses when we do not use them 
and make some profit out of them :-).

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 156330
Subject: Re: license server
From: HT-Lab <hans64@htminuslab.com>
Date: Mon, 10 Mar 2014 17:00:25 +0000
Links: << >>  << T >>  << A >>
On 10/03/2014 16:17, alb wrote:

Hi Alb,

> On Mon, 10 Mar 2014, HT-Lab wrote:
> Hi Hans,
>
>> On 10/03/2014 13:30, alb wrote:
>>> We were wondering whether exists some services which 'lend' the license
>>> on a 'per-use' base and is charged for the amount of *actual* time the
>>> license is used.
>>
>> Most vendors have a so called term license, that is you purchase a
>> license for several month. This is relative expensive but might be a
>> solution for you.
>
> I was aware about this, but it does not solve the issue. The amount of
> projects we work on is sufficient to require a 'continuous' access to
> the licenses. Nevertheless the amount of sharing can be greatly
> optimized if there was a service which charged on per-use base.

<realism>
If a per-use scheme would bring in any extra money then I am sure the 
EDA (or any other) industry will adopt it. Trying to get something 
supported which will bring in less money is never going to be easy ;-)
</realism>

>
>>
>> If you spend most of your time with an editor then get 1 license and
>> share it amongst your engineers. You can install the license on a
>> server and VNC into it, share a dongle etc.
>
> sharing a dongle is something we do already (manually).

You can share a dongle over the network, not sure how legal this is.

Even if this is
> the case and the users were using it throughout the whole working day
> (which is not true) a dongle is grossly underused.
>
> Maybe we should think about lending *our* licenses when we do not use
> them and make some profit out of them :-).

You will find yourself quickly in court.....

Regards,
Hans
www.ht-lab.com




Article: 156331
Subject: Re: license server
From: langwadt@fonz.dk
Date: Mon, 10 Mar 2014 16:15:01 -0700 (PDT)
Links: << >>  << T >>  << A >>
Den mandag den 10. marts 2014 18.00.25 UTC+1 skrev HT-Lab:
> On 10/03/2014 16:17, alb wrote:
> 
> 
> 
> Hi Alb,
> 
> 
> 
> > On Mon, 10 Mar 2014, HT-Lab wrote:
> 
> > Hi Hans,
> 
> >
> 
> >> On 10/03/2014 13:30, alb wrote:
> 
> >>> We were wondering whether exists some services which 'lend' the license
> 
> >>> on a 'per-use' base and is charged for the amount of *actual* time the
> 
> >>> license is used.
> 
> >>
> 
> >> Most vendors have a so called term license, that is you purchase a
> 
> >> license for several month. This is relative expensive but might be a
> 
> >> solution for you.
> 
> >
> 
> > I was aware about this, but it does not solve the issue. The amount of
> 
> > projects we work on is sufficient to require a 'continuous' access to
> 
> > the licenses. Nevertheless the amount of sharing can be greatly
> 
> > optimized if there was a service which charged on per-use base.
> 
> 
> 
> <realism>
> 
> If a per-use scheme would bring in any extra money then I am sure the 
> 
> EDA (or any other) industry will adopt it. Trying to get something 
> 
> supported which will bring in less money is never going to be easy ;-)
> 
> </realism>
> 
> 
> 
> >
> 
> >>
> 
> >> If you spend most of your time with an editor then get 1 license and
> 
> >> share it amongst your engineers. You can install the license on a
> 
> >> server and VNC into it, share a dongle etc.
> 
> >
> 
> > sharing a dongle is something we do already (manually).
> 
> 
> 
> You can share a dongle over the network, not sure how legal this is.
> 
> 
> 
> Even if this is
> 
> > the case and the users were using it throughout the whole working day
> 
> > (which is not true) a dongle is grossly underused.
> 
> >
> 
> > Maybe we should think about lending *our* licenses when we do not use
> 
> > them and make some profit out of them :-).
> 
> 
> 
> You will find yourself quickly in court.....
> 

yeh I seems to remember year ago someone tried to start service licenses sharing. With people in different time zones that would be pretty smart

It was quickly shot down, can't remember what big eda tool it was but I think there was something about not being allowed to use a license more than a mile from the company that bought it

-Lasse  


Article: 156332
Subject: Re: Ball-park price of Xilinx Virtex 7 FPGA?
From: jkrshnan.v@gmail.com
Date: Tue, 11 Mar 2014 00:49:16 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Tuesday, April 3, 2012 2:07:07 PM UTC+5:30, Uwe Bonnes wrote:
> Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote:
> 
> > Elam <elampooranan@gmail.com> wrote:
> 
> 
> 
> > > I understand that the price depends on the volume etc
> 
> > > but I would like to know the per unit price of Virtex 7 FPGA..
> 
> 
> 
> > > Any guesses..
> 
> 
> 
> > Search for XC7V on www.findchips.com.
> 
> 
> 
> No online availability for now. Prices last time I checked was up to 50 k$...
> 
> 
> 
> Bye
> 
> -- 
> 
> Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de
> 
> 
> 
> Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
> 
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

The prices indicated are for trays? How to identify a tray or single device from the part number ? And how do we know how many parts are there in one tray ?

Article: 156333
Subject: Re: license server
From: alb <al.basili@gmail.com>
Date: Tue, 11 Mar 2014 08:58:25 +0100
Links: << >>  << T >>  << A >>
On Mon, 10 Mar 2014, langwadt@fonz.dk wrote:
Hi Lasse,

> Den mandag den 10. marts 2014 18.00.25 UTC+1 skrev HT-Lab:
[]
>>> Maybe we should think about lending *our* licenses when we do not use
>>
>>> them and make some profit out of them :-).
>>
>>
>>
>> You will find yourself quickly in court.....
>>
>
> yeh I seems to remember year ago someone tried to start service licenses 
> sharing. With people in different time zones that would be pretty smart
>
> It was quickly shot down, can't remember what big eda tool it was but I 
> think there was something about not being allowed to use a license more 
> than a mile from the company that bought it

Damn it I think you are right! I used to have access to Cern licenses' 
pool but the maintainer warned me about using it only within the site 
/thanks/ to a clause mentioning some physical distance between the user 
and the license...

And what if I'm travelling around the globe but still want to have access 
to the license that I legitemely paid?

<rant mode on>
In a world where everything is connected I find these type of clauses a 
threat to individual's freedom. Imagine if you buy a pair of shoes that 
you can only wear within a single city, or a cup of coffee that you can 
only drink within 2 blocks from the coffee shop...
<rant mode off>

Article: 156334
Subject: Re: license server
From: HT-Lab <hans64@htminuslab.com>
Date: Tue, 11 Mar 2014 08:48:45 +0000
Links: << >>  << T >>  << A >>
On 11/03/2014 07:58, alb wrote:
> On Mon, 10 Mar 2014, langwadt@fonz.dk wrote:
> Hi Lasse,
>
>> Den mandag den 10. marts 2014 18.00.25 UTC+1 skrev HT-Lab:
> []
>>>> Maybe we should think about lending *our* licenses when we do not use
>>>
>>>> them and make some profit out of them :-).
>>>
>>>
>>>
>>> You will find yourself quickly in court.....
>>>
>>
>> yeh I seems to remember year ago someone tried to start service
>> licenses sharing. With people in different time zones that would be
>> pretty smart
>>
>> It was quickly shot down, can't remember what big eda tool it was but
>> I think there was something about not being allowed to use a license
>> more than a mile from the company that bought it
>
> Damn it I think you are right! I used to have access to Cern licenses'
> pool but the maintainer warned me about using it only within the site
> /thanks/ to a clause mentioning some physical distance between the user
> and the license...

He is right, the distance clause is there to prevent company A from 
sharing its license with company B next door.

>
> And what if I'm travelling around the globe but still want to have
> access to the license that I legitemely paid?

I just checked my Modelsim license agreement which states:

A site is restricted to a one-half mile (800meter) radius.  Customer may 
have Software temporarily used by an employee for telecommuting purposes 
from locations other than a Customer office, such as the employee's resi 
dence, an airport or hotel, provided that such employee's primary place 
of employment is the site where the Software is authorized for use.

So you are OK to use it on your travels (assuming you use Modelsim). I 
suspect that most EDA tools have a clause like this. Just make sure you 
have your dongle insured in case you loose it.

If you want to use licenses globally you have to pay for a WAN license.

Regards,
Hans.
www.ht-lab.com

>
> <rant mode on>
> In a world where everything is connected I find these type of clauses a
> threat to individual's freedom. Imagine if you buy a pair of shoes that
> you can only wear within a single city, or a cup of coffee that you can
> only drink within 2 blocks from the coffee shop...
> <rant mode off>


Article: 156335
Subject: Re: Ball-park price of Xilinx Virtex 7 FPGA?
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Tue, 11 Mar 2014 11:31:44 +0000 (UTC)
Links: << >>  << T >>  << A >>
jkrshnan.v@gmail.com wrote:
> On Tuesday, April 3, 2012 2:07:07 PM UTC+5:30, Uwe Bonnes wrote:
...
> > No online availability for now. Prices last time I checked was up 
> > to 50 k$.

Now 5k is a starting point...

> The prices indicated are for trays? How to identify a tray or single device 
> from the part number ? And how do we know how many parts are there in
> one tray ?

The prices are per part...
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 156336
Subject: Re: Ball-park price of Xilinx Virtex 7 FPGA?
From: GaborSzakacs <gabor@alacron.com>
Date: Tue, 11 Mar 2014 17:02:18 -0400
Links: << >>  << T >>  << A >>
Uwe Bonnes wrote:
> jkrshnan.v@gmail.com wrote:
>> On Tuesday, April 3, 2012 2:07:07 PM UTC+5:30, Uwe Bonnes wrote:
> ...
>>> No online availability for now. Prices last time I checked was up 
>>> to 50 k$.
> 
> Now 5k is a starting point...
> 
>> The prices indicated are for trays? How to identify a tray or single device 
>> from the part number ? And how do we know how many parts are there in
>> one tray ?
> 
> The prices are per part...

A quick DigiKey search showed a range of $2,583.75 (XC7VX330T-1FFG1157C)
to $39,452.40 (XC7V2000T-G2FLG1925E).  These won't end up in any of my
designs any time soon.

-- 
Gabor

Article: 156337
Subject: Re: Ball-park price of Xilinx Virtex 7 FPGA?
From: Jon Elson <jmelson@wustl.edu>
Date: Tue, 11 Mar 2014 16:23:36 -0500
Links: << >>  << T >>  << A >>
GaborSzakacs wrote:


> 
> A quick DigiKey search showed a range of $2,583.75 (XC7VX330T-1FFG1157C)
> to $39,452.40 (XC7V2000T-G2FLG1925E).  These won't end up in any of my
> designs any time soon.
> 
REALLY!  1900 balls, and all of them have to solder perfectly or the chip
has to come off and be re-balled!  Arghhhh!  I'd LOVE to know who is
actually USING chips that expensive.  Must be the military in those
$500 Million airplanes.

Jon

Article: 156338
Subject: Re: license server
From: langwadt@fonz.dk
Date: Tue, 11 Mar 2014 14:23:43 -0700 (PDT)
Links: << >>  << T >>  << A >>
Den tirsdag den 11. marts 2014 09.48.45 UTC+1 skrev HT-Lab:
> On 11/03/2014 07:58, alb wrote:
> 
> > On Mon, 10 Mar 2014, langwadt@fonz.dk wrote:
> 
> > Hi Lasse,
> 
> >
> 
> >> Den mandag den 10. marts 2014 18.00.25 UTC+1 skrev HT-Lab:
> 
> > []
> 
> >>>> Maybe we should think about lending *our* licenses when we do not use
> 
> >>>
> 
> >>>> them and make some profit out of them :-).
> 
> >>>
> 
> >>>
> 
> >>>
> 
> >>> You will find yourself quickly in court.....
> 
> >>>
> 
> >>
> 
> >> yeh I seems to remember year ago someone tried to start service
> 
> >> licenses sharing. With people in different time zones that would be
> 
> >> pretty smart
> 
> >>
> 
> >> It was quickly shot down, can't remember what big eda tool it was but
> 
> >> I think there was something about not being allowed to use a license
> 
> >> more than a mile from the company that bought it
> 
> >
> 
> > Damn it I think you are right! I used to have access to Cern licenses'
> 
> > pool but the maintainer warned me about using it only within the site
> 
> > /thanks/ to a clause mentioning some physical distance between the user
> 
> > and the license...
> 
> 
> 
> He is right, the distance clause is there to prevent company A from 
> 
> sharing its license with company B next door.
> 

or "worse" company A, B and C in Asia, Europe and the US 



-Lasse





Article: 156339
Subject: Re: Ball-park price of Xilinx Virtex 7 FPGA?
From: langwadt@fonz.dk
Date: Tue, 11 Mar 2014 14:32:13 -0700 (PDT)
Links: << >>  << T >>  << A >>
Den tirsdag den 11. marts 2014 22.23.36 UTC+1 skrev Jon Elson:
> GaborSzakacs wrote:
> 
> 
> 
> 
> 
> > 
> 
> > A quick DigiKey search showed a range of $2,583.75 (XC7VX330T-1FFG1157C)
> 
> > to $39,452.40 (XC7V2000T-G2FLG1925E).  These won't end up in any of my
> 
> > designs any time soon.
> 
> > 
> 
> REALLY!  1900 balls, and all of them have to solder perfectly or the chip
> 
> has to come off and be re-balled!  Arghhhh!  I'd LOVE to know who is
> 
> actually USING chips that expensive.  Must be the military in those
> 
> $500 Million airplanes.
> 
> Jon

if it does the job of an asic that would require a million dollar NRE and 
you only need 20 it's a bargain 

-Lasse

Article: 156340
Subject: Re: Ball-park price of Xilinx Virtex 7 FPGA?
From: Tom Gardner <spamjunk@blueyonder.co.uk>
Date: Tue, 11 Mar 2014 22:10:54 +0000
Links: << >>  << T >>  << A >>
On 11/03/14 21:23, Jon Elson wrote:
> GaborSzakacs wrote:
>
>
>>
>> A quick DigiKey search showed a range of $2,583.75 (XC7VX330T-1FFG1157C)
>> to $39,452.40 (XC7V2000T-G2FLG1925E).  These won't end up in any of my
>> designs any time soon.
>>
> REALLY!  1900 balls, and all of them have to solder perfectly or the chip
> has to come off and be re-balled!  Arghhhh!  I'd LOVE to know who is
> actually USING chips that expensive.  Must be the military in those
> $500 Million airplanes.

I suspect the financial community as well. They will pay extraordinary
money to shave milliseconds off transaction times. Yes, they do encode
financial algorithms into FPGA hardware.

One well known example of their ability to spend money is that one
company spent $300m laying a transatlantic cable to reduce the
RTT of 65ms by 6ms.
http://www.telegraph.co.uk/finance/newsbysector/mediatechnologyandtelecoms/8753784/The-300m-cable-that-will-save-traders-milliseconds.html

Article: 156341
Subject: Re: Ball-park price of Xilinx Virtex 7 FPGA?
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Tue, 11 Mar 2014 22:18:47 +0000 (UTC)
Links: << >>  << T >>  << A >>
Tom Gardner <spamjunk@blueyonder.co.uk> wrote:
(snip)

> I suspect the financial community as well. They will pay extraordinary
> money to shave milliseconds off transaction times. Yes, they do encode
> financial algorithms into FPGA hardware.
 
> One well known example of their ability to spend money is that one
> company spent $300m laying a transatlantic cable to reduce the
> RTT of 65ms by 6ms.

Must not have read "Wait: the art and science of delay."

-- glen

Article: 156342
Subject: Re: Ball-park price of Xilinx Virtex 7 FPGA?
From: langwadt@fonz.dk
Date: Tue, 11 Mar 2014 16:14:31 -0700 (PDT)
Links: << >>  << T >>  << A >>
Den tirsdag den 11. marts 2014 23.18.47 UTC+1 skrev glen herrmannsfeldt:
> Tom Gardner <spamjunk@blueyonder.co.uk> wrote:
> 
> (snip)
> 
> 
> 
> > I suspect the financial community as well. They will pay extraordinary
> 
> > money to shave milliseconds off transaction times. Yes, they do encode
> 
> > financial algorithms into FPGA hardware.
> 
>  
> 
> > One well known example of their ability to spend money is that one
> 
> > company spent $300m laying a transatlantic cable to reduce the
> 
> > RTT of 65ms by 6ms.
> 
> 
> 
> Must not have read "Wait: the art and science of delay."
> 

but for some reason they say that them making billions manipulating 
prices by moving numbers around milliseconds faster than everyone 
else is an essential service to society

-Lasse

Article: 156343
Subject: Re: Ball-park price of Xilinx Virtex 7 FPGA?
From: Rob Gaddi <rgaddi@technologyhighland.invalid>
Date: Tue, 11 Mar 2014 16:19:45 -0700
Links: << >>  << T >>  << A >>
On Tue, 11 Mar 2014 16:14:31 -0700 (PDT)
langwadt@fonz.dk wrote:

> Den tirsdag den 11. marts 2014 23.18.47 UTC+1 skrev glen herrmannsfeldt:
> > Tom Gardner <spamjunk@blueyonder.co.uk> wrote:
> > 
> > (snip)
> > 
> > 
> > 
> > > I suspect the financial community as well. They will pay extraordinary
> > 
> > > money to shave milliseconds off transaction times. Yes, they do encode
> > 
> > > financial algorithms into FPGA hardware.
> > 
> >  
> > 
> > > One well known example of their ability to spend money is that one
> > 
> > > company spent $300m laying a transatlantic cable to reduce the
> > 
> > > RTT of 65ms by 6ms.
> > 
> > 
> > 
> > Must not have read "Wait: the art and science of delay."
> > 
> 
> but for some reason they say that them making billions manipulating 
> prices by moving numbers around milliseconds faster than everyone 
> else is an essential service to society
> 
> -Lasse

Financial markets are much like the colon; at some point there stops
being an upside to increasing liquidity.

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

Article: 156344
Subject: Re: Ball-park price of Xilinx Virtex 7 FPGA?
From: Rob Doyle <radioengr@gmail.com>
Date: Tue, 11 Mar 2014 16:21:09 -0700
Links: << >>  << T >>  << A >>
On 3/11/2014 2:23 PM, Jon Elson wrote:
> GaborSzakacs wrote:
>
>
>>
>> A quick DigiKey search showed a range of $2,583.75 (XC7VX330T-1FFG1157C)
>> to $39,452.40 (XC7V2000T-G2FLG1925E).  These won't end up in any of my
>> designs any time soon.
>>
> REALLY!  1900 balls, and all of them have to solder perfectly or the chip
> has to come off and be re-balled!  Arghhhh!  I'd LOVE to know who is
> actually USING chips that expensive.  Must be the military in those
> $500 Million airplanes.
>
> Jon

... can't meet SEU numbers in an airplane with /one/ of those.   You'd 
need a couple!

Rob.




Article: 156345
Subject: Re: Ball-park price of Xilinx Virtex 7 FPGA?
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Tue, 11 Mar 2014 23:48:05 +0000 (UTC)
Links: << >>  << T >>  << A >>
langwadt@fonz.dk wrote:

(snip, regarding financial timins)

>> Must not have read "Wait: the art and science of delay."
 
> but for some reason they say that them making billions manipulating 
> prices by moving numbers around milliseconds faster than everyone 
> else is an essential service to society

You should read the book for the full details, but there was a group
that moved the whole operation closer to New York, and then found
that faster isn't always better. 

The whole story of the book is that faster isn't always better,
and you should know when it might not be better.

-- glen

Article: 156346
Subject: Re: Ball-park price of Xilinx Virtex 7 FPGA?
From: Tom Gardner <spamjunk@blueyonder.co.uk>
Date: Wed, 12 Mar 2014 00:33:35 +0000
Links: << >>  << T >>  << A >>
On 11/03/14 23:14, langwadt@fonz.dk wrote:
> Den tirsdag den 11. marts 2014 23.18.47 UTC+1 skrev glen herrmannsfeldt:
>> Tom Gardner <spamjunk@blueyonder.co.uk> wrote:
>>
>> (snip)
>>
>>
>>
>>> I suspect the financial community as well. They will pay extraordinary
>>
>>> money to shave milliseconds off transaction times. Yes, they do encode
>>
>>> financial algorithms into FPGA hardware.
>>
>>
>>
>>> One well known example of their ability to spend money is that one
>>
>>> company spent $300m laying a transatlantic cable to reduce the
>>
>>> RTT of 65ms by 6ms.
>>
>>
>>
>> Must not have read "Wait: the art and science of delay."
>>
>
> but for some reason they say that them making billions manipulating
> prices by moving numbers around milliseconds faster than everyone
> else is an essential service to society

As I understand it, they say they are going to move
billions - and then withdraw a few ms later. This
allows them to gauge the way the market is going.
Or something.


Article: 156347
Subject: Re: Ball-park price of Xilinx Virtex 7 FPGA?
From: GaborSzakacs <gabor@alacron.com>
Date: Wed, 12 Mar 2014 11:41:28 -0400
Links: << >>  << T >>  << A >>
Jon Elson wrote:
> GaborSzakacs wrote:
> 
> 
>> A quick DigiKey search showed a range of $2,583.75 (XC7VX330T-1FFG1157C)
>> to $39,452.40 (XC7V2000T-G2FLG1925E).  These won't end up in any of my
>> designs any time soon.
>>
> REALLY!  1900 balls, and all of them have to solder perfectly or the chip
> has to come off and be re-balled!  Arghhhh!  I'd LOVE to know who is
> actually USING chips that expensive.  Must be the military in those
> $500 Million airplanes.
> 
> Jon

Xilinx's traditional market for high-end parts has been ASIC hardware
co-simulation / prototyping.  Maybe as a part of that $1M NRE it's not
such a big hit to buy one or two of these.

As for the number of balls, I haven't seen any indication that soldering
failure rates go up in relation to the number of balls in a BGA, at
least with the contract manufacturers that we use.  And the re-balling
expense for these would still be a lot less that buying a new part...

-- 
Gabor

Article: 156348
Subject: Re: cloud design flow
From: al.basili@gmail.com (alb)
Date: 13 Mar 2014 09:00:24 GMT
Links: << >>  << T >>  << A >>
alb <al.basili@gmail.com> wrote:
> I was wondering if there's any one out there working with a cloud design 
> flow which is tool agnostic.
[]

uhm, considering the amount of replies to this thread I have only two 
possibilities to choose from:

1. nobody is using such paradigm in this community
2. nobody using this paradigm is willing to share it with this community

In both cases I'm out of luck and guess that if I ever want to go down 
this path I'll be doing it on my own.


Article: 156349
Subject: full functional coverage
From: al.basili@gmail.com (alb)
Date: 13 Mar 2014 14:13:06 GMT
Links: << >>  << T >>  << A >>
Hi everyone,

I'm trying to understand how to improve our verification flow. 

As of now we have a great deal of unit level testbenches which are 
trying to make sure the unit is behaving correctly.

Now, if I make a fair analysis of my above statement, I'm already doomed! 
What does it mean 'behaving correctly'? In our workflow we have an FPGA 
spec which is coming from /above/ and we have a verification matrix to 
define which verification method we apply for each requirement. The 
problem is: we do not have a unit level spec so how can we make sure the 
unit is correctly behaving? 

Moreover at the system level there are a certain number of scenarios 
which do not apply at unit level and viceversa, but the bottom line is 
that the system as a whole should be fully verified.

Should I decline each system level requirement to a unit level one? That 
would be nearly as long as writing RTL code using only fabric's 
privitives.

Another issue is the coverage collection. Imagine I have my set of units 
all individually tested, all of them happily reporting some sort of 
functional coverage. First of all I do not now why the heck we collect 
coverage if we do not have a spec to compare it with and second of all 
how shall I collect coverage of a specific unit when it's integrated in 
the overall system? Does it make any sense to do it?

A purely system level approach might have too poor 
observability/controllability at unit level and would not be efficient 
to spot unit level problems, especially in the very beginning of the 
coding effort, where the debug cycle is very fast. But if I start to 
write unit level testbenches it would be unlikely that I will reuse 
those benches at system level.

As you may have noticed I'm a bit confused and any pointer would be 
greatly appreciated.

Al

-- 
A: Because it messes up the order in which people normally read text. 
Q: Why is top-posting such a bad thing? 
A: Top-posting. 
Q: What is the most annoying thing on usenet and in e-mail?



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