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Messages from 157950

Article: 157950
Subject: Re: AHDL VS. VHDL
From: John Speth <johnspeth@yahoo.com>
Date: Wed, 20 May 2015 09:30:52 -0700
Links: << >>  << T >>  << A >>
On 5/19/2015 3:24 PM, philipnchill@gmail.com wrote:
> VHDL is leads to verbose designs which are slow to write and hard to visualise.
> AHDL is elegant and specifically designed fpga type architectures.

Religious wars never have a winner.  I pick Kirk over Pickard.

JJS


Article: 157951
Subject: ESP8266 based Xilinx Virtual Cable server?
From: "Wojciech M. Zabolotny" <wzab@ise.pw.edu.pl>
Date: Wed, 20 May 2015 17:18:59 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hi,

I often need to access the debugged FPGA boards remotely. Now when Xilinx
has made its Xilinx Virtual Cable specification available:
http://www.xilinx.com/products/intellectual-property/xvc.html
https://github.com/Xilinx/XilinxVirtualCable

and when it is included in the newer versions of Vivado suite:
http://forums.xilinx.com/t5/General-Technical-Discussion/XVC-Protocol-Support-In-Vivado/td-p/387977
http://forums.xilinx.com/xlnx/attachments/xlnx/GenDis/21028/1/ProdDoc_XVC_2014%203.pptx

it seems, that it should be relatively easy to implement a cheap, Internet
enabled programmer/debugger.
The ESP8266 $3 module ( http://www.esp8266.com/wiki/doku.php?id=esp8266-module-family )
seems to be a good candidate to provide authenticated access via Wi-Fi to the debugged board.

It is an open question whether that chip has sufficient resources to
implement the XVC server, but it seems that this idea is worth of further
investigation.
I'd appreciate any comments or suggestions regarding this idea.

With best regards,
Wojtek

Article: 157952
Subject: Re: AHDL VS. VHDL
From: Jan Coombs <Jan-54 <jenfhaomndgfwutc@murmic.plus.com>>
Date: Wed, 20 May 2015 23:01:47 +0100
Links: << >>  << T >>  << A >>
On Wed, 20 May 2015 05:01:37 -0700 (PDT)
thomas.entner99@gmail.com wrote:

> I think you answered a question from the
> previous century...
> 
> Thomas

I wasn't going to say that, but perhaps Philip
should look in the opposite direction, to the
future. 

MyHDL encourages test-driven development, has
a short edit-test cycle, using just one tool,
and is supported by the power of python. 

It does not have the verbosity of VHDL, nor the
subtle problems of Verilog, but exports either.

Jan Coombs. 



Article: 157953
Subject: Re: Oqpsk Demod
From: "kaz" <37480@FPGARelated>
Date: Thu, 21 May 2015 06:59:54 -0500
Links: << >>  << T >>  << A >>
>Hi all ,
>      I implement qpsk demodulator on National instruments Fpga . Now i
>want to Demodulate  Oqpsk signal . As the difference between qpsk and
>oqpsk is  only the delay of one bit period in q channel.
> 
>Q1. Can a qpsk demodulator with some changes  demodulate oqpsk data ?
>
>Q2. If it works , what changes  i should  make ?
>           flow of qpsk demodulater what i made..
>               1. frequency shifter (input from step 4)
>               2. Matched filter
>               3. AGC
>               4.  coarse frequency offset estimator (Rife and broostyn
>algorithm).
>               5. Timing recovery (Gardener)
>               6. DDPLL
>               7. symbol demapping
>        
>      what are the stages to be modified?
>
>Q3. suggest me some papers ?  
>
>
>---------------------------------------
>Posted through http://www.FPGARelated.com

For QPSK I will recover timing first then do carrier tracking.
Though I haven't done oqpsk but I don't think Gardner TED algorithm for
either qpsk or oqpsk to be any different as it is based on sample rate of
2*symbol rate and oqpsk just means restricted symbol transtions on IQ
quadrants (tx transitions through origin avoided). 

Once you recover timing then delay I relative to Q (opposite tx) and apply
carrier tracking as for qpsk.

Kaz
---------------------------------------
Posted through http://www.FPGARelated.com

Article: 157954
Subject: Re: Oberon Operating System + Compiler + Graphic on a Spartan 3 FPGA
From: cfbsoftware@gmail.com
Date: Fri, 22 May 2015 21:43:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Thursday, March 6, 2014 at 9:19:53 AM UTC+10:30, Robert F. Jarnot wrote:
> If you manage to get this running on a more modern Xilinx Eval board, 
> please let us know -- I would love to try it out.  Everything that I 
> have every seen from Niklaus Wirth has been excellent.
> 

It has now been ported to a Pipistrello Spartan 6 board by Saanlima Electronics. See the Project Oberon forum discussion at:

http://saanlima.com/forum/viewtopic.php?f=4&t=1246

Chris Burrows
CFB Software
http://www.astrobe.com



Article: 157955
Subject: IMX6 Solo - FPGA Module
From: Mark <mark.wolf@alumni.tu-berlin.de>
Date: Sun, 24 May 2015 15:40:59 +0700 (GMT+07:00)
Links: << >>  << T >>  << A >>
Hello,

I am looking for a module with Freescales iMX6 Solo and an FPGA,
 maybe an Artix or similar.
Anyone know about such module?
For now no other requirements, I will look into details then.

Thanks...
-- 
Mark

Article: 157956
Subject: Re: ESP8266 based Xilinx Virtual Cable server?
From: Wojciech M. =?UTF-8?Q?Zabo=C5=82otny?= <wzab@ise.pw.edu.pl>
Date: Sat, 30 May 2015 22:07:18 +0000 (UTC)
Links: << >>  << T >>  << A >>
Dnia 20.05.2015 Wojciech M. Zabolotny <wzab@ise.pw.edu.pl> napisaƂ/a:
> Hi,
>
> I often need to access the debugged FPGA boards remotely. Now when Xilinx
> has made its Xilinx Virtual Cable specification available:
> http://www.xilinx.com/products/intellectual-property/xvc.html
> https://github.com/Xilinx/XilinxVirtualCable
>
> and when it is included in the newer versions of Vivado suite:
> http://forums.xilinx.com/t5/General-Technical-Discussion/XVC-Protocol-Support-In-Vivado/td-p/387977
> http://forums.xilinx.com/xlnx/attachments/xlnx/GenDis/21028/1/ProdDoc_XVC_2014%203.pptx
>
> it seems, that it should be relatively easy to implement a cheap, Internet
> enabled programmer/debugger.
> The ESP8266 $3 module ( http://www.esp8266.com/wiki/doku.php?id=esp8266-module-family )
> seems to be a good candidate to provide authenticated access via Wi-Fi to the debugged board.
>
> It is an open question whether that chip has sufficient resources to
> implement the XVC server, but it seems that this idea is worth of further
> investigation.
> I'd appreciate any comments or suggestions regarding this idea.
>
> With best regards,
> Wojtek

Hi,

I have written a quick&dirty Lua implementation for ESP8266 with nodemcu
firmware. The code is posted to alt.sources usenet group:
https://groups.google.com/forum/#!topic/alt.sources/RZbOS12JgMI

The first results seem to be promising, but unfortunately, I have found
information about serious problems with XVC plugin in ISE14 (which still
has to be used for older Xilinx FPGAs).
The problem is reported here:
http://forums.xilinx.com/t5/Design-Tools-Others/iMPACT-XVC-broken-with-multiple-devices/td-p/496232
And it is not clear if Xilinx is going to fix it :-(.

Until the mentioned bug is fixed (by Xilinx), and until the code is rewritten
in C, to obtain reasonable performance, the ESP8266 based XVC server is not
very useful...

With best regards,
Wojtek

Article: 157957
Subject: Re: Free timing diagram drawing software
From: elraymonds <elraymonds@gmail.com>
Date: Thu, 04 Jun 2015 06:12:40 -0500
Links: << >>  << T >>  << A >>
Did you mean timeline diagrams? You can use http://creately.com for that. Its a online diagramming tool with real-time collaboration enabled. try it



Article: 157958
Subject: Re: Free timing diagram drawing software
From: GaborSzakacs <gabor@alacron.com>
Date: Thu, 04 Jun 2015 11:45:29 -0400
Links: << >>  << T >>  << A >>
elraymonds wrote:
> Did you mean timeline diagrams? You can use http://creately.com for that. Its a online diagramming tool with real-time collaboration enabled. try it
> 
> 

Who?  The person who posted the question 12 years ago?

Article: 157959
Subject: Re: Free timing diagram drawing software
From: rickman <gnuarm@gmail.com>
Date: Thu, 04 Jun 2015 15:18:44 -0400
Links: << >>  << T >>  << A >>
On 6/4/2015 11:45 AM, GaborSzakacs wrote:
> elraymonds wrote:
>> Did you mean timeline diagrams? You can use http://creately.com for
>> that. Its a online diagramming tool with real-time collaboration
>> enabled. try it
>>
>>
>
> Who?  The person who posted the question 12 years ago?

There was a guy writing a timing diagram editor some time back.  I think 
it was called timing designer or similar, but I see "timing designer" is 
an expensive product name.  I downloaded the early versions and found it 
to be very lacking.  I tried to give him constructive feedback. After 
pushing it for two or three years he seemed to stop posting about it.

Is this what the original post was about?

-- 

Rick

Article: 157960
Subject: Re: Free timing diagram drawing software
From: GaborSzakacs <gabor@alacron.com>
Date: Thu, 04 Jun 2015 17:15:44 -0400
Links: << >>  << T >>  << A >>
rickman wrote:
> On 6/4/2015 11:45 AM, GaborSzakacs wrote:
>> elraymonds wrote:
>>> Did you mean timeline diagrams? You can use http://creately.com for
>>> that. Its a online diagramming tool with real-time collaboration
>>> enabled. try it
>>>
>>>
>>
>> Who?  The person who posted the question 12 years ago?
> 
> There was a guy writing a timing diagram editor some time back.  I think 
> it was called timing designer or similar, but I see "timing designer" is 
> an expensive product name.  I downloaded the early versions and found it 
> to be very lacking.  I tried to give him constructive feedback. After 
> pushing it for two or three years he seemed to stop posting about it.
> 
> Is this what the original post was about?
> 

Well the original post was looking for "any free software that draws
timing diagrams."  And the only reply at that time (12 years ago) was
to check out the lite version of http://www.timingtool.com which
still seems to exist.

I do remember Timing Designer as being not very good, and eventually
quite expensive.  At the time I was using dV/dT on a Mac, which worked
quite well for what it did.  Nowadays I usually use a simulator to
create timing diagrams more complex than any I might draw by hand.

-- 
Gabor

Article: 157961
Subject: Re: Free timing diagram drawing software
From: chrisabele <ccabele@yahoo.com>
Date: Thu, 04 Jun 2015 22:20:18 -0400
Links: << >>  << T >>  << A >>
On 6/4/2015 5:15 PM, GaborSzakacs wrote:
> rickman wrote:
>> On 6/4/2015 11:45 AM, GaborSzakacs wrote:
>>> elraymonds wrote:
>>>> Did you mean timeline diagrams? You can use http://creately.com for
>>>> that. Its a online diagramming tool with real-time collaboration
>>>> enabled. try it
>>>>
>>>>
>>>
>>> Who?  The person who posted the question 12 years ago?
>>
>> There was a guy writing a timing diagram editor some time back.  I
>> think it was called timing designer or similar, but I see "timing
>> designer" is an expensive product name.  I downloaded the early
>> versions and found it to be very lacking.  I tried to give him
>> constructive feedback. After pushing it for two or three years he
>> seemed to stop posting about it.
>>
>> Is this what the original post was about?
>>
>
> Well the original post was looking for "any free software that draws
> timing diagrams."  And the only reply at that time (12 years ago) was
> to check out the lite version of http://www.timingtool.com which
> still seems to exist.
>
> I do remember Timing Designer as being not very good, and eventually
> quite expensive.  At the time I was using dV/dT on a Mac, which worked
> quite well for what it did.  Nowadays I usually use a simulator to
> create timing diagrams more complex than any I might draw by hand.
>

You guys are aware of the free TimingAnalyzer program for Windows, 
right? If not, have a look at http://www.timing-diagrams.com.

I'm no expert, but it looks like a big improvement over hand drawn 
diagrams for just about any situation (and certainly would be easier to 
revise).


Article: 157962
Subject: Re: Free timing diagram drawing software
From: rickman <gnuarm@gmail.com>
Date: Thu, 04 Jun 2015 23:16:27 -0400
Links: << >>  << T >>  << A >>
On 6/4/2015 10:20 PM, chrisabele wrote:
> On 6/4/2015 5:15 PM, GaborSzakacs wrote:
>> rickman wrote:
>>> On 6/4/2015 11:45 AM, GaborSzakacs wrote:
>>>> elraymonds wrote:
>>>>> Did you mean timeline diagrams? You can use http://creately.com for
>>>>> that. Its a online diagramming tool with real-time collaboration
>>>>> enabled. try it
>>>>>
>>>>>
>>>>
>>>> Who?  The person who posted the question 12 years ago?
>>>
>>> There was a guy writing a timing diagram editor some time back.  I
>>> think it was called timing designer or similar, but I see "timing
>>> designer" is an expensive product name.  I downloaded the early
>>> versions and found it to be very lacking.  I tried to give him
>>> constructive feedback. After pushing it for two or three years he
>>> seemed to stop posting about it.
>>>
>>> Is this what the original post was about?
>>>
>>
>> Well the original post was looking for "any free software that draws
>> timing diagrams."  And the only reply at that time (12 years ago) was
>> to check out the lite version of http://www.timingtool.com which
>> still seems to exist.
>>
>> I do remember Timing Designer as being not very good, and eventually
>> quite expensive.  At the time I was using dV/dT on a Mac, which worked
>> quite well for what it did.  Nowadays I usually use a simulator to
>> create timing diagrams more complex than any I might draw by hand.
>>
>
> You guys are aware of the free TimingAnalyzer program for Windows,
> right? If not, have a look at http://www.timing-diagrams.com.
>
> I'm no expert, but it looks like a big improvement over hand drawn
> diagrams for just about any situation (and certainly would be easier to
> revise).

I think that is the one I saw some years ago.  I think it was a labor of 
love for the author and he got little respect for it at the time.  I'm 
glad to see that he stuck with it and turned it into something truly 
useful.

-- 

Rick

Article: 157963
Subject: Re: Free timing diagram drawing software
From: Anssi Saari <as@sci.fi>
Date: Fri, 05 Jun 2015 13:19:52 +0300
Links: << >>  << T >>  << A >>
chrisabele <ccabele@yahoo.com> writes:

> You guys are aware of the free TimingAnalyzer program for Windows,
> right? If not, have a look at http://www.timing-diagrams.com.

I think someone posted a list of timing diagrammers some time ago and I
looked into a few. One was WaveDrom Editor where you edit a JSON
description of your waveform and the waveform updates in real time. I
really like it.

It's a browser app and available http://wavedrom.com/editor.html (or you
can run it whereever since it's free) and it exports the diagram to
SVG. From experience SVG is well supported by Microsoft for importing
vector drawings into documents.

Article: 157964
Subject: Is it possible to have a parameterized verilog module name in verilog
From: cpandya@yahoo.com
Date: Sat, 6 Jun 2015 03:53:37 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,

I am trying create verilog module that can support parameterized instance n=
ame. I understand that the signal width and other such things can be parame=
terized. But can we also parameterize the module instance name?

In following code, I am curious if there is any way SomeDynamicInstanceName=
 can be parameterized also? I can try to use system verilog if that can hel=
p here=20

My purpose is to be able to reuse the verilog gmon module (generic verilog =
module) for various types of signals.  But for a reason, I need to change t=
he SomeDynamicInstanceName.  I have control of a verilog file where I insta=
ntiate gmon verilog module so I can pass the parameters.

Prompt response is greatly appreciated.

`timescale 1 ns/100 ps


module gmon=20
#(
parameter WIDTH =3D 32
)
(Clk, Rst, SignalName);


// PCIE MST_BIF
input Clk;
input Rst;
input [WIDTH-1:0] SignalName;

// input [31:0] SignalName_ret




reg [WIDTH-1:0] SignalName_d1;
//reg [31:0] SignalName_d2;




always @ (posedge Clk) begin
SignalName_d1 <=3D SignalName;
// SignalName_d2 <=3D SignalName_ret;
end


wire b =3D some combinatroial log;


test_module #(.FIFOBUF_WIDTH(WIDTH)) SomeDynamicInstanceName (
.reset(Rst), //CHECK THIS -- ACTIVE HIGH
.wclk(Clk),
.out_data_valid(b),
.out_data(SignalName[WIDTH-1:0]),
.out_eom(1'b0),
.out_flush_file(1'b0),
.out_flush_pipe(1'b0)
);


Article: 157965
Subject: Re: Is it possible to have a parameterized verilog module name in verilog or systemverilog?
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Sat, 6 Jun 2015 13:55:02 +0000 (UTC)
Links: << >>  << T >>  << A >>
cpandya@yahoo.com wrote:
 
> I am trying create verilog module that can support parameterized 
> instance name. I understand that the signal width and other such 
> things can be parameterized. But can we also parameterize the 
> module instance name?
 
> In following code, I am curious if there is any way 
> SomeDynamicInstanceName can be parameterized also? I can try 
> to use system verilog if that can help here 

(snip)

I didn't figure out from the example, so maybe you can explain again.

I mostly don't use parameters, but often enough generate a new
instance with a new name.

I might have an eight bit register named reg8, and a 16 bit
one named reg16, where others might name it reg with a parameter
that is 8 or 16. 

But it is one or the other, not both.

Well, I suppose one way to implement reg8 and reg16 is though
instantiating reg with parameter 8 or 16, but another way is to use
a program in some other language to generate source modules as
appropriate.

It is very easy, for example, with awk to generate appropriate
modules with appropriate names. 

-- glen


Article: 157966
Subject: hands on experience on SystemC
From: al.basili@gmail.com (alb)
Date: 6 Jun 2015 15:13:38 GMT
Links: << >>  << T >>  << A >>
Hi everyone,

I'm cross-posting here from the SystemC Accellera Forum since I believe 
I'm likely going to receive more feedback here than there.

I've recently started to wonder what kind of project I can start with 
to get my hands on SystemC and TLM. I know there are tons of tutorials, 
getting started like materials, open libraries, open platforms and I 
believe I can get my head around most of that stuff, but one thing I'd 
like to get advice on is how complex should be my first project to make 
my learning process more effective.

I've started proposing modelling with SystemC in my group because we 
often lack of a tool to explore the bottle neck of our architectures 
and realize about it too late down in the development phase. I've got 
granted a 30% of my time for the next 6 months to learn SystemC and TLM 
and come up with a reasonably shaped showcase.

One of our core challenges is mass storage (for space applications), 
therefore I thought about modelling a possible architecture involving 
NAND Flash storage handled through some processor and high speed data 
link.

Most of the elements of this fictitious architecture are somehow 
available on the net and I would have started plugging things together 
for a start.

Does this sound too naive, or is this application too complex to be 
achievable in such a short time?

One critical element in this task would be to make the management 
understand how much they should invest in 'training/learning' before 
getting some benefit out of it.

Any pointer/suggestion/comment is highly appreciated,

Al

-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 157967
Subject: Open/Free HLS weapon of choice ?
From: Leonardo Capossio <capossio.leonardo@gmail.com>
Date: Sun, 7 Jun 2015 15:45:45 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello all, I would like to know which open or free HLS (High Level Synthesi=
s) tools are gaining widespread use, or are more likely to survive, because=
 at the time there seems to be too many, and the advantages of each of them=
 are not quite clear. The HLS we are talking about should generate synthesi=
zable Verilog or VHDL for multiple architectures (at least Xilinx/Altera).

Learning a new language is cumbersome, hence I would like to fill my head w=
ith only a select few that have promising future.

I have read this comparison (http://upcommons.upc.edu/e-prints/bitstream/21=
17/25882/1/Cristal.pdf), which made my think that Chisel might be the way t=
o go.

Article: 157968
Subject: PCIe card with FPGA and DAC
From: John Larkin <jlarkin@highlandtechnology.com>
Date: Mon, 08 Jun 2015 15:32:30 -0700
Links: << >>  << T >>  << A >>


I got a call from a really nice guy who has a tiny company in the
Bahamas. Our gear is too expensive for his application, but it could
be done with a PCIe PC-plugin board that has an FPGA and a fast DAC.
It would need analog bandwidth in the 30 MHz range, maybe 100M
samples/sec or so. He would need help to program the FPGA, since the
signal set that he needs to generate is kind of weird, but not
actually super complex.

So, does anybody know of an existing board that would work? I'd expect
that lots of people make stuff like this and are used to helping
customers customize them. We're talking tens of systems here, not
enough for a custom board design.

I'll do a little googling myself, but I thought I'd ask.


-- 

John Larkin         Highland Technology, Inc
picosecond timing   precision measurement 

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com


Article: 157969
Subject: Re: PCIe card with FPGA and DAC
From: Martin Riddle <martin_ridd@verizon.net>
Date: Mon, 08 Jun 2015 19:21:16 -0400
Links: << >>  << T >>  << A >>
On Mon, 08 Jun 2015 15:32:30 -0700, John Larkin
<jlarkin@highlandtechnology.com> wrote:

>
>
>I got a call from a really nice guy who has a tiny company in the
>Bahamas. Our gear is too expensive for his application, but it could
>be done with a PCIe PC-plugin board that has an FPGA and a fast DAC.
>It would need analog bandwidth in the 30 MHz range, maybe 100M
>samples/sec or so. He would need help to program the FPGA, since the
>signal set that he needs to generate is kind of weird, but not
>actually super complex.
>
>So, does anybody know of an existing board that would work? I'd expect
>that lots of people make stuff like this and are used to helping
>customers customize them. We're talking tens of systems here, not
>enough for a custom board design.
>
>I'll do a little googling myself, but I thought I'd ask.


Theres a MAX 10 dev board, but its USB 2.0
NI comes to mind, they had a PCIe FPGA board to go with their LabView
FPGA complier.

MCCdaq comes up empty.

Cheers

Article: 157970
Subject: Re: PCIe card with FPGA and DAC
From: Martin Riddle <martin_ridd@verizon.net>
Date: Mon, 08 Jun 2015 19:36:48 -0400
Links: << >>  << T >>  << A >>
On Mon, 08 Jun 2015 19:21:16 -0400, Martin Riddle
<martin_ridd@verizon.net> wrote:

>On Mon, 08 Jun 2015 15:32:30 -0700, John Larkin
><jlarkin@highlandtechnology.com> wrote:
>
>>
>>
>>I got a call from a really nice guy who has a tiny company in the
>>Bahamas. Our gear is too expensive for his application, but it could
>>be done with a PCIe PC-plugin board that has an FPGA and a fast DAC.
>>It would need analog bandwidth in the 30 MHz range, maybe 100M
>>samples/sec or so. He would need help to program the FPGA, since the
>>signal set that he needs to generate is kind of weird, but not
>>actually super complex.
>>
>>So, does anybody know of an existing board that would work? I'd expect
>>that lots of people make stuff like this and are used to helping
>>customers customize them. We're talking tens of systems here, not
>>enough for a custom board design.
>>
>>I'll do a little googling myself, but I thought I'd ask.
>
>
>Theres a MAX 10 dev board, but its USB 2.0
>NI comes to mind, they had a PCIe FPGA board to go with their LabView
>FPGA complier.
>
>MCCdaq comes up empty.
>
>Cheers

bittware ???

Cheers

Article: 157971
Subject: Re: hands on experience on SystemC
From: al.basili@gmail.com (alb)
Date: 9 Jun 2015 06:25:02 GMT
Links: << >>  << T >>  << A >>
Hi again,

alb <al.basili@gmail.com> wrote:
[]
> I'm cross-posting here from the SystemC Accellera Forum since I believe 
> I'm likely going to receive more feedback here than there.
[]

well, I was overly optimistic I guess...I've started to believe that 
the SystemC community is less prone to discuss such topics online.

Mind you, this is not a complain towards the community, rather an 
hypothesis on the type and shape of the community itself. Traffic on 
the Accellera seems pretty low compared to other languages 
forums/groups but maybe it's just a not so well educated guess.

Some time ago I've explored the possibility to launch an RFD for 
opening a comp.lang.systemc newsgroup, but considering the amount of 
traffic on the subject I'm not sure it's going to be very much useful. 
OTOH I'd be happy to reassess my position if somebody prooves me wrong 
and I'd be willing to embark the journey to submit the proposal to the 
Big8 board.

Al

Article: 157972
Subject: Re: PCIe card with FPGA and DAC
From: Jasen Betts <jasen@xnet.co.nz>
Date: 9 Jun 2015 08:53:10 GMT
Links: << >>  << T >>  << A >>
On 2015-06-08, John Larkin <jlarkin@highlandtechnology.com> wrote:
>
>
> I got a call from a really nice guy who has a tiny company in the
> Bahamas. Our gear is too expensive for his application, but it could
> be done with a PCIe PC-plugin board that has an FPGA and a fast DAC.
> It would need analog bandwidth in the 30 MHz range, maybe 100M
> samples/sec or so. He would need help to program the FPGA, since the
> signal set that he needs to generate is kind of weird, but not
> actually super complex.
>
> So, does anybody know of an existing board that would work? I'd expect
> that lots of people make stuff like this and are used to helping
> customers customize them. We're talking tens of systems here, not
> enough for a custom board design.
>
> I'll do a little googling myself, but I thought I'd ask.

Sounds like a video card. no FPGA, but you get oodles of RAM and a 
massively parallel GPU.  dunno if the DAC has enough bits or not.

Jan did DVB-S in CPU software with VGA output.

-- 
umop apisdn


Article: 157973
Subject: Re: PCIe card with FPGA and DAC
From: Guy Eschemann <Guy.Eschemann@gmail.com>
Date: Tue, 9 Jun 2015 06:20:04 -0700 (PDT)
Links: << >>  << T >>  << A >>
John,

you might want to look at the 4DSP products (http://www.4dsp.com). They have both FPGA PCIe boards and DAC FMC daughter boards.

Regards,

Guy Eschemann
FPGA Consultant
http://noasic.com


On Tuesday, June 9, 2015 at 12:32:35 AM UTC+2, John Larkin wrote:
> I got a call from a really nice guy who has a tiny company in the
> Bahamas. Our gear is too expensive for his application, but it could
> be done with a PCIe PC-plugin board that has an FPGA and a fast DAC.
> It would need analog bandwidth in the 30 MHz range, maybe 100M
> samples/sec or so. He would need help to program the FPGA, since the
> signal set that he needs to generate is kind of weird, but not
> actually super complex.
> 
> So, does anybody know of an existing board that would work? I'd expect
> that lots of people make stuff like this and are used to helping
> customers customize them. We're talking tens of systems here, not
> enough for a custom board design.
> 
> I'll do a little googling myself, but I thought I'd ask.
> 
> 
> -- 
> 
> John Larkin         Highland Technology, Inc
> picosecond timing   precision measurement 
> 
> jlarkin att highlandtechnology dott com
> http://www.highlandtechnology.com

Article: 157974
Subject: Re: Open/Free HLS weapon of choice ?
From: Yaman Umuroglu <maltanar@gmail.com>
Date: Tue, 9 Jun 2015 08:11:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Monday, June 8, 2015 at 12:45:50 AM UTC+2, Leonardo Capossio wrote:
> Hello all, I would like to know which open or free HLS (High Level Synthe=
sis) tools are gaining widespread use, or are more likely to survive, becau=
se at the time there seems to be too many, and the advantages of each of th=
em are not quite clear. The HLS we are talking about should generate synthe=
sizable Verilog or VHDL for multiple architectures (at least Xilinx/Altera)=
.
>=20
> Learning a new language is cumbersome, hence I would like to fill my head=
 with only a select few that have promising future.
>=20
> I have read this comparison (http://upcommons.upc.edu/e-prints/bitstream/=
2117/25882/1/Cristal.pdf), which made my think that Chisel might be the way=
 to go.

Hi Leonardo,

I really like Chisel and have used it for two FPGA compute projects so far =
by either directly using the generated Verilog, or wrapping it as IP cores =
for importing into Vivado. However, I wouldn't really call it "HLS" -- whil=
e it gives higher productivity compared to Verilog or VHDL, Chisel code is =
still very close to RTL and requires RTL-like thinking.
While I've only looked at it briefly myself, LegUp seems to be a worthy ope=
n/free HLS alternative that is actively maintained (http://legup.eecg.utoro=
nto.ca/). I don't think they support Xilinx for the time being, but the abs=
tractions made by the framework should make it straightforward to port to X=
ilinx FPGAs (i.e defining the primitives and their relative cost).

Yaman



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