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Messages from 159275

Article: 159275
Subject: Re: requirement for PC for VHDL design
From: already5chosen@yahoo.com
Date: Tue, 20 Sep 2016 02:56:08 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Tuesday, September 20, 2016 at 12:36:42 PM UTC+3, already...@yahoo.com w=
rote:
> On Sunday, September 18, 2016 at 8:24:14 PM UTC+3, David Brown wrote:
> >=20
> > Modern FPGA tools should be quite good at using multiple cores.  And=20
> > they are /very/ good at using memory - get as much as you can afford.=
=20
>=20
> Both of the statements above are wrong.
>=20
> Modern FPGA tools can occupy multiple cores, but it does not translate in=
to significant improvements in synthesis or P&R speed.
> Two cores are at best 15% faster than one core. Four cores over two - har=
dly noticeable at all.
> As to memory, each FPGA device requires certain amount of memory for P&R.=
 When you have that much then getting more does not help. If you have less =
- you better don't start, it would be too slow. The said "certain amount" i=
s typically specified in the documentation of your tools.
>=20
> For example, Altera Quartus 15.1 (devices that are likely to matter for h=
obbyist):
> Cyclone IV E - 512 MB to 1.5 GB
> Cyclone IV GX - 512 MB to 2 GB
> Cyclone V - 6-8 GB=20
> MAX II/MAX V - 512 MB
> MAX 10 - 512 MB - 2 GB
>=20
> So, >2 cores and >8 GB of RAM matter *only* if one wants to run several c=
ompilations simultaneously.
>=20
> In money-limited situation the choice between=20
> a) 8 GB of RAM + HDD
> b) 16 GB of RAM + 256 GB SSD
> is very obvious - take b)
> That assumes that you are also buying external HDD for backups and for ra=
rely used staff, but you'll want it anyway, don't you?

Mistake above. I meant to say:
a) 16 GB of RAM + HDD
b) 8 GB of RAM + 256 GB SSD

Article: 159276
Subject: Re: requirement for PC for VHDL design
From: already5chosen@yahoo.com
Date: Tue, 20 Sep 2016 03:12:36 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sunday, September 18, 2016 at 5:17:36 PM UTC+3, kristoff wrote:
> Hi all,
> 
> 
> I am thinking to buy a new PC (laptop, ubuntu).
>

Ubuntu is o.k. for Xilinx Vivado
For Altera Quartus, it is not supported. It does not mean that it wouldn't work at the end, but initially it would be a pain to setup, relatively to Win7 or to Red Hat related Linux distros.

> 
> One of the things I want to do more in the future is FPGA design. I 
> currently do very simple projects and I notice that with the 4 GB of RAM 
> I have in the laptop I currently use, that is already an issue.
> 
> And I want to try out soft-cores in the future.

Soft cores don't add to RAM requirements on HW development side.

> 
> 
> What would one see as requirements for a PC for FPGA design for a hobbyist?
> I guess memory is the main issue. Or not?
> 
> 
> 
> Kristoff


Article: 159277
Subject: Re: Minimal-operation shift-and-add (or subtract)
From: Walter Banks <walter@bytecraft.com>
Date: Tue, 20 Sep 2016 16:28:36 -0400
Links: << >>  << T >>  << A >>
On 2016-09-01 4:24 PM, Tim Wescott wrote:
> On Thu, 01 Sep 2016 13:19:09 -0700, lasselangwadtchristensen wrote:
>
>> Den torsdag den 1. september 2016 kl. 21.53.33 UTC+2 skrev Tim
>> Wescott:
>>> There's a method that I know, but can't remember the name.  And
>>> now I want to tell someone to Google for it.
>>>
>>> It basically starts with the notion of multiplying by
>>> shift-and-add, but uses the fact that if you shift and then
>>> either add or subtract, you can minimize "addition" operations.
>>>
>>> I.e., 255 = 256 - 1, 244 = 256 - 16 + 4, etc.
>>>
>>>
>> Booth?
>>
>> -Lasse
>
> That's it.  Thanks.
>


Bit late but it sounds like Horner decomposition. Yep that guy..

I couldn't find a quick reference on line.  The notes in our compilers
for inline constant multiplies is implemented with Horners polynomial
decomposition. This requires no temporary space and only uses shifts and
adds.

I remember writing the code on a weekend on a trip where I was getting
caught up on a bunch of potentially interesting papers and it was
pouring rain. I decided this would be just as much fun anyway.

Old enough the paper is in a banker box close enough to the center that
it hasn't become nesting material for the field mice.

w..

Article: 159278
Subject: Re: Minimal-operation shift-and-add (or subtract)
From: rickman <gnuarm@gmail.com>
Date: Tue, 20 Sep 2016 17:24:27 -0400
Links: << >>  << T >>  << A >>
On 9/3/2016 7:44 PM, lasselangwadtchristensen@gmail.com wrote:
> Den søndag den 4. september 2016 kl. 00.10.56 UTC+2 skrev rickman:
>> On 9/3/2016 8:46 AM, lasselangwadtchristensen@gmail.com wrote:
>>> Den lørdag den 3. september 2016 kl. 03.45.13 UTC+2 skrev rickman:
>>>> On 9/2/2016 8:08 PM, lasselangwadtchristensen@gmail.com wrote:
>>>>> Den lørdag den 3. september 2016 kl. 01.37.56 UTC+2 skrev rickman:
>>>>>> On 9/2/2016 4:01 PM, lasselangwadtchristensen@gmail.com wrote:
>>>>>>> Den fredag den 2. september 2016 kl. 08.39.20 UTC+2 skrev rickman:
>>>>>>>> On 9/1/2016 7:22 PM, lasselangwadtchristensen@gmail.com wrote:
>>>>>>>>> Den fredag den 2. september 2016 kl. 00.40.28 UTC+2 skrev
>>>>>>>>> rickman:
>>>>>>>>>> On 9/1/2016 4:24 PM, Tim Wescott wrote:
>>>>>>>>>>> On Thu, 01 Sep 2016 13:19:09 -0700, lasselangwadtchristensen
>>>>>>>>>>> wrote:
>>>>>>>>>>>
>>>>>>>>>>>> Den torsdag den 1. september 2016 kl. 21.53.33 UTC+2 skrev
>>>>>>>>>>>> Tim Wescott:
>>>>>>>>>>>>> There's a method that I know, but can't remember the
>>>>>>>>>>>>> name. And now I want to tell someone to Google for it.
>>>>>>>>>>>>>
>>>>>>>>>>>>> It basically starts with the notion of multiplying by
>>>>>>>>>>>>> shift-and-add, but uses the fact that if you shift and
>>>>>>>>>>>>> then either add or subtract, you can minimize "addition"
>>>>>>>>>>>>> operations.
>>>>>>>>>>>>>
>>>>>>>>>>>>> I.e., 255 = 256 - 1, 244 = 256 - 16 + 4, etc.
>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>> Booth?
>>>>>>>>>>>>
>>>>>>>>>>>> -Lasse
>>>>>>>>>>>
>>>>>>>>>>> That's it.  Thanks.
>>>>>>>>>>
>>>>>>>>>> That is very familiar from college, but I don't recall the
>>>>>>>>>> utility. It would be useful for multiplying by constants, but
>>>>>>>>>> otherwise how would this be used to advantage?  It would save
>>>>>>>>>> add/subtract operations, but I can't think of another situation
>>>>>>>>>> where this would be useful.
>>>>>>>>>>
>>>>>>>>>> If the algorithm is doing an add and shift, the add does not
>>>>>>>>>> increase the time or the hardware.  If building the full
>>>>>>>>>> multiplier, an adder is included for each stage, it is either
>>>>>>>>>> used or not used.  When done in software, the same applies.  It
>>>>>>>>>> is easier to do the add than to skip over it.
>>>>>>>>>
>>>>>>>>> you only need half the stages so it is half the size* and the
>>>>>>>>> critical path through your adders are only half as long
>>>>>>>>
>>>>>>>> I think you need to look at the algorithm again.  The degenerate
>>>>>>>> case is a multiplier with alternating ones and zeros.  An add or
>>>>>>>> subtract is needed at each 1->0 or 0->1 transition.  Since every
>>>>>>>> bit is a transition you still need an adder/subtractor for every
>>>>>>>> bit.
>>>>>>>>
>>>>>>>> Of course you could add logic to detect these cases and do fewer
>>>>>>>> adder ops, but then that is not Booth's algorithm anymore and is
>>>>>>>> much more complex.  Booth's algorithm looks at pairs of bits in the
>>>>>>>> multiplier, this would require looking at more bits.
>>>>>>>>
>>>>>>>
>>>>>>> you are right, I was thinking of "modified Booth" it looks at 3 bits
>>>>>>> at a time,
>>>>>>>
>>>>>>> http://www.ellab.physics.upatras.gr/~bakalis/Eudoxus/mbm8.gif
>>>>>>>
>>>>>>>
>>>>>>>> If you are thinking in terms of constant multiplication then again,
>>>>>>>> this is a modified method that combines Booth's with straight
>>>>>>>> adds.
>>>>>>>>
>>>>>>>>
>>>>>>>>> * you need a few multiplexors to choose between x1 and x2,
>>>>>>>>> subtract is invert and carry in
>>>>>>>>
>>>>>>>> Multiplexers are not low cost in any sense in many technologies,
>>>>>>>> but it doesn't matter.  Booth's algorithm doesn't use
>>>>>>>> multiplexers.
>>>>>>>
>>>>>>> may not be low cost, but compared to a full adder?
>>>>>>
>>>>>> In an FPGA the unit of size is the Logic Cell (LC), a LUT and a FF.
>>>>>> Because there is extra carry logic in the LC one bit of an adder is the
>>>>>> same logic as one bit of a multiplexer.  The only disadvantage of an
>>>>>> adder is the carry propagation time, but they don't cascade, properly
>>>>>> designed you end up with one ripple cascade through one adder and then
>>>>>> the other logic delays as the adders all cascade in parallel.
>>>>>
>>>>> sure most fpgas have fast carry chains or build in multipliers so hand
>>>>> coding "fancy" multiplier structures might not come out ahead
>>>>>
>>>>>>
>>>>>>
>>>>>>> and since the inputs come from the multiplicand and the multiplier
>>>>>>> not from other intermediate results it shouldn't be in the critical
>>>>>>> path
>>>>>>
>>>>>> ???
>>>>>>
>>>>>> I don't see how you use multiplexers instead of adders.  If the
>>>>>> multiplier changes from one calculation to the next you need adders in
>>>>>> every position.  If the multiplier is fixed the combinations of sums is
>>>>>> fixed and no multiplexers are needed.
>>>>>
>>>>> with a regular multiplier you have to go through N layers of adders
>>>>> with a modified Booth you only have to go through N/2 adders
>>>>
>>>> and N/2 multiplexers which have the same delay... PLUS the selectable
>>>> inverter which may or may not be combined with the adder.  What's the
>>>> point?
>>>
>>> the multiplexers get their input from the multiplicant not the output
>>> of the previous adder
>>
>> Look at your diagram again.  The multiplexer is muxing the output of the
>> previous stage or the output of the stage prior to that if the previous
>> stage is skipped.  The multiplicand is the other input to the adder and
>> the control signal is derived from the multiplier which means there is
>> an added level of delay into the first stage with then has to ripple
>> through the entire structure.  The multiplexers *must* be in the path of
>> the additions.
>
> the multiplexers can be moved to multiplicand, adding zero is the same as skipping
>
> http://www.ellab.physics.upatras.gr/~bakalis/Eudoxus/mbm8.gif

This diagram is not totally clear, but it does not appear to be 
implementable in an FPGA using the carry chain.  Without carry chain the 
adds get much slower and/or use twice as much space.  The decoders and 
multiplexers do result in a larger design in most FPGAs.

It might be possible to use the carry chain across the adds.  This would 
be difficult to code in a way that is implemented with carry chains. 
Without the carry chains, the full adder bits require running through an 
extra LUT both for the input and the output in the devices I have looked 
at.

If this multiplier were to be pipelined, it would be exceedingly large 
using 2N FFs for every stage.  In that case the multiplier would also 
have to be pipelined resulting in 3N FFs per stage.


>>>> A simple adder has N stages of delay in an FPGA, same as the
>>>> much more complicated modified Booth's adder.  In an ASIC there may be
>>>> some advantage.  In software, I expect the much more complicated control
>>>> will make the modified Booth's algorithm the slowest of the three.
>>>
>>> agreed
>>>
>>>> People so often forget that multiplexers are not trivial logic.
>>>
>>> I think the main purpose of modified booth is speed not size
>>
>> I'm not sure how much faster a multiplexer is compared to the adder.
>> Even if you bypass a bunch of adders, you pass through an equivalent
>> number of muxes.
>
> I'm still talking modified Booth, it halfs the number of layers

Regardless, this is a fairly pointless exercise for FPGAs since most of 
them offer hard multipliers which run much faster than multipliers in 
the fabric typically.  I think this would only be useful in an ASIC.

-- 

Rick C

Article: 159279
Subject: Re: requirement for PC for VHDL design
From: colin <colin_toogood@yahoo.com>
Date: Wed, 21 Sep 2016 00:27:20 -0700 (PDT)
Links: << >>  << T >>  << A >>
Be very careful with your choice of laptop regarding cooling. Even the very=
 fast ones are designed to only be very fast for short periods, although mo=
nster gaming laptops are an obvious exception. Most of us here have laptops=
 but we synthesize on the "farm" due to overheating. My fan was running alm=
ost constantly until I stripped it down and replaced the dried up and usele=
ss thermal paste on the processor.

Colin.

Article: 159280
Subject: Re: requirement for PC for VHDL design
From: o pere o <me@somewhere.net>
Date: Wed, 21 Sep 2016 12:39:41 +0200
Links: << >>  << T >>  << A >>
On 20/09/16 12:12, already5chosen@yahoo.com wrote:
> On Sunday, September 18, 2016 at 5:17:36 PM UTC+3, kristoff wrote:
>> Hi all,
>>
>>
>> I am thinking to buy a new PC (laptop, ubuntu).
>>
>
> Ubuntu is o.k. for Xilinx Vivado
> For Altera Quartus, it is not supported. It does not mean that it wouldn't work at the end, but initially it would be a pain to setup, relatively to Win7 or to Red Hat related Linux distros.

Altera Quartus *is* supported on Linux, according to their web site (and 
to my past experience) https://dl.altera.com/

>
>>
>> One of the things I want to do more in the future is FPGA design. I
>> currently do very simple projects and I notice that with the 4 GB of RAM
>> I have in the laptop I currently use, that is already an issue.
>>
>> And I want to try out soft-cores in the future.
>
> Soft cores don't add to RAM requirements on HW development side.
>
>>
>>
>> What would one see as requirements for a PC for FPGA design for a hobbyist?
>> I guess memory is the main issue. Or not?
>>
>>
>>
>> Kristoff
>


Article: 159281
Subject: Re: requirement for PC for VHDL design
From: already5chosen@yahoo.com
Date: Wed, 21 Sep 2016 06:57:45 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Wednesday, September 21, 2016 at 1:39:12 PM UTC+3, o pere o wrote:
> On 20/09/16 12:12, already5chosen@yahoo.com wrote:
> > On Sunday, September 18, 2016 at 5:17:36 PM UTC+3, kristoff wrote:
> >> Hi all,
> >>
> >>
> >> I am thinking to buy a new PC (laptop, ubuntu).
> >>
> >
> > Ubuntu is o.k. for Xilinx Vivado
> > For Altera Quartus, it is not supported. It does not mean that it wouldn't work at the end, but initially it would be a pain to setup, relatively to Win7 or to Red Hat related Linux distros.
> 
> Altera Quartus *is* supported on Linux, according to their web site (and 
> to my past experience) https://dl.altera.com/
> 

What did I wrote that it isn't?
It is supported on Red Hat Linux. Not on Ubuntu.

Article: 159282
Subject: Re: requirement for PC for VHDL design
From: Theo Markettos <theom+news@chiark.greenend.org.uk>
Date: 22 Sep 2016 16:23:18 +0100 (BST)
Links: << >>  << T >>  << A >>
kristoff <kristoff@skypro.be> wrote:
> What would one see as requirements for a PC for FPGA design for a hobbyist?
> I guess memory is the main issue. Or not?

The most critical thing involved in choosing hardware for synthesis (at
least with Altera tools) is not what you expect.  It's Iris Pro graphics.
And it's even better when you have Iris Pro graphics /and/ a discrete GPU.
Even though the tools don't use the GPU for compute whatsoever.

Think I'm crazy?  Here's the explanation.

FPGA synthesis is very memory heavy.  The in-memory dataset can be large (eg
for Cyclone V Altera recommend 6GB of memory - that probably means you want
>8GB DRAM if you want to use larger FPGAs or run anything else).  This
utterly hammers the CPU cache which is tiny in comparison (2MB/core on many
Intel parts).  That means memory latency is a big bottleneck.

Some (not all) Iris Pro parts have EDRAM, which is 32/64/128MB of DRAM in
the CPU package.  It's intended for the GPU to have closer memory for than
having to share DDR3/DDR4 with everything else.  However on some Haswell,
Broadwell and Skylake parts, the EDRAM can be used as L4 cache for the CPU.

The latency of EDRAM is about half that of DDR3, and this shows in benchmark
results - eg against a dual-socket E5-2667v2 (8 cores per socket) the
Broadwell i7-5775c (quad-core 128MB EDRAM, 6MB L2) is about twice as quick. 
Against an i7-6700k the Broadwell is about 10-20% quicker (I don't have the
exact numbers here).  I tweaked other parts of the Broadwell machine with
some excessively 'enthusiast' parts (DDR3-2400, NVMe, crazy cooler) which
made insignificant differences but it was the CPU choice that stood out.

Now the bit I haven't benchmarked is as follows.  The L4 is relatively
small, and so having the GPU take out a chunk isn't ideal.  So my theory
goes that a machine with Iris Pro graphics and any old discrete GPU will
prevent the video system using the EDRAM and so keep it all for use as L4. 
Because I don't know exactly what the GPU drivers will use EDRAM for I
haven't found a good way to benchmark EDRAM contention.  The two test
machines I have are using ancient Radeon X1300 and Geforce 7700 GPUs just to
have a basic display off the EDRAM.

The downside to this is that EDRAM is pretty rare across Intel's product
range, particularly in desktops and servers.  However it's more common in
laptops - which means that, if you can get the cooling package right, a
laptop isn't a bad option for synthesis.  The other option, unless you're
willing to go to a desktop i7-5775c or i7-5675c, or a Xeon E3-1200 v4, is
the Skylake Skull Canyon NUC.  Despite being thermally constrained this
clocks in about the same performance as an i7-6700k desktop with a massive
cooling solution (the NUC is also sharing EDRAM with the GPU).

Theo

(who would be very interested if there's any standardised benchmarks out
there for synthesis tools)

Article: 159283
Subject: Re: requirement for PC for VHDL design
From: Theo Markettos <theom+news@chiark.greenend.org.uk>
Date: 22 Sep 2016 16:32:45 +0100 (BST)
Links: << >>  << T >>  << A >>
already5chosen@yahoo.com wrote:
> What did I wrote that it isn't?
> It is supported on Red Hat Linux. Not on Ubuntu.

Quartus is absolutely fine on Ubuntu (up to 16.04).  You just have to
install a handful of libraries and a udev rule and that's it.

(There are a couple more warnings you can make go away by deleting the
supplied libraries it uses and letting it fall back to the system ones, but
I usually don't bother and just ignore them)

We use it 100% on Ubuntu and never had an Ubuntu-related problem we couldn't
easily solve.  (The main one is working out what Ubuntu have renamed the
packages to this time, which happens every two years).

Theo

Article: 159284
Subject: Re: requirement for PC for VHDL design
From: Theo Markettos <theom+news@chiark.greenend.org.uk>
Date: 22 Sep 2016 16:51:27 +0100 (BST)
Links: << >>  << T >>  << A >>
David Brown <david.brown@hesbynett.no> wrote:
> If you have a very large working set (i.e., a lot of big files that you 
> are reading and writing at once), so that the data can't be cached in 
> your ram, then an SSD will often be faster.  But even then, a couple of 
> decent HD's in raid (Linux supports top-class software raid) will often 
> give you similar speed.
> 
> Of course, an SSD is never a /bad/ thing - but if you have a choice of 
> an SSD or more ram, then more ram is usually the best use of your money.

For Quartus, there are two phases with different performance
characteristics:

Synthesis is mostly RAM-bound, except when it needs to interact with the
on-disk database (which can be about 1GB in size).
 
IP Generation (mostly the Qsys tool) - when you ask it to generate
Verilog for a system-on-chip you built, and it produces a large number of
verilog files instantiating all the IP you need for your system.  This is
disk bound because it's all about latency.


SATA SSD will make IP generation about a factor of 2 faster, NVMe perhaps
1.5x faster than SATA SSD.  SATA SSD is perhaps 10% quicker for synthesis
(figures off the top of my head, I don't have hard numbers with me).  NVMe
didn't make much difference to synthesis.

What really kills is network filesystems.  Do not put your files on NFS, or
worse any kind of off-premises network filesystem, because you will be in for
much pain.  Do not put your files in Dropbox, because you will then thrash
trying to upload them (as well as eat bandwidth for breakfast).


At the moment flash is cheap enough that I won't really consider HDD any
more except for semi-archival storage.  Though beware the cheap end of the
consumer flash market where there's plenty of dross (5400rpm laptop HDDs are
pretty dire too).  My current trick is buying 'prosumer' kit (eg Samsung 850
EVO) and formatting it 7-10% short.  That gives the controller some margin
so that performance consistency doesn't nosedive as it gets full, but is
cheaper than buying the 'PRO' models (which are ~50% more expensive last
time I looked at 1TB).  I have no numbers to back that up as yet, but my
strategy is taken from staring at too many benchmark graphs.

Theo

Article: 159285
Subject: Re: requirement for PC for VHDL design
From: Theo Markettos <theom+news@chiark.greenend.org.uk>
Date: 22 Sep 2016 16:57:32 +0100 (BST)
Links: << >>  << T >>  << A >>
Cecil Bayona <cbayona@cbayona.com> wrote:
> That is the beauty of having options, I used to use VirtualBox myself 
> but after a bout where VirtualBox removed the licenses to Windows 10 out 
> of the blue I switched to VMware.
> 
> I installed Windows 7 and used up a license, then upgraded it to Windows 
> 10 and all was fine for a while, then on one of the upgrades to 
> VirtualBox it removed the licenses to Windows 10 and several Partitions 
> that had Windows Server that I used for school also lost their licenses, 
> that was it, and away it went.

Our Quartus measurement suggests that VirtualBox performance (Linux host on
Linux guest as it happens, but that shouldn't matter so much) is within
about 10-15% of running on the host.  The same feels about true with VMWare
Fusion on comparable hardware (obviously we can't run Quartus on macOS, and
I haven't tried native Linux).  I haven't tested Quartus directly on Windows
of any kind.

Theo

Article: 159286
Subject: Re: requirement for PC for VHDL design
From: already5chosen@yahoo.com
Date: Thu, 22 Sep 2016 09:23:42 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Thursday, September 22, 2016 at 6:23:22 PM UTC+3, Theo Markettos wrote:
> kristoff <kristoff@skypro.be> wrote:
> > What would one see as requirements for a PC for FPGA design for a hobbyist?
> > I guess memory is the main issue. Or not?
> 
> The most critical thing involved in choosing hardware for synthesis (at
> least with Altera tools) is not what you expect.  It's Iris Pro graphics.
> And it's even better when you have Iris Pro graphics /and/ a discrete GPU.
> Even though the tools don't use the GPU for compute whatsoever.
> 
> Think I'm crazy?  Here's the explanation.
> 
> FPGA synthesis is very memory heavy.  The in-memory dataset can be large (eg
> for Cyclone V Altera recommend 6GB of memory - that probably means you want
> >8GB DRAM if you want to use larger FPGAs or run anything else).  This
> utterly hammers the CPU cache which is tiny in comparison (2MB/core on many
> Intel parts).  That means memory latency is a big bottleneck.
> 
> Some (not all) Iris Pro parts have EDRAM, which is 32/64/128MB of DRAM in
> the CPU package.  It's intended for the GPU to have closer memory for than
> having to share DDR3/DDR4 with everything else.  However on some Haswell,
> Broadwell and Skylake parts, the EDRAM can be used as L4 cache for the CPU.
> 
> The latency of EDRAM is about half that of DDR3, and this shows in benchmark
> results - eg against a dual-socket E5-2667v2 (8 cores per socket) the
> Broadwell i7-5775c (quad-core 128MB EDRAM, 6MB L2) is about twice as quick. 
> Against an i7-6700k the Broadwell is about 10-20% quicker (I don't have the
> exact numbers here).  I tweaked other parts of the Broadwell machine with
> some excessively 'enthusiast' parts (DDR3-2400, NVMe, crazy cooler) which
> made insignificant differences but it was the CPU choice that stood out.
> 
> Now the bit I haven't benchmarked is as follows.  The L4 is relatively
> small, and so having the GPU take out a chunk isn't ideal.  So my theory
> goes that a machine with Iris Pro graphics and any old discrete GPU will
> prevent the video system using the EDRAM and so keep it all for use as L4. 
> Because I don't know exactly what the GPU drivers will use EDRAM for I
> haven't found a good way to benchmark EDRAM contention.  The two test
> machines I have are using ancient Radeon X1300 and Geforce 7700 GPUs just to
> have a basic display off the EDRAM.
> 
> The downside to this is that EDRAM is pretty rare across Intel's product
> range, particularly in desktops and servers.  

I think, eDRAM presents in all Xeon-E3 v4 (Broadwell) processors.
For Xeon E3 v5 (Skylake) Intel ark suggests E3-1585 v5, E3-1585L v5 and E3-1565L v5 as well as a few mobile Xeons, like  E3-1545M v5 

> However it's more common in
> laptops - which means that, if you can get the cooling package right, a
> laptop isn't a bad option for synthesis.  The other option, unless you're
> willing to go to a desktop i7-5775c or i7-5675c, or a Xeon E3-1200 v4, is
> the Skylake Skull Canyon NUC.  Despite being thermally constrained this
> clocks in about the same performance as an i7-6700k desktop with a massive
> cooling solution (the NUC is also sharing EDRAM with the GPU).
> 
> Theo
> 
> (who would be very interested if there's any standardised benchmarks out
> there for synthesis tools)

Interesting.
If memory latency is so crazily important then probably even a number of installed DIMMs matters. 4 DIMMs will work slower than 2 DIMMs.
ECC also adds to latency, but probably less so than 4 DIMMs.


Article: 159287
Subject: Re: requirement for PC for VHDL design
From: David Brown <david.brown@hesbynett.no>
Date: Fri, 23 Sep 2016 09:00:23 +0200
Links: << >>  << T >>  << A >>
On 22/09/16 17:51, Theo Markettos wrote:
> David Brown <david.brown@hesbynett.no> wrote:
>> If you have a very large working set (i.e., a lot of big files that you 
>> are reading and writing at once), so that the data can't be cached in 
>> your ram, then an SSD will often be faster.  But even then, a couple of 
>> decent HD's in raid (Linux supports top-class software raid) will often 
>> give you similar speed.
>>
>> Of course, an SSD is never a /bad/ thing - but if you have a choice of 
>> an SSD or more ram, then more ram is usually the best use of your money.
> 
> For Quartus, there are two phases with different performance
> characteristics:
> 
> Synthesis is mostly RAM-bound, except when it needs to interact with the
> on-disk database (which can be about 1GB in size).
>  
> IP Generation (mostly the Qsys tool) - when you ask it to generate
> Verilog for a system-on-chip you built, and it produces a large number of
> verilog files instantiating all the IP you need for your system.  This is
> disk bound because it's all about latency.
> 
> 
> SATA SSD will make IP generation about a factor of 2 faster, NVMe perhaps
> 1.5x faster than SATA SSD.  SATA SSD is perhaps 10% quicker for synthesis
> (figures off the top of my head, I don't have hard numbers with me).  NVMe
> didn't make much difference to synthesis.
> 
> What really kills is network filesystems.  Do not put your files on NFS, or
> worse any kind of off-premises network filesystem, because you will be in for
> much pain.  Do not put your files in Dropbox, because you will then thrash
> trying to upload them (as well as eat bandwidth for breakfast).
> 

What sort of sizes are you talking about for these files?

If you have enough ram, so that they are in your disk caches, then disk
latency will be pretty much irrelevant.  When the app writes the files,
they go into cache - the actual write to disk takes place asynchronously
unless the app specifically waits for it - the delay before hitting the
disk surface does not matter.  When the app reads the files, they are
already in cache and the data is returned immediately.  (This is on
Linux - Windows tends to wait for files to be written out, then might
clear them from cache so that they must be re-read later.)

If these files are temporaries, then the best choice of filesystem for
them is tmpfs (again, on Linux).  Even if you don't have quite enough
ram, so that the tmpfs spills into swap, it is more efficient -
structures like directories and allocation tables are entirely within
ram, and the tmpfs doesn't bother with logs, barriers, or anything else
integrity-related.  More ram and a tmpfs will beat the fastest PCIe
SSD's by orders of magnitude.


But of course an SSD is faster than an HD, as well as being more
reliable (in some ways at least), and quieter.  My point is just that
you concentrate on ram first, disk second when you are wanting to have
quick handling of files that are within the size that fits in ram.

> 
> At the moment flash is cheap enough that I won't really consider HDD any
> more except for semi-archival storage.  Though beware the cheap end of the
> consumer flash market where there's plenty of dross (5400rpm laptop HDDs are
> pretty dire too).  My current trick is buying 'prosumer' kit (eg Samsung 850
> EVO) and formatting it 7-10% short.  That gives the controller some margin
> so that performance consistency doesn't nosedive as it gets full, but is
> cheaper than buying the 'PRO' models (which are ~50% more expensive last
> time I looked at 1TB).  I have no numbers to back that up as yet, but my
> strategy is taken from staring at too many benchmark graphs.
> 

I agree with that strategy (also based on just a few numbers of my own,
and lots of "this makes sense to me" feelings).  But make sure you do
your 90-95% partitioning when the disk is new and clean, or after a full
secure erase!  Decent SSDs already have a certain amount of
overprovisioning, but leaving a little space unused at the end to
increase the overprovisioning can improve performance and lifetimes
under heavy write load (at the expense of reduced capacity, of course).


Article: 159288
Subject: Re: requirement for PC for VHDL design
From: David Brown <david.brown@hesbynett.no>
Date: Fri, 23 Sep 2016 09:09:32 +0200
Links: << >>  << T >>  << A >>
On 22/09/16 17:23, Theo Markettos wrote:
> kristoff <kristoff@skypro.be> wrote:
>> What would one see as requirements for a PC for FPGA design for a hobbyist?
>> I guess memory is the main issue. Or not?
> 
> The most critical thing involved in choosing hardware for synthesis (at
> least with Altera tools) is not what you expect.  It's Iris Pro graphics.
> And it's even better when you have Iris Pro graphics /and/ a discrete GPU.
> Even though the tools don't use the GPU for compute whatsoever.
> 
> Think I'm crazy?  Here's the explanation.
> 
> FPGA synthesis is very memory heavy.  The in-memory dataset can be large (eg
> for Cyclone V Altera recommend 6GB of memory - that probably means you want
>> 8GB DRAM if you want to use larger FPGAs or run anything else).  This
> utterly hammers the CPU cache which is tiny in comparison (2MB/core on many
> Intel parts).  That means memory latency is a big bottleneck.
> 
> Some (not all) Iris Pro parts have EDRAM, which is 32/64/128MB of DRAM in
> the CPU package.  It's intended for the GPU to have closer memory for than
> having to share DDR3/DDR4 with everything else.  However on some Haswell,
> Broadwell and Skylake parts, the EDRAM can be used as L4 cache for the CPU.
> 
> The latency of EDRAM is about half that of DDR3, and this shows in benchmark
> results - eg against a dual-socket E5-2667v2 (8 cores per socket) the
> Broadwell i7-5775c (quad-core 128MB EDRAM, 6MB L2) is about twice as quick. 
> Against an i7-6700k the Broadwell is about 10-20% quicker (I don't have the
> exact numbers here).  I tweaked other parts of the Broadwell machine with
> some excessively 'enthusiast' parts (DDR3-2400, NVMe, crazy cooler) which
> made insignificant differences but it was the CPU choice that stood out.
> 
> Now the bit I haven't benchmarked is as follows.  The L4 is relatively
> small, and so having the GPU take out a chunk isn't ideal.  So my theory
> goes that a machine with Iris Pro graphics and any old discrete GPU will
> prevent the video system using the EDRAM and so keep it all for use as L4. 
> Because I don't know exactly what the GPU drivers will use EDRAM for I
> haven't found a good way to benchmark EDRAM contention.  The two test
> machines I have are using ancient Radeon X1300 and Geforce 7700 GPUs just to
> have a basic display off the EDRAM.
> 
> The downside to this is that EDRAM is pretty rare across Intel's product
> range, particularly in desktops and servers.  However it's more common in
> laptops - which means that, if you can get the cooling package right, a
> laptop isn't a bad option for synthesis.  The other option, unless you're
> willing to go to a desktop i7-5775c or i7-5675c, or a Xeon E3-1200 v4, is
> the Skylake Skull Canyon NUC.  Despite being thermally constrained this
> clocks in about the same performance as an i7-6700k desktop with a massive
> cooling solution (the NUC is also sharing EDRAM with the GPU).
> 
> Theo
> 
> (who would be very interested if there's any standardised benchmarks out
> there for synthesis tools)
> 

Thanks for that post - it was very interesting, and I will keep those
ideas in mind if I need a fast system sometime.

There is a list of the Intel devices with eDRAM at Wikipedia (which
usually has more convenient lists than anyone else) :

<https://en.wikipedia.org/wiki/Intel_HD_and_Iris_Graphics>




Article: 159289
Subject: Re: requirement for PC for VHDL design
From: kristoff <kristoff@skypro.be>
Date: Fri, 23 Sep 2016 17:14:59 +0200
Links: << >>  << T >>  << A >>
Cecil, all,


First, thank to everybody who replied.
This has grown into quite an interesting discussion about some of the 
"underlaying" issues of FPGA design.


(inline comment)


On 18-09-16 18:05, Cecil Bayona wrote:
> You can get some very powerful machines for not too much money. I would
> get a decent I7 machine with lots of memory, that way it will be useful
> for a long time. If you are low on money, there are some choices
> available for a lot less, but get the fastest high memory machine you
> can afford and you won't suffer from regret.

Well, what got me thinking is the fact that my employer now has a 
project with HP which includes an additional reduction on the price, but 
-in the other hand- really limits my choice.

As I work about 120 km from where I live for 3 days in a week, I am more 
interested in a laptop with a limited screen-size as I do need to carry 
the thing on the train and in my backpack every day).

I do have a large external screen at home.



In addition to the limited choice, (e.g. all the devices in the project 
are all 8 GB of RAM) it has been very difficult to get more additional 
information about the devices (like, "can you extend the memory of the 
HP envy from 8 to 16 GB, how much slots whould that use and what about 
garantee if you do that?"

Also, for some reason, I find very limited information on how well 
ubuntu runs on these devices.
(I guess "no news is good news").


BTW. For some reason, more and more of these devices come with relative 
few USB slots.

Yesteray, I was testing my SPI-slave VHDL code on a cheap FPGA board 
with a mbed board, and that required three USB slots: the FPGA board, 
the mbed board and a logic analyser that set in between them.
Needless to say that the combination of altair quartus, chrome (for the 
embed board) and the logic analyser software quickly ate up all my (4 
GB) of memory I have on my current machine.



> Although a lesser machine might do, in the long run one ends regretting
> the choice. As an example I was recently working on the ep32 CPU a zero
> address CPU and found  that with Windows 10 64 bit some of the older
> software used to generate programs for it would not work right, what
> ended working right was when I used VMware virtual CPU running Windows 7
> 32 bits then everything worked flawlessly. Had my machine been not
> capable of running VMware well the issues would not have been resolved.

I simply run ubuntu natively, not in a VM.


> My FPGA machine uses an I7 at 3.4GHz, 24GB of RAM, and a 512GB SSD drive
> for the OS and virtual partitions, it can handle anything I throw at it.

OK, but to put things in perspective, I am just a hobbyist. My goal is 
to be able to try out one of the new riscv CPUs.



Perhaps I will get a olimex iCE40HX8K board that should come out in 
october and try out the "icestorm" toolchain (completely open-source 
FPGA toolchain for the ice40HX fpga's).


The people of the icestorm project claim thair toolchain uses much less 
resources then the commercial products; and they also claim that have 
been able to get one of the riscv implementations running on one board.



Cheerio! Kr. Bonne.

Article: 159290
Subject: Re: Minimal-operation shift-and-add (or subtract)
From: Hul Tytus <ht@panix.com>
Date: Sat, 24 Sep 2016 22:23:45 +0000 (UTC)
Links: << >>  << T >>  << A >>
If you mean 4 through 7 in a literal sense, that is scaling by those four 
numbers, 4 requires 2 shifts, 5 2 shifts and an add, 6 2 shifts and an add 
and seven needs 3 shifts and a subtract.

Hul

Tim Wescott <seemywebsite@myfooter.really> wrote:
> On Thu, 01 Sep 2016 18:40:25 -0400, rickman wrote:

> > On 9/1/2016 4:24 PM, Tim Wescott wrote:
> >> On Thu, 01 Sep 2016 13:19:09 -0700, lasselangwadtchristensen wrote:
> >>
> >>> Den torsdag den 1. september 2016 kl. 21.53.33 UTC+2 skrev Tim
> >>> Wescott:
> >>>> There's a method that I know, but can't remember the name.  And now I
> >>>> want to tell someone to Google for it.
> >>>>
> >>>> It basically starts with the notion of multiplying by shift-and-add,
> >>>> but uses the fact that if you shift and then either add or subtract,
> >>>> you can minimize "addition" operations.
> >>>>
> >>>> I.e., 255 = 256 - 1, 244 = 256 - 16 + 4, etc.
> >>>>
> >>>>
> >>> Booth?
> >>>
> >>> -Lasse
> >>
> >> That's it.  Thanks.
> > 
> > That is very familiar from college, but I don't recall the utility.  It
> > would be useful for multiplying by constants, but otherwise how would
> > this be used to advantage?  It would save add/subtract operations, but I
> > can't think of another situation where this would be useful.
> > 
> > If the algorithm is doing an add and shift, the add does not increase
> > the time or the hardware.  If building the full multiplier, an adder is
> > included for each stage, it is either used or not used.  When done in
> > software, the same applies.  It is easier to do the add than to skip
> > over it.

> I asked here and on comp.arch.embedded.  It's for a guy who's doing 
> assembly-language programming on a PIC12xxx -- for that guy, and for a 
> small range of constants (4 through 7), it can save time over a full-
> blown multiplication algorithm.

> -- 

> Tim Wescott
> Wescott Design Services
> http://www.wescottdesign.com

> I'm looking for work -- see my website!

Article: 159291
Subject: Re: requirement for PC for VHDL design
From: rickman <gnuarm@gmail.com>
Date: Sat, 24 Sep 2016 22:55:54 -0400
Links: << >>  << T >>  << A >>
On 9/23/2016 11:14 AM, kristoff wrote:
> Cecil, all,
>
>
> First, thank to everybody who replied.
> This has grown into quite an interesting discussion about some of the
> "underlaying" issues of FPGA design.
>
>
> (inline comment)
>
>
> On 18-09-16 18:05, Cecil Bayona wrote:
>> You can get some very powerful machines for not too much money. I would
>> get a decent I7 machine with lots of memory, that way it will be useful
>> for a long time. If you are low on money, there are some choices
>> available for a lot less, but get the fastest high memory machine you
>> can afford and you won't suffer from regret.
>
> Well, what got me thinking is the fact that my employer now has a
> project with HP which includes an additional reduction on the price, but
> -in the other hand- really limits my choice.
>
> As I work about 120 km from where I live for 3 days in a week, I am more
> interested in a laptop with a limited screen-size as I do need to carry
> the thing on the train and in my backpack every day).
>
> I do have a large external screen at home.

One thing I think is very important for a computer is to have separate 
video memory.  Someone once tried to convince me using main memory for 
the video does not appreciably impact the CPU performance, but it has to 
create a hit to the bandwidth.  I always buy laptops with separate video 
memory.  I also got 16 GB of main memory with my laptop and have never 
regretted that.  I only regretted the machine it is in, a Lenovo, lol.


> In addition to the limited choice, (e.g. all the devices in the project
> are all 8 GB of RAM) it has been very difficult to get more additional
> information about the devices (like, "can you extend the memory of the
> HP envy from 8 to 16 GB, how much slots whould that use and what about
> garantee if you do that?"
>
> Also, for some reason, I find very limited information on how well
> ubuntu runs on these devices.
> (I guess "no news is good news").
>
>
> BTW. For some reason, more and more of these devices come with relative
> few USB slots.

Maybe because they are smaller machines.  Mine has two USB 2.0 and two 
USB 3.0.  It also has HDMI, VGA and Ethernet.  But then it has a 17 inch 
screen.  lol


> Yesteray, I was testing my SPI-slave VHDL code on a cheap FPGA board
> with a mbed board, and that required three USB slots: the FPGA board,
> the mbed board and a logic analyser that set in between them.
> Needless to say that the combination of altair quartus, chrome (for the
> embed board) and the logic analyser software quickly ate up all my (4
> GB) of memory I have on my current machine.

I use Lattice devices and found their basic USB programmer would not 
work on a hub.  Can't say if that was because of the programmer or the 
hub, it was a cheap Chinese unit from Ebay.  I think I may have bought a 
name brand hub.  I should try that just to see if the programmer will 
work with it.


>> Although a lesser machine might do, in the long run one ends regretting
>> the choice. As an example I was recently working on the ep32 CPU a zero
>> address CPU and found  that with Windows 10 64 bit some of the older
>> software used to generate programs for it would not work right, what
>> ended working right was when I used VMware virtual CPU running Windows 7
>> 32 bits then everything worked flawlessly. Had my machine been not
>> capable of running VMware well the issues would not have been resolved.
>
> I simply run ubuntu natively, not in a VM.
>
>
>> My FPGA machine uses an I7 at 3.4GHz, 24GB of RAM, and a 512GB SSD drive
>> for the OS and virtual partitions, it can handle anything I throw at it.
>
> OK, but to put things in perspective, I am just a hobbyist. My goal is
> to be able to try out one of the new riscv CPUs.

Riscy?  Does that mean one with an embedded ARM on the chip?  I have a 
Microsemi board with a CM3 or CM4 on chip.  Not nearly the performance 
of the ARM11s on the X and A chips, but I'm not trying to run Linux on 
my FPGA.  I can always connect it to an rPi if I want that.


> Perhaps I will get a olimex iCE40HX8K board that should come out in
> october and try out the "icestorm" toolchain (completely open-source
> FPGA toolchain for the ice40HX fpga's).

If you need a Lattice compatible programmer to get going, I bought one 
of the Ebay clones and it seems to work ok.  I can get you details if 
you would like.


> The people of the icestorm project claim thair toolchain uses much less
> resources then the commercial products; and they also claim that have
> been able to get one of the riscv implementations running on one board.

Translation?

-- 

Rick C

Article: 159292
Subject: Re: requirement for PC for VHDL design
From: already5chosen@yahoo.com
Date: Sun, 25 Sep 2016 01:09:09 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sunday, September 25, 2016 at 5:55:56 AM UTC+3, rickman wrote:
> On 9/23/2016 11:14 AM, kristoff wrote:
> > Cecil, all,
> >
> >
> > First, thank to everybody who replied.
> > This has grown into quite an interesting discussion about some of the
> > "underlaying" issues of FPGA design.
> >
> >
> > (inline comment)
> >
> >
> > On 18-09-16 18:05, Cecil Bayona wrote:
> >> You can get some very powerful machines for not too much money. I would
> >> get a decent I7 machine with lots of memory, that way it will be useful
> >> for a long time. If you are low on money, there are some choices
> >> available for a lot less, but get the fastest high memory machine you
> >> can afford and you won't suffer from regret.
> >
> > Well, what got me thinking is the fact that my employer now has a
> > project with HP which includes an additional reduction on the price, but
> > -in the other hand- really limits my choice.
> >
> > As I work about 120 km from where I live for 3 days in a week, I am more
> > interested in a laptop with a limited screen-size as I do need to carry
> > the thing on the train and in my backpack every day).
> >
> > I do have a large external screen at home.
> 
> One thing I think is very important for a computer is to have separate 
> video memory.  Someone once tried to convince me using main memory for 
> the video does not appreciably impact the CPU performance, but it has to 
> create a hit to the bandwidth.  I always buy laptops with separate video 
> memory.  I also got 16 GB of main memory with my laptop and have never 
> regretted that.  I only regretted the machine it is in, a Lenovo, lol.
> 

Why lol?

> 
> > In addition to the limited choice, (e.g. all the devices in the project
> > are all 8 GB of RAM) it has been very difficult to get more additional
> > information about the devices (like, "can you extend the memory of the
> > HP envy from 8 to 16 GB, how much slots whould that use and what about
> > garantee if you do that?"
> >
> > Also, for some reason, I find very limited information on how well
> > ubuntu runs on these devices.
> > (I guess "no news is good news").
> >
> >
> > BTW. For some reason, more and more of these devices come with relative
> > few USB slots.
> 
> Maybe because they are smaller machines.  Mine has two USB 2.0 and two 
> USB 3.0.  It also has HDMI, VGA and Ethernet.  But then it has a 17 inch 
> screen.  lol
> 

Why lol?

> 
> > Yesteray, I was testing my SPI-slave VHDL code on a cheap FPGA board
> > with a mbed board, and that required three USB slots: the FPGA board,
> > the mbed board and a logic analyser that set in between them.
> > Needless to say that the combination of altair quartus, chrome (for the
> > embed board) and the logic analyser software quickly ate up all my (4
> > GB) of memory I have on my current machine.
> 
> I use Lattice devices and found their basic USB programmer would not 
> work on a hub.  Can't say if that was because of the programmer or the 
> hub, it was a cheap Chinese unit from Ebay.  I think I may have bought a 
> name brand hub.  I should try that just to see if the programmer will 
> work with it.
> 
> 
> >> Although a lesser machine might do, in the long run one ends regretting
> >> the choice. As an example I was recently working on the ep32 CPU a zero
> >> address CPU and found  that with Windows 10 64 bit some of the older
> >> software used to generate programs for it would not work right, what
> >> ended working right was when I used VMware virtual CPU running Windows 7
> >> 32 bits then everything worked flawlessly. Had my machine been not
> >> capable of running VMware well the issues would not have been resolved.
> >
> > I simply run ubuntu natively, not in a VM.
> >
> >
> >> My FPGA machine uses an I7 at 3.4GHz, 24GB of RAM, and a 512GB SSD drive
> >> for the OS and virtual partitions, it can handle anything I throw at it.
> >
> > OK, but to put things in perspective, I am just a hobbyist. My goal is
> > to be able to try out one of the new riscv CPUs.
> 
> Riscy?  

kristoff probably meant RISC-V.
But he is one of these people thinking that using proper case nad proper punctuation is above them...
https://en.wikipedia.org/wiki/RISC-V

> Does that mean one with an embedded ARM on the chip?  I have a 
> Microsemi board with a CM3 or CM4 on chip.  Not nearly the performance 
> of the ARM11s on the X and A chips, but I'm not trying to run Linux on 
> my FPGA. 

X and A don't have ARM11s on their chips. They have much more modern and much more fast ARM Cortex-A9.

> I can always connect it to an rPi if I want that.
> 
> 
> > Perhaps I will get a olimex iCE40HX8K board that should come out in
> > october and try out the "icestorm" toolchain (completely open-source
> > FPGA toolchain for the ice40HX fpga's).
> 
> If you need a Lattice compatible programmer to get going, I bought one 
> of the Ebay clones and it seems to work ok.  I can get you details if 
> you would like.
> 
> 
> > The people of the icestorm project claim thair toolchain uses much less
> > resources then the commercial products; and they also claim that have
> > been able to get one of the riscv implementations running on one board.
> 
> Translation?
> 
> -- 
> 
> Rick C


Article: 159293
Subject: Re: requirement for PC for VHDL design
From: rickman <gnuarm@gmail.com>
Date: Sun, 25 Sep 2016 19:10:45 -0400
Links: << >>  << T >>  << A >>
On 9/25/2016 4:09 AM, already5chosen@yahoo.com wrote:
> On Sunday, September 25, 2016 at 5:55:56 AM UTC+3, rickman wrote:
>> On 9/23/2016 11:14 AM, kristoff wrote:
>>> Cecil, all,
>>>
>>>
>>> First, thank to everybody who replied.
>>> This has grown into quite an interesting discussion about some of the
>>> "underlaying" issues of FPGA design.
>>>
>>>
>>> (inline comment)
>>>
>>>
>>> On 18-09-16 18:05, Cecil Bayona wrote:
>>>> You can get some very powerful machines for not too much money. I would
>>>> get a decent I7 machine with lots of memory, that way it will be useful
>>>> for a long time. If you are low on money, there are some choices
>>>> available for a lot less, but get the fastest high memory machine you
>>>> can afford and you won't suffer from regret.
>>>
>>> Well, what got me thinking is the fact that my employer now has a
>>> project with HP which includes an additional reduction on the price, but
>>> -in the other hand- really limits my choice.
>>>
>>> As I work about 120 km from where I live for 3 days in a week, I am more
>>> interested in a laptop with a limited screen-size as I do need to carry
>>> the thing on the train and in my backpack every day).
>>>
>>> I do have a large external screen at home.
>>
>> One thing I think is very important for a computer is to have separate
>> video memory.  Someone once tried to convince me using main memory for
>> the video does not appreciably impact the CPU performance, but it has to
>> create a hit to the bandwidth.  I always buy laptops with separate video
>> memory.  I also got 16 GB of main memory with my laptop and have never
>> regretted that.  I only regretted the machine it is in, a Lenovo, lol.
>>
>
> Why lol?

Because this laptop is a major piece of crap.  Seems the Lenovo consumer 
brand aims for a rock bottom price at the expense of quality.  It has 
many issues and is much worse than the Toshiba I had before (which I 
wasn't totally fond of).

In contrast, getting 16 GB of main memory makes it run many apps well in 
that regard.  My previous machine only had 4 GB which was very limiting.


>>> In addition to the limited choice, (e.g. all the devices in the project
>>> are all 8 GB of RAM) it has been very difficult to get more additional
>>> information about the devices (like, "can you extend the memory of the
>>> HP envy from 8 to 16 GB, how much slots whould that use and what about
>>> garantee if you do that?"
>>>
>>> Also, for some reason, I find very limited information on how well
>>> ubuntu runs on these devices.
>>> (I guess "no news is good news").
>>>
>>>
>>> BTW. For some reason, more and more of these devices come with relative
>>> few USB slots.
>>
>> Maybe because they are smaller machines.  Mine has two USB 2.0 and two
>> USB 3.0.  It also has HDMI, VGA and Ethernet.  But then it has a 17 inch
>> screen.  lol
>>
>
> Why lol?

It is the only thing of any value in this piece of crap laptop... well, 
that and the separate graphics memory.  Actually, the display is poor 
quality having only a very narrow angle of clear viewing.  Sometimes 
when I watch movies I have to choose if I want to see the top or the 
bottom of the screen clearly, not both.


>>> Yesteray, I was testing my SPI-slave VHDL code on a cheap FPGA board
>>> with a mbed board, and that required three USB slots: the FPGA board,
>>> the mbed board and a logic analyser that set in between them.
>>> Needless to say that the combination of altair quartus, chrome (for the
>>> embed board) and the logic analyser software quickly ate up all my (4
>>> GB) of memory I have on my current machine.
>>
>> I use Lattice devices and found their basic USB programmer would not
>> work on a hub.  Can't say if that was because of the programmer or the
>> hub, it was a cheap Chinese unit from Ebay.  I think I may have bought a
>> name brand hub.  I should try that just to see if the programmer will
>> work with it.
>>
>>
>>>> Although a lesser machine might do, in the long run one ends regretting
>>>> the choice. As an example I was recently working on the ep32 CPU a zero
>>>> address CPU and found  that with Windows 10 64 bit some of the older
>>>> software used to generate programs for it would not work right, what
>>>> ended working right was when I used VMware virtual CPU running Windows 7
>>>> 32 bits then everything worked flawlessly. Had my machine been not
>>>> capable of running VMware well the issues would not have been resolved.
>>>
>>> I simply run ubuntu natively, not in a VM.
>>>
>>>
>>>> My FPGA machine uses an I7 at 3.4GHz, 24GB of RAM, and a 512GB SSD drive
>>>> for the OS and virtual partitions, it can handle anything I throw at it.
>>>
>>> OK, but to put things in perspective, I am just a hobbyist. My goal is
>>> to be able to try out one of the new riscv CPUs.
>>
>> Riscy?
>
> kristoff probably meant RISC-V.
> But he is one of these people thinking that using proper case nad proper punctuation is above them...
> https://en.wikipedia.org/wiki/RISC-V
>
>> Does that mean one with an embedded ARM on the chip?  I have a
>> Microsemi board with a CM3 or CM4 on chip.  Not nearly the performance
>> of the ARM11s on the X and A chips, but I'm not trying to run Linux on
>> my FPGA.
>
> X and A don't have ARM11s on their chips. They have much more modern and much more fast ARM Cortex-A9.

I stand corrected.  The point is they have much higher end CPUs than the 
CM3 (or CM4) in the Microsemi chip.


>> I can always connect it to an rPi if I want that.
>>
>>
>>> Perhaps I will get a olimex iCE40HX8K board that should come out in
>>> october and try out the "icestorm" toolchain (completely open-source
>>> FPGA toolchain for the ice40HX fpga's).
>>
>> If you need a Lattice compatible programmer to get going, I bought one
>> of the Ebay clones and it seems to work ok.  I can get you details if
>> you would like.
>>
>>
>>> The people of the icestorm project claim thair toolchain uses much less
>>> resources then the commercial products; and they also claim that have
>>> been able to get one of the riscv implementations running on one board.
>>
>> Translation?
>>
>> --
>>
>> Rick C
>


-- 

Rick C

Article: 159294
Subject: Re: requirement for PC for VHDL design
From: kristoff <kristoff@skypro.be>
Date: Mon, 26 Sep 2016 20:44:28 +0200
Links: << >>  << T >>  << A >>
Rickman,



On 25-09-16 04:55, rickman wrote:
>> As I work about 120 km from where I live for 3 days in a week, I am more
>> interested in a laptop with a limited screen-size as I do need to carry
>> the thing on the train and in my backpack every day).

>> I do have a large external screen at home.

> One thing I think is very important for a computer is to have separate
> video memory.  Someone once tried to convince me using main memory for
> the video does not appreciably impact the CPU performance, but it has to
> create a hit to the bandwidth.  I always buy laptops with separate video
> memory.  ...

Yes. A very valid point.



>> Yesteray, I was testing my SPI-slave VHDL code on a cheap FPGA board
>> with a mbed board, and that required three USB slots: the FPGA board,
>> the mbed board and a logic analyser that set in between them.
>> Needless to say that the combination of altair quartus, chrome (for the
>> embed board) and the logic analyser software quickly ate up all my (4
>> GB) of memory I have on my current machine.
>
> I use Lattice devices and found their basic USB programmer would not
> work on a hub.  Can't say if that was because of the programmer or the
> hub, it was a cheap Chinese unit from Ebay.  I think I may have bought a
> name brand hub.  I should try that just to see if the programmer will
> work with it.

I bought a cheap powered USB 3.0 hub and both the Chinese clones of the 
Altera USB Blaster and Salea Logic Analyser work without a problem. 
(under linux, that is).



>> OK, but to put things in perspective, I am just a hobbyist. My goal is
>> to be able to try out one of the new riscv CPUs.
>
> Riscy?  Does that mean one with an embedded ARM on the chip?  I have a
> Microsemi board with a CM3 or CM4 on chip.  Not nearly the performance
> of the ARM11s on the X and A chips, but I'm not trying to run Linux on
> my FPGA.  I can always connect it to an rPi if I want that.

No, I meant risc-v. See https://riscv.org/

It's an open ISA being developed at MIT (or, in fact, a family of ISAs) 
and there are already a couple of open-source implementations of them.

64 bit versions:
Lowrisc: http://www.lowrisc.org/

SiFive: http://www.cnx-software.com/tag/fpga/
http://www.eetimes.com/document.asp?doc_id=1330086&page_number=1


32 bit versions:
Pulpino: http://www.pulp-platform.org/

f32c: https://github.com/f32c/f32c
as used here: http://www.nxlab.fer.hr/fpgarduino/

Seams like a fun project to play around with.




>> Perhaps I will get a olimex iCE40HX8K board that should come out in
>> october and try out the "icestorm" toolchain (completely open-source
>> FPGA toolchain for the ice40HX fpga's).

> If you need a Lattice compatible programmer to get going, I bought one
> of the Ebay clones and it seems to work ok.  I can get you details if
> you would like.

Olimex has released an open-source sketch for a programmer:

https://github.com/OLIMEX/iCE40HX1K-EVB/blob/master/programmer/olimexino-32u4%20firmware/iceprog.ino

This is for their ICE40HX1K board.


>> The people of the icestorm project claim thair toolchain uses much less
>> resources then the commercial products; and they also claim that have
>> been able to get one of the riscv implementations running on one board.

> Translation?
https://www.youtube.com/watch?v=bQxVaScu9tg





Cheerio! Kr. Bonne.

Article: 159295
Subject: learning verilog
From: kristoff <kristoff@skypro.be>
Date: Mon, 26 Sep 2016 20:54:55 +0200
Links: << >>  << T >>  << A >>
Hi all,


I am currently learning VHDL step by step, but I noticed there are also 
quite a lot of projects written in verilog.

So, for somebody who knows the basis, what would be best?

- First get a very good knowledge of VHDL and then start with verilog

- or learn vhdl and verilog at the same time (as the two languages do 
offer simular features).


Kristoff

Article: 159296
Subject: Re: learning verilog
From: Jan Coombs <jenfhaomndgfwutc@murmic.plus.com>
Date: Mon, 26 Sep 2016 20:12:12 +0100
Links: << >>  << T >>  << A >>
On Mon, 26 Sep 2016 20:54:55 +0200
kristoff <kristoff@skypro.be> wrote:

> Hi all,
> 
> 
> I am currently learning VHDL step by step, but I noticed there
> are also quite a lot of projects written in verilog.
> 
> So, for somebody who knows the basis, what would be best?
> 
> - First get a very good knowledge of VHDL and then start with
> verilog
> 
> - or learn vhdl and verilog at the same time (as the two
> languages do offer simular features).

Probably only you will know whether you prefer to write every
thing in triplicate, or fall between the stepping stones. 

Alternatively, if you model in MyHDL [1] it can export either, or
even both.  

Jan Coombs
--
[1] myhdl.org


Article: 159297
Subject: Re: learning verilog
From: kristoff <kristoff@skypro.be>
Date: Mon, 26 Sep 2016 21:29:21 +0200
Links: << >>  << T >>  << A >>
Jan,



On 26-09-16 21:12, Jan Coombs wrote:
>> I am currently learning VHDL step by step, but I noticed there
>> are also quite a lot of projects written in verilog.
>> So, for somebody who knows the basis, what would be best?
>> - First get a very good knowledge of VHDL and then start with
>> verilog
>> - or learn vhdl and verilog at the same time (as the two
>> languages do offer simular features).

> Probably only you will know whether you prefer to write every
> thing in triplicate, or fall between the stepping stones.

Well, my first interest is to understand the code written by others in 
the many open-source projects out there.



> Alternatively, if you model in MyHDL [1] it can export either, or
> even both.

Isn't it best first to learn (or at least to understand) the two "main" 
languages and then move on to the alternatives?



Kristoff

Article: 159298
Subject: Re: requirement for PC for VHDL design
From: rickman <gnuarm@gmail.com>
Date: Mon, 26 Sep 2016 15:39:18 -0400
Links: << >>  << T >>  << A >>
On 9/26/2016 2:44 PM, kristoff wrote:
> Rickman,
>
>
>
> On 25-09-16 04:55, rickman wrote:
>>> As I work about 120 km from where I live for 3 days in a week, I am more
>>> interested in a laptop with a limited screen-size as I do need to carry
>>> the thing on the train and in my backpack every day).
>
>>> I do have a large external screen at home.
>
>> One thing I think is very important for a computer is to have separate
>> video memory.  Someone once tried to convince me using main memory for
>> the video does not appreciably impact the CPU performance, but it has to
>> create a hit to the bandwidth.  I always buy laptops with separate video
>> memory.  ...
>
> Yes. A very valid point.
>
>
>
>>> Yesteray, I was testing my SPI-slave VHDL code on a cheap FPGA board
>>> with a mbed board, and that required three USB slots: the FPGA board,
>>> the mbed board and a logic analyser that set in between them.
>>> Needless to say that the combination of altair quartus, chrome (for the
>>> embed board) and the logic analyser software quickly ate up all my (4
>>> GB) of memory I have on my current machine.
>>
>> I use Lattice devices and found their basic USB programmer would not
>> work on a hub.  Can't say if that was because of the programmer or the
>> hub, it was a cheap Chinese unit from Ebay.  I think I may have bought a
>> name brand hub.  I should try that just to see if the programmer will
>> work with it.
>
> I bought a cheap powered USB 3.0 hub and both the Chinese clones of the
> Altera USB Blaster and Salea Logic Analyser work without a problem.
> (under linux, that is).

USB is one of those things that sounds great in theory, but has problems 
in practice.  Windows doesn't help.


>>> OK, but to put things in perspective, I am just a hobbyist. My goal is
>>> to be able to try out one of the new riscv CPUs.
>>
>> Riscy?  Does that mean one with an embedded ARM on the chip?  I have a
>> Microsemi board with a CM3 or CM4 on chip.  Not nearly the performance
>> of the ARM11s on the X and A chips, but I'm not trying to run Linux on
>> my FPGA.  I can always connect it to an rPi if I want that.
>
> No, I meant risc-v. See https://riscv.org/
>
> It's an open ISA being developed at MIT (or, in fact, a family of ISAs)
> and there are already a couple of open-source implementations of them.

Oh, my bad, you wrote riscv and I read "riscy".  lol  I'm familiar with 
risc-v, but the way you talk about the FPGAs they already have a 
processor in them.  I thought you were talking about the FPGA, but you 
mean you want to try the risc-v core and the FPGA is just the vehicle.


>>> Perhaps I will get a olimex iCE40HX8K board that should come out in
>>> october and try out the "icestorm" toolchain (completely open-source
>>> FPGA toolchain for the ice40HX fpga's).
>
>> If you need a Lattice compatible programmer to get going, I bought one
>> of the Ebay clones and it seems to work ok.  I can get you details if
>> you would like.
>
> Olimex has released an open-source sketch for a programmer:
>
> https://github.com/OLIMEX/iCE40HX1K-EVB/blob/master/programmer/olimexino-32u4%20firmware/iceprog.ino
>
>
> This is for their ICE40HX1K board.
>
>
>>> The people of the icestorm project claim thair toolchain uses much less
>>> resources then the commercial products; and they also claim that have
>>> been able to get one of the riscv implementations running on one board.
>
>> Translation?
> https://www.youtube.com/watch?v=bQxVaScu9tg

That's a 45 minute video!  But I did watch the first few minutes and saw 
the FPGA board mounted on the rPi as its dev system.  Pretty cool.

But I don't think that alone indicates economy of memory.  The chips 
they target are only a few kLUTs rather than 100s or 1000s of kLUTs. 
Still it's interesting.  I have an iCE40 project on the back burner that 
would be interesting to try with this dev system.  I've just never taken 
the time to study it enough to get it up and running.

Getting a riscv running in an iCE40 is a feat.  They only come up to 8 
kLUTs.  But still, that's not interesting to me.  I am interested in 
processors that only use a few hundred LUTs.

-- 

Rick C

Article: 159299
Subject: Re: learning verilog
From: rickman <gnuarm@gmail.com>
Date: Mon, 26 Sep 2016 15:51:22 -0400
Links: << >>  << T >>  << A >>
On 9/26/2016 2:54 PM, kristoff wrote:
> Hi all,
>
>
> I am currently learning VHDL step by step, but I noticed there are also
> quite a lot of projects written in verilog.
>
> So, for somebody who knows the basis, what would be best?
>
> - First get a very good knowledge of VHDL and then start with verilog
>
> - or learn vhdl and verilog at the same time (as the two languages do
> offer simular features).

I have learned VHDL pretty well and have used Verilog some.  I prefer 
VHDL mainly because that is what I know well.  Some have a quite strong 
opinion that Verilog is much more productive and useful.  I won't argue 
about it until I learn Verilog better.

If you are going to learn both and have a good learning book for each of 
these languages, here is one you might want to include.

HDL Chip Design, Douglas J. Smith

It has many more examples than other books and many show the same thing 
in VHDL and Verilog.  A great way to see the differences.  I only wish I 
had a copy that was updated for VHDL 2008.  VHDL 2008 is a *huge* 
improvement over previous versions.  I will never go back to limiting 
myself to older versions.

-- 

Rick C



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