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Messages from 17050

Article: 17050
Subject: How to build a NetBridge use FPGA
From: channing@my-deja.com
Date: Mon, 28 Jun 1999 16:00:07 GMT
Links: << >>  << T >>  << A >>
Hi, All,

I want to apply a FPGA to build a Net Bridge. Is there anybody advise
how I can find the reference designs or get the technical document
related to this?


Thanks a lot.



Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 17051
Subject: Re: Request for information on discontinued Xilinx XC4000-series
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 28 Jun 1999 09:07:56 -0700
Links: << >>  << T >>  << A >>
Peter, I don't understand.
A, D, H are obsolete, and L is really a version of E.
And A and H  had a totally different bitstream.

Isn't XL much cheaper than any 5-V part?

Tell me what you really need to know.

Greetings
Peter

Peter wrote:

> >XC4000         The original version of the family
> >XC4000A         Same CLB architecture as XC4000, less routing : cheaper
> >XC4000D         Same as XC4000, no CLB RAM : cheaper
> >XC4000H         Same CLB architecture as XC4000, twice as many I/O
> >XC4000L         Same CLB architecture as XC4000, lower power
>
> Are these all bitstream compatible with the original XC4k?
>
> I am talking about using my old 1992 Viewlogic 4 + 1996 XACT6.01 for a
> new design, for which I would use a small 4k device. The pricing on
> the small 4k parts is quite good, 100-off.
>
> --
> Peter.
>
> Return address is invalid to help stop junk mail.
> E-mail replies to zX80@digiYserve.com but remove the X and the Y.
> Please do NOT copy usenet posts to email - it is NOT necessary.

Article: 17052
Subject: Re: newbie -- What's the best way to get started?
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Mon, 28 Jun 1999 09:14:38 -0700
Links: << >>  << T >>  << A >>
There are several companies that provide free or low-cost software for FPGAs
and CPLDs.  Check out The Programmable Logic Jump Station at
http://www.optimagic.com/lowcost.shmtl.  The site also has links to various
software companies and to various university languages that may better suit
your need.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

raravan wrote in message ...
>As to your C/C++ question, not really, but certain higher
>level languages are being developed for hardware compilation
> which are closely related to C, such as Handel-C.  If you are interested
in
>graphics then consider the Altera UP1 board, it has VGA support and is
>fairly cheap.
>
>vrml3d.com wrote in message <7k6teh$b24$1@autumn.news.rcn.net>...
>>What's the best way to start working with FPGAs?  Can it be done for
approx
>>$500 US, or is it impossible to do anything cool without spending alot of
>>money?  Does all of the software run on commercial Unix?  Does any of it
>run
>>on Win98?  If not, Linux would be a bearable alternative.  How difficult
is
>>it to program FPGAs?  Are there any C/C++ libraries that will allow you to
>>say, for example... do something like this:
>>
>
>
>


Article: 17053
Subject: Re: 100 Billion operations per sec.!
From: husby@fnal.gov (Don HUsby)
Date: Mon, 28 Jun 1999 16:17:53 GMT
Links: << >>  << T >>  << A >>
Jonathan Feifarek <feifarek@removethis.ieee.org> wrote:
> Vaporware?  I suspect they want a customer to fund the product so they
> can start designing it.

Or they are trying to snare some unsuspecting venture capitalist and
cash in on inflated stock?  This machine was discussed here a couple of
months ago ( http://www.deja.com/[ST_rn=ps]/getdoc.xp?AN=442894814 )
To me, it looks like marketing hype that is so misleading, it borders
on fraud (or comedy).  

Their over-inflated performance numbers appear to be derived from
counting all of the possible 4-bit adders in a large number of
FPGAs.  This is unrealistic for a whole bunch of reasons.
Realistically, I would expect about 10% of the FPGA resources
to be used for "OPs" (equivalent microprocessor operations)
and the rest to be used for data path, control path, and
unusable space (even for a good, hand-crafted FPGA design,
~20% of the chip resources are unused.)

Even if you could squeeze a large number of "OPs" out of an
FPGA, these are at best simple operations.  They are not multiplies
or divides.  They aren't even close to being floating point operations.
FPGAs are very innefficient at doing floating point.  There is absolutely
no way that anyone can build a 10Gflop processor out of FPGAs for
under $1000.

I would derate any of their performance claims by a factor of 1000 to
1,000,000 for any realisitic use of their system.

Their software claims are almost as comical.  Their over-use of buzzwords
and hyperbole makes them sound like bad science fiction writers.  They make
many fantastic claims, but have yet to back them up with even a single running
(or simulated) example application.

If you are planning on investing in this company, please call me, because
I have a new type of gasoline that can make your car go 1000 miles per hour.

Article: 17054
Subject: Re: Altera EPC1 replacement?
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Mon, 28 Jun 1999 09:21:11 -0700
Links: << >>  << T >>  << A >>
There's a list of serial EPROM suppliers on The Programmable Logic Jump
Station at http://www.optimagic.com/companies.html#SPROM.  In specific, you
should investigate Atmel's serial PROMs as they offer both Xilinx and Altera
compatible devices.  See http://www.atmel.com/atmel/config.htm for more
information.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------



lewis chen wrote in message <7kqmh6$5de@netnews.hinet.net>...
>Hi,
>    How about use the EPC2 reconfigable device(PLCC 20 pin)
>                                Lewis
>Garrick Kremesec ¼¶¼g©ó¤å³¹ <376678FC.5CEA58AF@ews.uiuc.edu>...
>>Hello,
>>
>>   This was brought up recently, but are there any erasable replacements
>>for the 8 pin dip Altera EPC1?  I'm really looking for something that is
>>pin/function equivalent yet either electronically erasable or UV
>>erasable.
>>
>>Thank you for the help.
>>
>>Garrick Kremesec
>>University of Illinois
>>gkremese@ews.uiuc.edu
>
>


Article: 17055
Subject: Re: fast counter in 4013XL?
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Mon, 28 Jun 1999 10:49:10 -0700
Links: << >>  << T >>  << A >>
Ray Andraka wrote in message <3774353E.ED223757@ids.net>...
>Andy,
>
>This will generate two levels of logic.  Depending on the placement, you
could
>easily get performance even worse than 50MHz in a -09.  If you look at the
>logic required for a loadable counter without the count enable, you'll see
>that all four LUT inputs are used for each bit ( CIN ^ Q ) & (!LD) + (D &
>LD).  The code you list below adds the count enable in the bit's equation
>extending it to a 5 input function.  The synthesizer extends this to a
second
>level of logic rather than going to one bit per CLB.  If you place the
second
>level immediately adjacent to the counter you should do better, but
placement
>in VHDL is not for the faint of heart.
>
>Instead of putting the count enable in the logic, you can use the
Flip-flop's
>count enable.  Check the xilinx website on the code style required to infer
>it's use in FPGA express.  You'll also have to assert the clock enable when
>the load input is active.  The other alternative is to use the carry in as
a
>count enable, although that is slower and can be a pain to code.


The code I wrote should use the clock enable; looking at FPGA Express'
optimized output shows that indeed, all of the counter registers have their
CE inputs used.  The CE inputs are driven by an ORing of the load enable and
the count enable; the D inputs are driven by a function of the current
count, the initialization value (loaded when load asserted) and the count
enable - one level of logic.

Post place-and-route timing analysis told me that the counter can do 141
MHz.  Stuart's comments about the synthesizer results seem like they are an
excellent observation!

thanks,

-- andy
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu



Article: 17056
Subject: Re: fast counter in 4013XL?
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Mon, 28 Jun 1999 10:54:53 -0700
Links: << >>  << T >>  << A >>
Stuart Clubb wrote in message <3774ad99.782981@nntp.netcomuk.co.uk>...
>Firstly to the original poster.
>
>NEVER EVER EVER BELIEVE THE ESTIMATES FROM A SYNTHESIS TOOL.
>
>(sorry for the shouting)


Sometimes you have to shout to be heard! :)

>Or at least don't take them as gospel.
>
>I've seen this soooo many times where new users assume that the
>synthesis tool that is the most optimistic in timing/area estimates
>must be the best. Personally I feel a Synthesis tool should be
>pessimistic. Synthesis is usually fairly quick, but P&R when properly
>constrained is a considerably larger chunk of time. The tool that sets
>your expectations in excess of what the silicon can achieve will only
>disappoint later on. But by then, it's usually too late.


So, pessimism is warranted. I agree.

>All the original posters code *should* create is a "self-enabling"
>load. ie, enable and load are OR'd together and fed to the dedicated
>enable input of the flip-flops. Fortunately the code sticks with
>active high, which the right way around for 4000XL. This means that if
>the enable were to be given priority in the code, you can shave a LUT
>off the implementation. Speed should be constant though. The load
>signal then also feeds the mux-logic that will be merged into the
>FLUTs that use the carry chain etc. for the increment. Bingo, one
>level of logic in theory.


Looking at FPGA Express' schematic viewer for the optimized chip shows that
there is indeed one level of logic.

>Synthesising your example circuit to a -09 using Leonardo Spectrum
>resulted in an estimate of around under 15 ns for the critical path.
>But this was the path for through the input pin to the enable. Just
>estimating internal frequency performance gave a path delay of about
>12ns. After P&R in a 4013xl-09 this was actually 7.8 ns (128 MHz).
>Fast enough I think.


After P+R, I got a very similar result.  Friday at 6pm is not the time to
synthesize the code and not place it.  Makes for a bad weekend.  In any even
t, my results were also fast enough!

What were you guys doing all weekend on the computer, anyway? :)


-- andy
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu



Article: 17057
Subject: Re: Read/Writes to memories/register files for PIC core
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Mon, 28 Jun 1999 10:57:07 -0700
Links: << >>  << T >>  << A >>
Braam wrote in message <377746EE.E0AB3CAD@azona.com>...
>Hi,
>
>I am a bit late in this thread but why dont you write a memory like that in
>Verilog.
>It cant be too difficult. Let me know if I should help.


Easy to write; but it's more difficult to get the synthesis tool to infer
the RAM.

'twould be wonderful to have it do so.


-- a
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu



Article: 17058
Subject: Re: 100 Billion operations per sec.!
From: gah@ugcs.caltech.edu (glen herrmannsfeldt)
Date: 28 Jun 1999 18:05:37 GMT
Links: << >>  << T >>  << A >>
husby@fnal.gov (Don HUsby) writes:

(snip)

There are machines in production and in use now, both FPGA and ASIC
based, that, for specific algorithms, can do 100 GOp/s, and cost in the
$100,000 to $500,000 range.  In this case, the OP are usually 16 bit
add or compare, and are used for molecular biology problems.

>Even if you could squeeze a large number of "OPs" out of an
>FPGA, these are at best simple operations.  They are not multiplies
>or divides.  They aren't even close to being floating point operations.
>FPGAs are very innefficient at doing floating point.  There is absolutely
>no way that anyone can build a 10Gflop processor out of FPGAs for
>under $1000.

>I would derate any of their performance claims by a factor of 1000 to
>1,000,000 for any realisitic use of their system.

That depends on the problem you want to do, but for general purpose computing,
yes.   I know a problem that could require 10**21 Ops over the next two
years (about 10**8s).  This needs 10TOp/s, for maybe $1M.  

To get these rates, the algorithms must be very simple and very repetitive.

-- glen 

Article: 17059
Subject: Re: 100 Billion operations per sec.!
From: Steven Casselman <sc@vcc.com>
Date: Mon, 28 Jun 1999 11:44:37 -0700
Links: << >>  << T >>  << A >>


Jonathan Feifarek wrote:

> Vaporware?  I suspect they want a customer to fund the product so they
> can start designing it.
>

According to the artical below Gilson
coined the term "reconfigurable computing"

> http://www.pcworld.com/pcwtoday/article/0,1510,11336+1+1,00.html

The first reference to the exact phrase "reconfigurable computing"
that I could find is Pak Chan and Martine Schlag in
their the 1993 FCCM paper (page 152).

Can anyone find a earlier reference to the
exact phrase "reconfigurable computing" ?????

> They have applied for a new patent  which may knock me
> off my humble soapbox - but the existing patent cited on the web site
> has not prevented competition from companies such as VCC, Gigaops, or
> Annapolis Microsystems (who all have real products), and these companies
> hold patents of their own pre-dating this one.
> Jonathan
> --
> Jonathan F. Feifarek
> Consulting and design
> Programmable logic solutions
>

My patent predates Gilsons.
My priority date is July 29, 1992
http://www.patents.ibm.com/details?pn=US05684980__&language=en
his is
http://www.patents.ibm.com/details?pn10=US05361373
Dec 11 1992.
Brad Taylors' (gigops) priority date is Nov 5 1992
http://www.patents.ibm.com/details?pn=US05603043__
Which also predates Gilson.

I can not find any patents for Annapolis Microsystems
if you know of any let me know. (it is my job
to keep up on this stuff)



--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 17060
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Date: Monday, 28 Jun 1999 13:05:01 -0600
Links: << >>  << T >>  << A >>
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Article: 17061
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Date: Monday, 28 Jun 1999 13:44:00 -0600
Links: << >>  << T >>  << A >>
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Article: 17062
Subject: ALTERA GDF to VHDL QUESTION
From: "Asher C. Martin" <martin2@acm.uiuc.edu>
Date: Mon, 28 Jun 1999 15:13:21 -0500
Links: << >>  << T >>  << A >>
Greetings,

I am doing some undergraduate research this summer at Beckman Institute
and I am working on some VHDL code to control an analog to digital
converter for various sensors on a robot.  

I am fairly new to ALTERA's MAX+PLUS II software and have a question
regarding how to convert GDF files to straight VHDL.  I would like to
know if it is possible to tern a GDF file into a VHDL file.  

Any suggestions...?
 
Best regards,

>Asher<
(Undergraduate students @ UIUC)

<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
 Asher C. Martin
 805 West Oregon Street
 Urbana, IL 61801-3825
 (217) 367-3877
 E-MAIL: martin2@acm.uiuc.edu
 http://fermi.isdn.uiuc.edu
 telnet://fermi.isdn.uiuc.edu
 ftp://feynman.isdn.uiuc.edu
<<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>
Article: 17063
Subject: Re: 100 Billion operations per sec.!
From: "Austin Franklin" <austin@darkroom66.com>
Date: 28 Jun 1999 20:53:28 GMT
Links: << >>  << T >>  << A >>
My guess is this is all hype setup to take the company public some time
soon.

There is nothing new, or innovative, about implementing 'custom' algorithms
in hardware, in fact, that's basically what hardware is, and has been ;-)

Another thing to remember about 'patents', is, they don't necessarily mean
anything, until they are defended.  In other words, you can be granted a
patent, but that doesn't mean it's an enforceable patent.  Though there is
SOME scrutiny before you are granted the patent, but the scrutiny today is
so bad......

Also, I doubt they could really enforce 'hypercomputer' as a supposed
trademark, since it has been used, at least, for over 20 years.  This is a
growing (bad) 'trend' these days, to take two commonly used words, and
apply for a  trademark.  But, like a patent, it really doesn't mean much
until it is challenged/defended.

Austin Franklin
austin@darkroom.com

Jonathan Feifarek <feifarek@removethis.ieee.org> wrote in article
<37740990.A12B09A4@removethis.ieee.org>...
> Vaporware?  I suspect they want a customer to fund the product so they
> can start designing it.
> A call to the Star Bridge Systems sales number resulted in an exchange I
> would expect from a used car salesman.  Despite lack of any firm price,
> the $1000 computer of the future currently *starts* at $2M (later
> changed to a mere $500K) but can't be bought - only leased for $200K
> down plus $8K/mo for a 3 year minimum.  But of course this depends on
> which of many models you want, how many you want, etc., etc.
> Known work using FPGAs in Custom Computing Machines routinely break Cray
> speeds for a specific application.  This, coupled with scalability,
> hardware reuse through reconfigurability, and massive parallelism in
> execution make units such Gigaops (developed for comparing von Neumann
> type architectures) misleading if not meaningless when applied to this
> paradigm.  I suspect (especially after looking at the web site) that it
> is precisely this type of measure that is being bantered about.
> I don't dispute that FPGA based computing is 'blindingly fast' to be
> subjective, but I believe a) this technology is currently evolutionary
> rather revolutionary, and b) the afore-mentioned company has no lock on
> the technology.  They have applied for a new patent  which may knock me
> off my humble soapbox - but the existing patent cited on the web site
> has not prevented competition from companies such as VCC, Gigaops, or
> Annapolis Microsystems (who all have real products), and these companies
> hold patents of their own pre-dating this one.
> Jonathan
> -- 
> Jonathan F. Feifarek
> Consulting and design
> Programmable logic solutions
> 
> "Robert K. Veazey Jr." wrote:
> > 
> > I never heard of FPGA's until I recently read an article at CNN's
> > website <http://www.cnn.com/TECH/computing/9906/15/supercomp.idg/> that
> > said a company called Star Bridge Systems, Inc.
> > <http://www.starbridgesystems.com> has developed a revolutionary
> > computer using FPGA's that sits on a desktop & plugs into a 120v
> > standard outlet but outperforms IBM's fastest supercomputer called
> > Pacific Blue (which takes up 8,000sq.ft. floor space and uses something
> > like 3 Megawatts of power) by many times. They go on to say that this
> > company will be selling $1000 desktop computers in about 18 months that
> > are THOUSANDS of times faster than a 350PII Intel processor based
> > desktop. Here are my questions:
> > 
> > You guys(and gals) have been using FPGA's and programming for them for
> > some time now. What do all think of these claims?
> > ...
> 
Article: 17064
Subject: Re: 100 Billion operations per sec.!
From: husby@fnal.gov (Don HUsby)
Date: Mon, 28 Jun 1999 21:09:12 GMT
Links: << >>  << T >>  << A >>
gah@ugcs.caltech.edu (glen herrmannsfeldt) wrote:
> There are machines in production and in use now, both FPGA and ASIC
> based, that, for specific algorithms, can do 100 GOp/s, and cost in the
> $100,000 to $500,000 range.  In this case, the OP are usually 16 bit
> add or compare, and are used for molecular biology problems.

And you can get similar performance claims from your Sony Playstation.
I'm not questioning the basic abilities of configurable/custom computing.
I've gotten a considerable amount of processing out of FPGAs.  What I
am questioning is the marketing claims of Star Bridge Systems.  By their
way of measuring, I can tie 100 Sony playstations together with a nylon
thread and call it a teraflop supercomputer.  (And with the super-hyper-
phasic-multi-dimensional-quagulator software package, all you have to
do is think of an algorithm and it will be compiled to run on the machine.)

> That depends on the problem you want to do, but for general purpose computing,
> yes.   I know a problem that could require 10**21 Ops over the next two
> years (about 10**8s).  This needs 10TOp/s, for maybe $1M.  

We have similar requirements for theoretical physics problems (QCD).
I've built some pretty impressive (real) hardware for QCD.  It's customary
in the industry to portray your hardware in a good light, and maybe even
exaggerate a  bit, but you lose credibility pretty quickly when you glue
280 xilinx chips together, call it a 13-Teraflop supercomputer, and try
to sell it for 26 million dollars.

Article: 17065
Subject: FGPA Servo Motor Controller
From: "EKC" <NOSPAMalpha3.1@ix.netcom.com>
Date: Mon, 28 Jun 1999 17:13:44 -0400
Links: << >>  << T >>  << A >>
    I am attempting to build a PWM Servo Motor Controller card based on an
FPGA. I was wondering if anyone had any pointers to literature or other
information sources that could help me design such a system. I haven't
decided which FPGA vendor I will be using, so I would appreciate any
suggestions.

Thanks in advance,

EKC


Article: 17066
Subject: Re: Altera EPC1 replacement?
From: "Carlhermann Schlehaus" <carlhermann.schlehaus@t-online.de>
Date: Mon, 28 Jun 1999 23:22:51 +0200
Links: << >>  << T >>  << A >>
Hi,

just took a look at these pages, but all replacements for ALTERA Conf. EPROM
(need device for EPF10K / EPF6K) are also PLCC. I'd like to use a TQFP or
SOIC, thus JTAG or ISP (replacement for EPC2).

Any suggestions?

Thanx, CS

Steven K. Knapp <sknapp@optimagic.com> schrieb in im Newsbeitrag:
7l8dkg$rp8@dfw-ixnews5.ix.netcom.com...
> There's a list of serial EPROM suppliers on The Programmable Logic Jump
> Station at http://www.optimagic.com/companies.html#SPROM.  In specific,
you
> should investigate Atmel's serial PROMs as they offer both Xilinx and
Altera
> compatible devices.  See http://www.atmel.com/atmel/config.htm for more
> information.
>


Article: 17067
Subject: Re: Simple PCI card prototyping.
From: Steven Casselman <sc@vcc.com>
Date: Mon, 28 Jun 1999 15:10:23 -0700
Links: << >>  << T >>  << A >>


Austin Franklin wrote:

> Steven Casselman <sc@vcc.com> wrote in article
> <376FF120.6A53D036@vcc.com>...
> > A PCI target on an computer using an Intel PCI
> > bridge can expect 80MBytes/sec on transfers
> > going to a board and about 10-12MBytes/sec
> > comming from a board.
> >
> > These numbers vary.
>
> Do you have more specific data?  As you said, these numbers can be all over
> the place, so including a bit more about your 'results' would certainly be
> helpful...
>
> What was the size of the transfer?
> Sustained or burst?
> From where to where?
> What chip set?
> What CPU?
>
> Using the CPU to do the transfer, you might see that for a single (whose
> transfer size would be limited by the x86 instruction set) transfer, but
> certainly not sustained.
>
> Austin

The program takes an word (32-bits) buffer( 256 to 4K bytes on
word boundaries) then the CPU transfers this to board. Just
WinTell boxes. You have to write a little assembly
program (posted long ago) and call that for each of the transfers.

 start = clock();
 while(1)
 {
  for (i = 0; i < 1000; i++)
  {
     // burstbuff 65K bytes blocksize 256 - 4K bytes
     Board.write(offset,burstbuff,blocksize);
  }
  nblock += 1000;
  finish = clock();
  if (finish >= (clock_t)(start + ntick))
   break;
 }


--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 17068
Subject: Re: pessimistic synth results (was: fast counter in 4013XL?)
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Mon, 28 Jun 1999 15:36:42 -0700
Links: << >>  << T >>  << A >>
Some quick numbers using FPGA Express 3.1 and Xilinx M1.5i SP2:

The 12-bit counter mentioned before has a(n) FF-to-FF delay of about 7.2 ns
after place and route.  FPGA Express said to expect a little bit more than
20 ns.

Also, a 32-bit adder that FPGA Express told me to chuck in the trash with a
55 ns delay ended up being about 14 ns after P+R.

-- andy
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu
Andy Peters wrote in message <7l189t$2ua0$1@noao.edu>...



Article: 17069
Subject: Re: Read/Writes to memories/register files for PIC core
From: tcoonan@mindspring.com (Thomas A. Coonan)
Date: Mon, 28 Jun 1999 23:20:39 GMT
Links: << >>  << T >>  << A >>
Like I said, just saying:

   reg [7:0] my_memory[0:31];

Will typically create a flip-flop based "register file" that does
*exactly* what I need - problem is that it is flip-flops and
horribly silicon intensive.  I need a real RAM.  The above
actually (in my synthesis experience) simply elaborates from
the 2-D array into the flattened 1-D array (e.g. 256
flip-flops).

Now, everyone.  Please - the issue is not whether FPGAs
and ASICs have memories.  Of course they do.  Do they
have SYNCHRONOUS WRITEs and ASYNCHRONOUS READs.

>Hi,
>
>I am a bit late in this thread but why dont you write a memory like that in
>Verilog.
>It cant be too difficult. Let me know if I should help.
>
>
>Rickman wrote:
>
>> "Thomas A. Coonan" wrote:
>> >
>> > Hey Folks,
>> >
>> > I've spent some time discussing this issue with Wade Peterson who
>> > has a commercial version of the PIC.  If I might summarize; one way
>> > to do this required read/modify/write operation is to use a type
>> > of synchronous memory that offers SYNCHRONOUS WRITEs
>> > as well as ASYNCHRONOUS READs.  Wade has shown me
>> > an ORCA memory model that does exactly this, and infers that
>> > many of his ASIC customers must also have such a memory.
>> > I, however, do not see such a memory in the models I have access
>> > to at the moment (which are XILINX Vertex, some LSI Logic
>> > ASIC memories and some ST ASIC memories).  So.. would y'all
>> > be so kind as to indicate if you have access to such a memory?
>> > If you sent me the name of the vendor, memory name, etc. that
>> > would be great.  And again, I'm hoping that these memories are "real
>> > memories" and not just flip-flop based register files.  I'll summarize
>> > when I get some.
>>
>> I can guaranty that the Xilinx Vertex has such a memory. The Xilinx
>> parts since the XC4000E all have had a dual port synchronous SRAM built
>> into the LUT of each CLB. This will give you 32 x 1 when used as you
>> describe above which does not require a dual port memory if you cycle
>> the address using an external mux. Or you will get 16 x 1 in each CLB if
>> you want the memory to supply that mux.
>>
>> In addition, the Vertex parts supply separate blocks of memory with full
>> true dual porting. Each port can read or write independantly from the
>> other. They can even be configured for different data widths, such as 8
>> bits in on one side and 16 bits out on the other.
>>
>> In the Xilinx library the CLB SRAMs are RAM32X1S and RAM16X1D for the
>> single port synchronous and dual port synchronous memories respectively.
>> I haven't worked with the Vertex so I don't know the name of the block
>> ram.
>>
>> Where is Peter Alfke when you need him?
>>
>> --
>>
>> Rick Collins
>>
>> rick.collins@XYarius.com
>>
>> remove the XY to email me.
>>
>> Arius - A Signal Processing Solutions Company
>> Specializing in DSP and FPGA design
>>
>> Arius
>> 4 King Ave
>> Frederick, MD 21701-3110
>> 301-682-7772 Voice
>> 301-682-7666 FAX
>>
>> Internet URL http://www.arius.com
>

Article: 17070
Subject: 18+ 62321
From: ginger987@aol.com
Date: Tuesday, 29 Jun 1999 00:11:45 -0600
Links: << >>  << T >>  << A >>
Pirate Password Links Below (check 'em out before the page dies):

http://freedailyvirgins.the14u.com





h]$xFk<.(<Path: ix.netcom.com!news.maxwell.syr.edu!dispose.news.demon.net!demon!news.demon.co.uk!demon!holyrood.demon.co.uk!not-for-mail
Article: 17071
Subject: Re: Read/Writes to memories/register files for PIC core
From: Ray Andraka <randraka@ids.net>
Date: Tue, 29 Jun 1999 02:28:33 -0400
Links: << >>  << T >>  << A >>


Thomas A. Coonan wrote:

> Now, everyone.  Please - the issue is not whether FPGAs
> and ASICs have memories.  Of course they do.  Do they
> have SYNCHRONOUS WRITEs and ASYNCHRONOUS READs.

Most current devices do, including Xilinx4K/XCS, Virtex (CLB rams), Altera 10K,
and 20K.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 17072
Subject: Re: 100 Billion operations per sec.!
From: Tom Kean <tom@algotronix.com>
Date: Tue, 29 Jun 1999 13:58:55 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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Steven Casselman wrote:

> 
> My patent predates Gilsons.
> My priority date is July 29, 1992
> http://www.patents.ibm.com/details?pn=US05684980__&language=en
> his is
> http://www.patents.ibm.com/details?pn10=US05361373
> Dec 11 1992.
> Brad Taylors' (gigops) priority date is Nov 5 1992
> http://www.patents.ibm.com/details?pn=US05603043__
> Which also predates Gilson.

I think it is generally accepted that the first papers on reconfigurable
computing with FPGA's were published in the 1988/1989 timeframe.  DEC
Paris Research labs. published several papers about their Xilinx based
computer and Algotronix published several papers on their system which
used proprietary chips.

Algotronix CHS2x4 custom computer was reviewed in the International
edition
of BYTE magazine in September 1991.  

Having said that 'reconfigurable computing' was really invented by a
bunch
of very smart people in the late 60's and early 70's who did not have
the
process technology available to make it stick.

This does not mean that there are no patent issues around the
technology:
there are.  The patents mentioned above are not the ones that would
worry
me the most if I was in the reconfigurable computer business.  

Tom.
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Article: 17073
Subject: Re: Read/Writes to memories/register files for PIC core
From: Rickman <spamgoeshere4@yahoo.com>
Date: Tue, 29 Jun 1999 10:11:16 -0400
Links: << >>  << T >>  << A >>
"Thomas A. Coonan" wrote:
> 
> Like I said, just saying:
> 
>    reg [7:0] my_memory[0:31];
> 
> Will typically create a flip-flop based "register file" that does
> *exactly* what I need - problem is that it is flip-flops and
> horribly silicon intensive.  I need a real RAM.  The above
> actually (in my synthesis experience) simply elaborates from
> the 2-D array into the flattened 1-D array (e.g. 256
> flip-flops).
> 
> Now, everyone.  Please - the issue is not whether FPGAs
> and ASICs have memories.  Of course they do.  Do they
> have SYNCHRONOUS WRITEs and ASYNCHRONOUS READs.

Was I unclear in my earlier post? Let me restate...

"I can guaranty that the Xilinx Vertex has such a memory. The Xilinx
parts since the XC4000E all have had a dual port synchronous SRAM built
into the LUT of each CLB. This will give you 32 x 1 when used as you
describe above which does not require a dual port memory if you cycle
the address using an external mux. Or you will get 16 x 1 in each CLB if
you want the memory to supply that mux. 

In addition, the Vertex parts supply separate blocks of memory with full
true dual porting. Each port can read or write independantly from the
other. They can even be configured for different data widths, such as 8
bits in on one side and 16 bits out on the other. 

In the Xilinx library the CLB SRAMs are RAM32X1S and RAM16X1D for the
single port synchronous and dual port synchronous memories respectively.
I haven't worked with the Vertex so I don't know the name of the block
ram. "

So yes, there are multiple types of memory in the Xilinx Vertex devices
that have sync writes and async reads. Is there anything unclear about
that? 

-- 

Rick Collins

rick.collins@XYarius.com

remove the XY to email me.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 17074
Subject: altera flex 10k20 dedicated input
From: Sven =?iso-8859-1?Q?L=FCcke?= <luecke@esk.fhg.de>
Date: Tue, 29 Jun 1999 17:08:13 +0200
Links: << >>  << T >>  << A >>
Dies ist eine mehrteilige Nachricht im MIME-Format.
--------------DC97A38CAC877AB0819A267E
Content-Type: text/plain; charset=iso-8859-1
Content-Transfer-Encoding: 8bit

Hi, All,


is it possible to use the flex 10k20  dedicated inputs as a general
purpose input. 

Sven
-- 
Fraunhofer Institut Festkörpertechnologie

Sven Lücke			Hansastraße 32/IV
				D-80686 München
Systemtechnik/			Telefon: +49(0)89/547088-40
Telekommunikation		Telefax: +49(0)89/547088-25
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--------------DC97A38CAC877AB0819A267E--



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