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Messages from 15400

Article: 15400
Subject: Re: HDL-307 error
From: Bob Efram <efram@divide.net>
Date: Mon, 22 Mar 1999 10:02:57 -0700
Links: << >>  << T >>  << A >>

I don't know your design but from my experience, latches can be created
when 
a default "else" statement is not used  in a conditional "if" statement. 

The synthesis tool assumes that you want to latch any unspecified values
to the last value.

Check for any if statements that don't have ending "else"'s.

Bob

Jamie Morken wrote:
> 
> Hi,
> 
>     I am having a problem with my VHDL code.  I get: "Warning: Latch
> inferred in design "pc.vhd" read with hdlin_check_no_latch (HDL-307)".
>     The component will synthesize with this warning.  When I make a
> macro from the vhdl code, an input pin (inc_pc) that uses 'event is
> missing.   I use "elsif (inc_pc'event AND inc_pc ='0')" in the code.  Is
> it illegal to use 'event in an elsif?  Thanks for your time.
> 
> Jamie Morkn
Article: 15401
Subject: Re: Reconfigurable computing thesis on the web
From: Tim Tyler <tt@cryogen.com>
Date: Mon, 22 Mar 1999 17:22:47 GMT
Links: << >>  << T >>  << A >>
In comp.arch and comp.arch.fpga Zik Saleeba <zik@zikzak.net> wrote:
: Tim Tyler <tt@cryogen.com> writes:

:>[...] - or, to put it another way, I wonder if it will be too
:>expensive...?

: This may well be - it's hard to say at this stage. [...]

OK.  Apologies if I sounded a bit critical - I've only read a small
quantity of the thesis - and understood a smaller quantity of it still.

I'm fairly impressed so far - it's obvious that a lot of hard work has
gone into it.  Keep up the good work ;-)
-- 
__________
 |im |yler  The Mandala Centre  http://www.mandala.co.uk/  tt@cryogen.com

A clean disc is the sign of a sick computer.
Article: 15402
Subject: Re: Power Estimiation - report.zip (0/1)
From: s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb)
Date: Mon, 22 Mar 1999 20:18:48 GMT
Links: << >>  << T >>  << A >>
On Fri, 19 Mar 1999 16:49:14 -0800, Tom Burgess
<tom.burgess@hia.nrc.ca> wrote:

<on power figures>

>They have already claimed as much in their marketing bumf.

Depressing isn't it?

<snip>

>computer brand on the box). I don't know if the recent depressing
>Xilinx ad series went international or not, so the joke may be
>lost on Europeans if they were lucky enough to have missed it.

I saw the ad. Quite funny I thought.

<regarding tools budgets>

>I laughed out loud. In hindsight, I should have said "this exceeds
>what I sometimes jokingly refer to as my 'tools budget' by at
>least an order of magnitude", but the result is the same. 

Glad to bring a laugh to your day.

Cheers
Stuart
For Email remove "NOSPAM" from the address
Article: 15403
Subject: Re: FLEX 10K question
From: "Jason Pattison" <jason.pattison@xtra.co.nz>
Date: Tue, 23 Mar 1999 08:21:29 +1200
Links: << >>  << T >>  << A >>
If you read the *.RPT file that the compiler generates, it tells you what to
do with them.

Bill Moffitt wrote in message <36F5F698.36B77598@connect.net>...
>Can anyone help me with an Altera 10k design?  I'm going to be
>configuring a 10k device with the passive serial method (PS).  The data
>book nor the app note "configuring flex 10k devices" describe what to do
>with the tms, tdo, tdi, tck signals that are used for the jtag port.  Do
>I need to pull these up or leave them untied?
>
>TIA
>
>--
>Bill Moffitt
>
>


Article: 15404
Subject: Re: quicklogic w/ pci interface
From: "Barry Brown" <barry_brown@hp.com>
Date: Mon, 22 Mar 1999 12:56:16 -0800
Links: << >>  << T >>  << A >>
There are also some ready-made PCI bridge chips:
www.amcc.com
www.vcubed.com
www.plxtech.com
www.anchorchips.com


rk wrote in message <36F46594.D83D811A@erols.com.NOSPAM>...
>hi,
>
>does anyone have any thoughts or experience on the pci core built into
>the quicklogic fpga's?  i'm looking for an easy to use pci solution to
>make boards for some test equipment and want to spend the absolute
>minimum time fussing with pci.
>
>thanks in advance,
>
>rk
>


Article: 15405
Subject: Re: From VHDL to FPGA?
From: Wiggo Olufsen <wiggo.olufsen@online.no>
Date: Tue, 23 Mar 1999 00:37:19 +0100
Links: << >>  << T >>  << A >>
Actel has a FREE design kit containing the VHDL simulator from VeriBest.
It's free until 1st. of Feb. 2000.

Wiggo.

NO-SPAM damiano wrote:

> Ok, I started looking at VHDL. Having a lot of experience with
> programming languages it does not seem too hard to manage.
> Now I need to know a few things.
>
> Is there a free or low cost tool for circuit simulation starting from
> VHDL code?
>
> Are there VHDL examples, expecially of RISC CPU cores availble for
> free, just to learn how they are coded.
>
> Starting from VHDL, which tools a and passes do I need to have a FPGA
> working chip (I plan to use one of the low cost PC programmers to
> begin).
>
> (A question about FPGA, is it one time programmable or can it be
> re.programmed?)
> Having VHDL what changes do I need to go from FPGA to ASIC?
> I heard that Orbit accepts low volume orders, does someone know which
> is the minimal order and costs?
>
> Thanks in advance,
>
> Damiano Rullo
> Trezzano S/N
> Milan, Italy
> http://members.it.tripod.de/Damianoux/index.html
> mailto: dmn@cheerful.com
> mailto: damiano@mclink.it



--
+---------------------------------------------------------------+
| Wiggo Olufsen                                                 |
| Cypress Software AS           Phone : +47-73-52 46 59         |
| P.O.Box 2668                  Fax   : +47-73-52 46 80         |
| N-7415 TRONDHEIM              E-mail: wiggo.olufsen@online.no |
| NORWAY                                                        |
+---------------------------------------------------------------+


Article: 15406
Subject: Re: HDL-307 error
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Mon, 22 Mar 1999 16:58:41 -0700
Links: << >>  << T >>  << A >>
Jamie Morken wrote in message <36F5EBD5.50590336@uvic.ca>...
>Hi,
>
>    I am having a problem with my VHDL code.  I get: "Warning: Latch
>inferred in design "pc.vhd" read with hdlin_check_no_latch (HDL-307)".
>    The component will synthesize with this warning.  When I make a
>macro from the vhdl code, an input pin (inc_pc) that uses 'event is
>missing.   I use "elsif (inc_pc'event AND inc_pc ='0')" in the code.  Is
>it illegal to use 'event in an elsif?  Thanks for your time.


Post your code!

-- a
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

Don't waste apostrophes!  The plural of the acronym for "personal computers"
is PCs, NOT PC's.



Article: 15407
Subject: FPGA Express, STARTUPs and user clocks
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Mon, 22 Mar 1999 17:49:38 -0700
Links: << >>  << T >>  << A >>
Here's one...

I just got finished tweaking an all-VHDL design I'd finished a couple of
months ago.  (I figured out a way to make it simpler.)  Anyways, after all
of that about "can Foundation Express infer a STARTUP block" stuff, I
decided to remove the STARTUP from my top-level code.  Everything
synthesized just fine (no warnings), and P+R'd great, too.  Met timing specs
with flying colors, etc. etc.

I'm going to be configuring this particular chip using slave serial mode, so
I told the configuration tools that the startup clock was to be a User Clock
(not the CCLK output).

But, I got this complaint in BITGEN:

ERROR:x4kbs:35 - There must be a STARTUP component with a signal on the CLK
pin when StartupClk is UserClk.

This is interesting.  Should I put a pin on my top-level design called CCLK
and run that to the CLK input on the STARTUP?  And, if so, do I also hook up
the global reset net, which will give a complaint about "there is already an
implicit global reset net in this design; you've just made it explicit" ?

This is so much fun.

-- andy
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

Don't waste apostrophes!  The plural of the acronym for "personal computers"
is PCs, NOT PC's.


Article: 15408
Subject: Re: Free Xilinx Vendor Tools ... NOT :-(
From: mcgett@feynman.xsj.xilinx.com (Ed McGettigan)
Date: 22 Mar 1999 17:29:27 -0800
Links: << >>  << T >>  << A >>
In article <36F479DF.71AC4AD9@home.com>,
Richard Guerin  <guerin2@home.com> wrote:
>Would anyone care comment on why Xilinx doesn't offer some type of free
>PC based vendor tools  ? ... it seems like every other FPGA/CPLD vendor
>does :-)

We do offer free software over the web for our XC9500 CPLD
series. 

  http://www.xilinx.com/sxpresso/webftrpromo.htm

It's a fast and easy way to try out designs written in VHDL, 
Verilog, ABEL, AHDL or synthesized to XC9500 XNF or EDIF.
WebFITTER sends back all of the files including the JEDEC bits 
for programming.

Heck, we're even running a contest giving away a Diamond MP3 Rio
just for registering.

Ed McGettigan
Article: 15409
Subject: testboard for flex10k
From: stuhpg@my-dejanews.com
Date: Tue, 23 Mar 1999 02:38:22 GMT
Links: << >>  << T >>  << A >>
Hi,
I'm looking for a vendor of a testboard with A/D-D/A-Converter for
an Altera Flex10k. Additional there should be an interface to a PC.
Thanks in advance.
Paul

-----------== Posted via Deja News, The Discussion Network ==----------
http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own    
Article: 15410
Subject: Re: FLEX 10K question
From: carlhermann.schlehaus@t-online.de (Carlhermann Schlehaus)
Date: Tue, 23 Mar 1999 04:15:49 +0100
Links: << >>  << T >>  << A >>
Hi,

Bill Moffitt <compass@connect.net> schrieb in im Newsbeitrag:
36F5F698.36B77598@connect.net...
> Can anyone help me with an Altera 10k design?  I'm going to be
> configuring a 10k device with the passive serial method (PS).  The data
> book nor the app note "configuring flex 10k devices" describe what to do
> with the tms, tdo, tdi, tck signals that are used for the jtag port.  Do
> I need to pull these up or leave them untied?
>
that depends on your settings in the Compiler Options. If you read through
the device data sheet AFAIK there should be a hint to the JTAG-Interface. If
you turn in this option in the configuration of the compiler these Pins are
to be tied to GND (AFAIK). Otherwise these pins are available as User I/O
pins.
I should have a look at the data sheet to tell you on which page you can
find this information...

Ciao, Carlhermann Schlehaus


Article: 15411
Subject: Re: HDL-307 error
From: thor@sm.luth.se (Jonas Thor)
Date: Tue, 23 Mar 1999 05:33:54 GMT
Links: << >>  << T >>  << A >>
On Mon, 22 Mar 1999 10:02:57 -0700, Bob Efram <efram@divide.net>
wrote:

>Check for any if statements that don't have ending "else"'s.

.. or if any output is not specified for each "case" statement.


/ Jonas Thor
Article: 15412
Subject: Re: Free Xilinx Vendor Tools ... NOT :-(
From: Richard Guerin <guerin2@home.com>
Date: Tue, 23 Mar 1999 05:59:25 GMT
Links: << >>  << T >>  << A >>


Ed McGettigan wrote:
>
> We do offer free software over the web for our XC9500 CPLD
> series.
> 
>   http://www.xilinx.com/sxpresso/webftrpromo.htm

I'm familiar with your webfitter tool.  This approach presents a couple
of problems:

1.) It's limited to the XC9500 CPLD series of devices.

2.) There's the issue of secrity & intellectual property protection ...
In my case, both corporate and government (for DOD funded programs)

 ... I could upload my code .. but then I'd have to kill you ;-)
Article: 15413
Subject: Re: HDL-307 error
From: Nicolas Matringe <nicolas@dot.com.fr>
Date: Tue, 23 Mar 1999 09:43:20 +0100
Links: << >>  << T >>  << A >>
Jamie Morken wrote:
>     I am having a problem with my VHDL code.  I get: "Warning: Latch
> inferred in design "pc.vhd" read with hdlin_check_no_latch (HDL-307)".
>     The component will synthesize with this warning.  When I make a
> macro from the vhdl code, an input pin (inc_pc) that uses 'event is
> missing.   I use "elsif (inc_pc'event AND inc_pc ='0')" in the code. 
> Is it illegal to use 'event in an elsif?  Thanks for your time.


This reminds me of the code I posted a few days ago... If this is so, I
think the latch is inferred because of the asynchronous counter load :

IF reset = '1' THEN
  reg <= (others => '0');
ELSIF load = '1' THEN   -- This could cause the tool
  reg <= input;         -- to infer a latch
ELSIF clk = '1' AND clk'event THEN
  reg <= reg + 1;
END IF;


Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE
mail reply : remove one dot from my address (guess which :o)
Article: 15414
Subject: What do you think about philips XPLA?
From: (NO-SPAM)md7114@mclink.it (damiano)
Date: 23 Mar 1999 09:08:14 GMT
Links: << >>  << T >>  << A >>
They seem low cost available and with low cost tools.
But performance compared to Xilinx and others?

Damiano Rullo
Trezzano S/N
Milan, Italy
http://members.it.tripod.de/Damianoux/index.html
mailto: dmn@cheerful.com
mailto: damiano@mclink.it

Article: 15415
Subject: HELP ME : About JTAG on Altera Flex 10k
From: "Honey News" <honey@hyowon.pusan.ac.kr>
Date: Tue, 23 Mar 1999 21:01:35 +0900
Links: << >>  << T >>  << A >>
Hi, Everybody.

I'm learning JTAG on Altera Flex 10k.
So, I have read App. note of Altera.
But, I don't know well.

Can anybody announce me about Sequence of JTAG execution?
And, What is BSDL(Boundary-Scan Description Language)?
Is BSDL essential to JTAG?

Please, Help me.

Young Han Kim


Article: 15416
Subject: Re: FPGA Express, STARTUPs and user clocks
From: Hobson Frater <hobson@xilinx.com>
Date: Tue, 23 Mar 1999 07:31:39 -0800
Links: << >>  << T >>  << A >>
Andy,

As you know, the whole point in selecting UserClk is to synchronize the
last couple of steps of configuration (I/Os released, GSR toggled) to a
user clock.  This user clock is typically a clock that's already used on
the device.  This is to make sure that, for example, GSR doesn't get
toggled within the setup time (according to the user clock) of any or
all of your FFs.  Just think of it as trying to switch from one clock
domain to another.  Anyway, if you use this option, you must connect a
clock that you're using on the device to the CLK pin on the STARTUP
block.  Theoretically you could have a signal called CCLK come onto your
device and drive only this pin, but this may defeat the purpose of using
the UserClk option because it won't be driving any of the on-chip
logic..

As for GSR and the STARTUP block, this input is completely independant
of the CLK input.  In fact, all three inputs (GSR, GTS, and CLK) are
independant of one another and thus you don't "have to" hook up your
reset net to the GSR pin if you don't want to.

Regards,
Hobson Frater
Xilinx Applications

Article: 15417
Subject: viterbi coder/decoder
From: Andres David Garcia Garcia <garcia@elec.enst.fr>
Date: Tue, 23 Mar 1999 17:15:20 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------43B0F34829C7489DBC332C9C
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

HI,

I'd like to know if anybody is or was working on a design of a viterbi
coder/decoder
or a treillis application using FPGAs.

thank you

Andres David

--------------43B0F34829C7489DBC332C9C
Content-Type: text/x-vcard; charset=us-ascii;
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Content-Transfer-Encoding: 7bit
Content-Description: Card for Andres David Garcia Garcia
Content-Disposition: attachment;
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begin:vcard 
n:Garcia Garcia;Andres David
tel;pager:http://www-elec.enst.fr/~garcia/index.html
tel;fax:(33-1)-45-80-40-36
tel;home:(33-1)-44-16-18-90
tel;work:(33-1)-45-81-78-03
x-mozilla-html:TRUE
org:Ecole Nationale Superieure des Telecommunications; Dept. Communications et Electronique
version:2.1
email;internet:garcia@elec.enst.fr
title:PhD Student on Electronics and Communications
adr;quoted-printable:;;46, rue Barrault=0D=0A;Paris;;75634;France
fn:Andres David Garcia Garcia
end:vcard

--------------43B0F34829C7489DBC332C9C--

Article: 15418
Subject: Re: LCD driver
From: Sven =?iso-8859-1?Q?L=FCcke?= <luecke@st.ift.fhg.de>
Date: Tue, 23 Mar 1999 17:19:16 +0100
Links: << >>  << T >>  << A >>
Dies ist eine mehrteilige Nachricht im MIME-Format.
--------------600ECAA70DA36B51D78135B3
Content-Type: text/plain; charset=iso-8859-1
Content-Transfer-Encoding: 8bit

Hi,

I wrote nearly the same thing. Maybe you can use this.
I used constant pattern like this

CONSTANT Pattern0 : std_logic_vector := "0000001" ;	
CONSTANT Pattern1 : std_logic_vector := "1001111" ;	
CONSTANT Pattern2 : std_logic_vector := "0010010" ;	
CONSTANT Pattern3 : std_logic_vector := "0000110" ;	
CONSTANT Pattern4 : std_logic_vector := "1001100" ;	
CONSTANT Pattern5 : std_logic_vector := "0100100" ;		
CONSTANT Pattern6 : std_logic_vector := "0100000" ;	
CONSTANT Pattern7 : std_logic_vector := "0001111" ;	
CONSTANT Pattern8 : std_logic_vector := "0000000" ;	
CONSTANT Pattern9 : std_logic_vector := "0001100" ;	
CONSTANT PatternA : std_logic_vector := "0001000" ;		
CONSTANT PatternB : std_logic_vector := "1100000" ;	
CONSTANT PatternC : std_logic_vector := "1110010" ;		
CONSTANT PatternD : std_logic_vector := "1000010" ;	
CONSTANT PatternE : std_logic_vector := "0110000" ;	
CONSTANT PatternF : std_logic_vector := "0111000" ;	

and i think bcd input is wrong youn cant use integer.
You must use an vector lie this :

	bcd : IN std_logic_vector(0 TO 3);
I hope this can help you.
If you want I can mail you my source code.

Sven

vitalyh@hotmail.com schrieb:
> 
> Hi,
> 
> I wrote BCD-to-7Segment driver for LCD, something like 74HC/HCT4543.
> When I synthesize it in Warp, everything is fine. But  Altera Max+II 9.01
> gives it a hard time. There are 590(!) warning messages with Flex rules and
> the device doesn't work at all. How can I change the design to satisfy
> Altera?
> 
> ------------------------
> ---- bcd to lcd --------
> ------------------------
> library ieee ;
> use ieee.std_logic_1164.all ;
> entity aldera10 is
>    port ( bcd           : in integer range 0 to 9     ;
>           lt, rbi, pol  : in std_logic                      ;
>           abcdefg       : buffer std_logic_vector (6 downto 0) ;
>           rbo           : buffer std_logic                   ) ;
> end aldera10 ;
> architecture arc_aldera10 of aldera10 is
> begin
>    process(lt,rbi,pol,bcd)
>    begin
>      if (lt='1' and pol='1') then
>         abcdefg <= "1111111" ;
>         rbo <= '0' ;
>      elsif (lt='1' and pol='0') then
>          abcdefg <= "0000000" ;
>          rbo <= '0' ;
>      elsif (rbi='0' and pol='1') or (rbi='1' and bcd/=0 and pol='1') then
>         if bcd = 0 then
>               abcdefg <= "1111110" ;
>         elsif bcd = 1 then
>               abcdefg <= "0110000" ;
>         elsif bcd =  2 then
>               abcdefg <= "1101101" ;
>         elsif bcd = 3 then
>               abcdefg <= "1111001" ;
>         elsif bcd = 4 then
>               abcdefg <= "0110010" ;
>         elsif bcd = 5 then
>               abcdefg <= "1011011" ;
>         elsif bcd = 6 then
>               abcdefg <= "1011111" ;
>         elsif bcd = 7 then
>               abcdefg <= "1110000" ;
>         elsif bcd = 8 then
>               abcdefg <= "1111111" ;
>         elsif bcd = 9 then
>               abcdefg <= "1111011" ;
>         else
>               abcdefg <= "1011011" ;     -- for invalide values
>    end if ;
>    rbo <= '0' ;
>      elsif (rbi='0' and pol='0') or (rbi='1' and bcd/=0 and pol='0') then
>       if bcd = 0 then
>            abcdefg <= "0000001" ;
>      elsif bcd = 1 then
>            abcdefg <= "1001111" ;
>      elsif bcd =  2 then
>            abcdefg <= "0010010" ;
>      elsif bcd = 3 then
>            abcdefg <= "0000110" ;
>      elsif bcd = 4 then
>            abcdefg <= "1001100" ;
>      elsif bcd = 5 then
>            abcdefg <= "0100100" ;
>      elsif bcd = 6 then
>            abcdefg <= "0100000" ;
>      elsif bcd = 7 then
>            abcdefg <= "0001111" ;
>      elsif bcd = 8 then
>            abcdefg <= "0000000" ;
>      elsif bcd = 9 then
>            abcdefg <= "0000100" ;
>      else
>            abcdefg <= "0100100" ;     --for invalide values
>     end if;
>     rbo <='0' ;
>      elsif (rbi='1' and bcd=0 and pol='0') then
>          abcdefg <= "1111111" ;
>        rbo <= '1' ;
>      elsif (rbi='1' and bcd=0 and pol='1') then
>          abcdefg <= "0000000" ;
>        rbo <= '1' ;
>    end if ;
> end process;
> end arc_aldera10;
> 
> ---------------------------- --- bcd to_lcd ( 3 in 1)----
> ---------------------------- library ieee ; use ieee.std_logic_1164.all ;
> entity aldera100 is  port ( bcd1, bcd2, bcd3  : in integer range 0 to 9  ;
> lt, rbi, pol  : in std_logic  ;  abcdefg1, abcdefg2, abcdefg3 : buffer
> std_logic_vector (6 downto 0)); end aldera100 ; architecture arc_aldera100 of
> aldera100 is component aldera10  port ( bcd  : in integer range 0 to 9  ;
> lt, rbi, pol  : in std_logic  ;  abcdefg  : buffer std_logic_vector (6 downto
> 0) ;  rbo  : buffer std_logic  ) ; end component ;
> 
>   signal  rbi2, rbi3  : std_logic ;
> begin
>  lcd1: aldera10 port map(bcd1,lt,rbi ,pol,abcdefg1,rbi2 ) ;
>  lcd2: aldera10 port map(bcd2,lt,rbi2,pol,abcdefg2,rbi3 ) ;
>  lcd3: aldera10 port map(bcd3,lt,rbi3,pol,abcdefg3,open ) ;
> end arc_aldera100;
> regards,
> Vitaly.
> 
> -----------== Posted via Deja News, The Discussion Network ==----------
> http://www.dejanews.com/       Search, Read, Discuss, or Start Your Own

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Article: 15419
Subject: Re: FPGA Express, STARTUPs and user clocks
From: "Andy Peters" <apeters@noao.edu.NOSPAM>
Date: Tue, 23 Mar 1999 09:31:23 -0700
Links: << >>  << T >>  << A >>
Andy Peters wrote in message <7d6ojt$gip$1@noao.tuc.noao.edu>...

>I'm going to be configuring this particular chip using slave serial mode,
so
>I told the configuration tools that the startup clock was to be a User
Clock
>(not the CCLK output).
>
>This is interesting.  Should I put a pin on my top-level design called CCLK
>and run that to the CLK input on the STARTUP?  And, if so, do I also hook
up
>the global reset net, which will give a complaint about "there is already
an
>implicit global reset net in this design; you've just made it explicit" ?


I had it all confused.  It's still configured by CCLK, and that has nothing
to do with the sequence of events AFTER configuration.  I just told it to
use CCLK instead of UserClock for the StartUp clock and all is well.  I
confused Startup Clock and Configuration clock.  This chip is going to be
configured in slave serial mode; everything else I've done has either been
master parallel or master slave, and I put two and two together and
interpreted the correct result (twenty-two, of course) incorrectly...

Thanks to Hobson at Xilinx for the quick response.

This is STILL so much fun.


-- a
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu

Don't waste apostrophes!  The plural of the acronym for "personal computers"
is PCs, NOT PC's.



Article: 15420
Subject: Re: Xilinx Batchfile?
From: Rick <rick@algor.co.uk>
Date: Tue, 23 Mar 1999 16:43:36 +0000
Links: << >>  << T >>  << A >>
Bruce Nepple wrote:
> 
> Do you have a batchfile that will work with Foundation Express HDL flow?
> Is there a sample batchfile in that mess somewhere that I've missed?
> 
> bruce
> 
> Peter <z80@ds2.com> wrote in article
> <36f54871.333079883@news.netcomuk.co.uk>...
> | I can't agree more, especially for projects which one needs to revisit
> | years later.
> 

Absolutely. The GUI usefulness just barely extends beyond the demo you
got from the salesman. As soon as you try and do anything serious it
becomes more and more of an obstruction.

To the original poster: Even though it looks pretty intimidating its
really worth puting in the effort to at least learn the basics of
``make''. If you've got a PC version of emacs you could teach yourself a
lot from the info section on g(nu)make.
Or plead with a s/w engineer for a morning's basic instruction. [Why are
tools such as make, RCS, CVS considered by the EDA vendors to be beyond
the scope of h/w engineers ? I, personally, consider that insulting]

Once you have got at least some of it understood it makes design
integration very simple. In my case I use it not only to keep track of
the synthesis but also to keep synth and simulation in synchronisation.

BTW: What Xilinx verion control ? As far as I'm aware all it does is
archive a routed design with absolutely no record of how  and from what
the design was built.
Article: 15421
Subject: Anyone know what happened to www.prep.org
From: Ken Boorom <KEN_BOOROM@NOSPAM_HP.COM>
Date: Tue, 23 Mar 1999 10:42:36 -0700
Links: << >>  << T >>  << A >>
I noticed that the Programmable Electronics Performance
Corp's domain has disappeared (web site was www.prep.org)

They used to post Verilog sources, and the synthesis
results targetting FPGA's, to be used as benchmarks.

Does anyone know what happened to them?

-Ken
Article: 15422
Subject: Re: ALTERA Byteblaster configuration for DOS and LINUX
From: "Lev Razamat" <lrazamat@netvision.net.il>
Date: Tue, 23 Mar 1999 21:20:33 +0200
Links: << >>  << T >>  << A >>
here is attachment with simple, working C source
you have to prepare *.rbf file and this file is loadable with this program
no config signal used to reset FPGA, you have reset your FPGA manualy or add
extra wire

danger <danger@enst.fr> wrote in message news:36F6654F.6CC1E4FB@enst.fr...
>Has anybody a small routine to configure ALTERA devices via the
>Byteblaster from a DOS and and LINUX system ?
>
>Thank you
>
>--
>Jean-Luc DANGER                       email : danger@enst.fr
>ENST/dpt ComElec   46 rue Barrault               75013 PARIS
>Phone : 01 45 81 81 17                  Fax : 01 45 80 40 36
>
>


begin 666 La.cpp
M(VEN8VQU9&4@/'-T9&EO+F@^#0HC:6YC;'5D92 \9&]S+F@^#0H-"G5N<VEG
M;F5D(&-H87(@<F)T6S(U-C P,%T[#0IU;G-I9VYE9"!I;G0@;&5N/3 [#0I&
M24Q%("IR8F$[#0H-"G9O:60@;&]A9%]A;'1E<F$H=F]I9"D-"GL-"B @=6YS
M:6=N960@8VAA<B!A+&(L8SL-"B @9F]R("AU;G-I9VYE9"!I;G0@:3TP.VD\
M;&5N.VDK*RD-"B @>PT*(" @(&$]<F)T6VE=.PT*(" @(&9O<B H:6YT(&H]
M,#MJ/#@[:BLK*0T*(" @('L-"B @(" @(&(]82 F(#$[#0H)("!B(#T@*&(@
M*B R*2 F(#([#0H@(" @("!B/6([( T*(" @(" @8SUB('P@,'@Q.R @(" )
M"2 @(" O+V0Q("T@9&%T83L)<&EN,PT*(" @(" @;W5T<&]R=&(H,'@S-S@L
M8BD[(" )+R]D," M(&-L;V-K.PEP:6XR#0H@(" @("!O=71P;W)T8B@P>#,W
M."QC*3L-"B @(" @(&]U='!O<G1B*#!X,S<X+&(I.PT*(" @(" @83UA(#X^
M(#$[#0H@(" @?0T*("!]#0H@(&]U='!O<G1B*#!X,S<X+# I.PT*?0T*#0IV
M;VED(&UA:6XH:6YT(&%R9V,L8VAA<B J87)G=EM=*0T*>PT*("!R8F$]9F]P
M96XH87)G=ELQ72PB<F(B*3L-"B @;&5N/69R96%D*')B="PQ+#8T,# P+')B
M82D[#0H@(&9C;&]S92AR8F$I.PT*("!I9B H<F)T6S!=/3TP>&9F("8F(')B
M=%LQ73T],'AF9BD-"B @("!L;V%D7V%L=&5R82@I.PT*("!E;'-E#0H@(" @
E<')I;G1F*")7<F]N9R!F:6QE(&9O<FUA=%QN(BD[#0H-"GT-"@``
`
end

Article: 15423
Subject: Virtual Socket meeting
From: sbaker@best.com (Stan Baker)
Date: Tue, 23 Mar 1999 19:20:44 GMT
Links: << >>  << T >>  << A >>
The VSI Alliance European member meeting is being held in Paris on
April 19 at the Le Meridien Etoile Hotel.

The program will include technical presentations about new Virtual
Socket Interface specifications, and discussions about key issues of
System Level Design and On-Chip Busses.  Also, get the latest updates
on the VSIA mission, organization, and pilot projects.  Get the
details about this informative meeting from the VSIA website at
www.vsi.org

If you're not in Europe, please inform your interested colleagues who
are.

To register, please email Flornece at office@ecsi.alpes-net.fr and
include:
Name
Company
Title
Phone Number
Fax Number
Email Address

Hope to see you there,
Stan Baker
VSI Alliance


Article: 15424
Subject: Re: FPGA Express FSM Synthesis Concern
From: Brian Boorman <XZY.bboorman@harris.com>
Date: Tue, 23 Mar 1999 14:54:13 -0500
Links: << >>  << T >>  << A >>
Not true. You can mix comnbinational and registered ouptuts in same
process.

For example...

pTest: process (reset, clock, {comb. signals})
begin
  if (reset = '1') then
    ...reset registered sig's here
  elsif (rising_edge(clock)) then
    ...registered sig assigns
  end if;
  ... comb assigns here
end process;

Bruce Nepple wrote:
> 
> I don't think that can be done.  If you have 1 output that is the OR of two
> states, then you need a comb. output.  If you are inferring flip-fops in a
> process you can't have comb. outputs.
> 
> bruce
> 

-- 
Brian C. Boorman
Harris RF Communications
Rochester, NY 14610
XYZ.bboorman@harris.com
<Remove the XYZ. for valid address>


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