Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 19500

Article: 19500
Subject: HDL to graphic conversion
From: #YEO WEE KWONG# <P7102672H@ntu.edu.sg>
Date: Tue, 28 Dec 1999 13:01:26 +0800
Links: << >>  << T >>  << A >>
Hi,

Anyone come across any tools that does the above. By the way, does
xilinx foundation s/w provide the above avenue.

Thanks.

Article: 19501
Subject: Re: xilinx help *desperately* needed
From: "Matt Billenstein" <mbillens@one.net>
Date: Tue, 28 Dec 1999 05:02:32 GMT
Links: << >>  << T >>  << A >>
You say that the "falling edge should latch the data off the bus..." but
you're using if rising_edge(hc11_e) then

...  Also, take a look in the FPGA editor and actually follow the signal off
of the input PAD, through the register, and out onto the output PAD checking
along the way that you're really registering the data on the proper clock
edge and that your clock enable looks good and so on and so forth...

l8r

m

Matt Billenstein
http://w3.one.net/~mbillens/
mbillens@one.net


"Susan Deike" <jonathan@canuck.com> wrote in message
news:8495gu$q0j$1@cleavage.canuck.com...
| I'm working on a design of moderate complexity in 5V Spartan using
| Foundation 2.1i sp3 (yeah, I know.  just let me get over this problem,
| lord, and I'll move to the HP...).
|
| The problem is that I can't get a D register in the device to latch data
| off of my microprocessor's (68HC11) data bus.  My original target is an
| XCS40, but I've built a proto using an XCS10 to try to isolate this
problem.
|
| Both protos exhibit exactly the same behaviour:  The combinatorial logic
| (address decoders) work just fine.  When I probe the clock enable signal
| (flashreg) out it's exactly what and where it should be, valid 50nS before
| and after the system (e) clock, the falling edge of which should latch the
| data off of the bus.  Scope shows the data to be good as well, just never
| appears on the register output
|
| This one's serious, folks.  If it were just me being stupid it wouldn't be
| so bad, but it's also baffling the local FAE and rep.  Major inspiration
| needed from major smart person.
|
| Thanks much.
|
| Jonathan Levine
|
|
|
| ----- details below -----
|
|
|
| Attached is the vhdl source and the ucf file, verbatim.  Device is 5V
XCS10
| in PLCC84.  Each pair of power supply pins is decoupled.  MODE pin is
pulled
| up and INIT pin is pulled down (I'm using JTAG for programming via the
| parallel cable).  All other pins not listed in the ucf are NC (floating).
|
|
|
| ----- vhdl source -----
|
|
|
| -- stripped-down test to see if data can be latched offa the bus
| -- Last revised Dec 27/99
|
| library ieee;
| use ieee.std_logic_1164.all;
|
| entity hc11_dec is
|     port (
|         hc11_a: in std_logic_vector(15 downto 8);
|         hc11_d: in std_logic_vector(1 downto 0);
| hc11_e: in std_logic;
| hc11_rw: in std_logic;
| hc11_as: in std_logic;
| hc11_reset: in std_logic;
|
| hc11_fa: out std_logic_vector(1 downto 0);
|
|         hc11_romcs: out std_logic;
| hc11_memoe: out std_logic;
|
| hc11_dpramcs: out std_logic;
| hc11_duartcs: out std_logic;
| hc11_ramcs: out std_logic
|     );
|
| end hc11_dec;
|
| architecture rtl of hc11_dec is
|
| signal flashreg: std_logic;
|
| begin
|
| hc11_dpramcs <= '1';
| hc11_duartcs  <= '1';
| hc11_ramcs <= '1';
|
| -- eprom
|
| hc11_romcs <= '0' when (((hc11_a >= x"e0") and (hc11_a <= x"ff"))
| and (hc11_as = '0') and (hc11_rw = '1')) else '1';
|
| hc11_memoe <= '0' when (((hc11_a >= x"e0") and (hc11_a <= x"ff"))
| and (hc11_as = '0') and (hc11_rw = '1')) else '1';
|
| -- flashreg
|
| flashreg <= '1' when ((hc11_a = x"b4") and (hc11_as = '0')
| and (hc11_rw = '0')) else '0';
|
| process (flashreg, hc11_d, hc11_e, hc11_reset)
|
| begin
|
| -- latch data lsb into flash address lsb
|
| if rising_edge(hc11_e) then
| if (flashreg = '1') then
| hc11_fa(0) <= hc11_d(0);
| end if;
| end if;
|
| end process;
|
| end rtl;
|
|
|
| ----- ucf file -----
|
|
|
| ##############################################
| #      BASIC UCF SYNTAX EXAMPLES V2.1.6      #
| ##############################################
| #
| # The "#" symbol is a comment character.   To use this sample file, find
the
| # specification necessary, remove the comment character (#) from the
beginning
| # of the line, and modify the line (if necessary) to fit your design.
| #
| #              TIMING SPECIFICATIONS
| #
| # Timing specifications can be applied to the entire device (global) or to
| # specific groups in your design (called "time groups'). The time groups
are
| # declared in two basic ways.
| #
| # Method 1: Based on a net name, where 'my_net' is a net that touches all
the
| #           logic to be grouped in to 'logic_grp'. Example:
| #NET my_net TNM_NET = logic_grp ;
| #
| # Method 2: Group using the key word 'TIMEGRP' and declare using the names
of
| #           logic in your design. Example:
| #TIMEGRP group_name = FFS ("U1/*");
| #           creates a group called 'group_name' for all flip-flops within
| #           the hierarchical block called U1. Wildcards are valid.
| #
| # Grouping is very important because it lets you tell the software which
parts
| # of a design run at which speeds.  For the majority of the designs with
only
| # one clock, use simple global constraints.
| #
| # The type of grouping constraint you use can vary depending on the
synthesis
| # tools you are using.  Foundation Express does better with Method 2.
| #
| #
| ############################################################
| # Internal to the device clock speed specifications - Tsys #
| ############################################################
| #
| # data      _________      /^^^^^\       _________   out
| # ----------| D   Q |-----{ LOGIC } -----| D   Q |------
| #           |       |      \vvvvv/       |       |
| #        ---|> CLK  |                 ---|> CLK  |
| # clock  |  ---------                 |  ---------
| # ------------------------------------
| #
| # ---------------
| # Single Clock
| # ---------------
| #
| # ----------------
| # PERIOD TIME-SPEC
| # ----------------
| # The PERIOD spec. covers all timing paths that start or end at a
| # register, latch, or synchronous RAM which are clocked by the reference
| # net (excluding pad destinations).  Also covered is the setup
| # requirement of the synchronous element relative to other elements
| # (ex. flip flops, pads, etc...).
| # NOTE:  The default unit for time is nanoseconds.
| #
| #NET clock PERIOD = 50ns ;
| #
| #       -OR-
| #
| # ------------------
| # FROM:TO TIME-SPECs
| # ------------------
| # FROM:TO style timespecs can be used to constrain paths between time
| # groups.  NOTE:  Keywords:  RAMS, FFS, PADS, and LATCHES are predefined
| # time groups used to specify all elements of each type in a design.
| #TIMEGRP RFFS = RISING FFS ("*");  // creates a rising group called RFFS
| #TIMEGRP FFFS = FALLING FFS ("*");  // creates a falling group called FFFS
| #TIMESPEC TSF2F  = FROM : FFS   : TO : FFS   : 50 ns; // Flip-flips with
the same edge
| #TIMESPEC TSR2F  = FROM : RFFS  : TO : FFFS  : 25 ns; // rising edge to
falling edge
| #TIMESPEC TSF2R  = FROM : FFFS  : TO : RFFS  : 25 ns; // falling edge to
rising edge
| #
| # ---------------
| # Multiple Clocks
| # ---------------
| # Requires a combination of the 'Period' and 'FROM:TO' type time
specifications
| #NET clock1 TNM_NET = clk1_grp ;
| #NET clock2 TNM_NET = clk2_grp ;
| #
| #TIMESPEC TS_clk1 = PERIOD : clk1_grp : 50 ;
| #TIMESPEC TS_clk2 = PERIOD : clk2_grp : 30 ;
| #TIMESPEC TS_ck1_2_ck2 = FROM : clk1_grp : TO : clk2_grp : 50 ;
| #TIMESPEC TS_ck2_2_ck1 = FROM : clk2_grp : TO : clk1_grp : 30 ;
| #
| #
| ############################################################
| # CLOCK TO OUT specifications - Tco                        #
| ############################################################
| #
| # from      _________      /^^^^^\       --------\
| # ----------| D   Q |-----{ LOGIC } -----| Pad    >
| # PLD       |       |      \vvvvv/       --------/
| #        ---|> CLK  |
| # clock  |  ---------
| # --------
| #
| # ----------------
| # OFFSET TIME-SPEC
| # ----------------
| # To automatically include clock buffer/routing delay in your
| # clock-to-out timing specifications, use OFFSET constraints .
| # For an output where the maximum clock-to-out (Tco) is 25 ns:
| #
| #NET out_net_name OFFSET = OUT 25 AFTER clock_net_name ;
| #
| #      -OR-
| #
| # ------------------
| # FROM:TO TIME-SPECs
| # ------------------
| #TIMESPEC TSF2P  = FROM : FFS   : TO : PADS  : 25 ns;
| # Note that FROM: FFS : TO: PADS constraints start the delay analysis
| # at the flip flop itself, and not the clock input pin.  The recommended
| # method to create a clock-to-out constraint is to use an OFFSET
constraint.
| #
| #
| ############################################################
| # Pad to Flip-Flop speed specifications - Tsu              #
| ############################################################
| #
| # ------\         /^^^^^\       _________   into PLD
| # |pad   >-------{ LOGIC } -----| D   Q |------
| # ------/         \vvvvv/       |       |
| #                            ---|> CLK  |
| # clock                      |  ---------
| # ----------------------------
| #
| # ----------------
| # OFFSET TIME-SPEC
| # ----------------
| # To automatically account for clock delay in your input setup timing
| # specifications, use OFFSET constraints.
| # For an input where the maximum setup time is 25 ns:
| #NET in_net_name OFFSET = IN 25 BEFORE clock_net_name ;
| #
| #      -OR-
| #
| # ------------------
| # FROM:TO TIME-SPECs
| # ------------------
| #TIMESPEC TSP2F  = FROM : PADS  : TO : FFS   : 25 ns;
| # Note that FROM: PADS : TO: FFS constraints do not take into account any
| # delay for the clock path.  The recommended method to create an input
| # setup time constraint is to use an OFFSET constraint.
| #
| #
| ############################################################
| # Pad to Pad speed specifications - Tpd                    #
| ############################################################
| #
| # ------\         /^^^^^\       -------\
| # |pad   >-------{ LOGIC } -----| pad   >
| # ------/         \vvvvv/       -------/
| #
| # ------------------
| # FROM:TO TIME-SPECs
| # ------------------
| #TIMESPEC TSP2P  = FROM : PADS  : TO : PADS  : 125 ns;
| #
| #
| ############################################################
| # Other timing specifications                              #
| ############################################################
| #
| # -------------
| # TIMING IGNORE
| # -------------
| # If you can ignore timing of paths, use Timing Ignore (TIG). NOTE: The
| # "*" character is a wild card, which can be used for bus names.  A "?"
| # character can be used to wild-card one character.
| # Ignore timing of net reset_n:
| #NET : reset_n : TIG ;
| #
| # Ignore data_reg(7:0) net in instance mux_mem:
| #NET : mux_mem/data_reg* : TIG ;
| #
| # Ignore data_reg(7:0) net in instance mux_mem as related to a TIMESPEC
| # named TS01 only:
| #NET : mux_mem/data_reg* : TIG = TS01 ;
| #
| # Ignore data1_sig and data2_sig nets:
| #NET : data?_sig : TIG ;
| #
| # ---------------
| # PATH EXCEPTIONS
| # ---------------
| # If your design has outputs that can be slower than others, you can
| # create specific timespecs similar to this example for output nets
| # named out_data(7:0) and irq_n:
| #TIMEGRP slow_outs = PADS(out_data* : irq_n) ;
| #TIMEGRP fast_outs = PADS : EXCEPT : slow_outs ;
| #TIMESPEC TS08 = FROM : FFS : TO : fast_outs : 22 ;
| #TIMESPEC TS09 = FROM : FFS : TO : slow_outs : 75 ;
| #
| # If you have multi-cycle FF to FF paths, you can create a time group
| # using either the TIMEGRP or TNM statements.
| #
| # WARNING:  Many VHDL/Verilog synthesizers do not predictably name flip
| # flop Q output nets.  Most synthesizers do assign predictable instance
| # names to flip flops, however.
| #
| # TIMEGRP example:
| #TIMEGRP slowffs = FFS(inst_path/ff_q_output_net1* :
| #inst_path/ff_q_output_net2*);
| #
| # TNM attached to instance example:
| #INST inst_path/ff_instance_name1_reg* TNM = slowffs ;
| #INST inst_path/ff_instance_name2_reg* TNM = slowffs ;
| #
| # If a FF clock-enable is used on all flip flops of a multi-cycle path,
| # you can attach TNM to the clock enable net.  NOTE:  TNM attached to a
| # net "forward traces" to any FF, LATCH, RAM, or PAD attached to the
| # net.
| #NET ff_clock_enable_net TNM = slowffs ;
| #
| # Example of using "slowffs" timegroup, in a FROM:TO timespec, with
| # either of the three timegroup methods shown above:
| #TIMESPEC TS10 = FROM : slowffs : TO : FFS : 100 ;
| #
| # Constrain the skew or delay associate with a net.
| #NET any_net_name MAXSKEW = 7 ;
| #NET any_net_name MAXDELAY = 20 ns;
| #
| #
| # Constraint priority in your .ucf file is as follows:
| #
| #    highest 1.  Timing Ignore (TIG)
| #            2.  FROM : THRU : TO specs
| #            3.  FROM : TO specs
| #    lowest  4.  PERIOD specs
| #
| # See the on-line "Library Reference Guide" document for
| # additional timespec features and more information.
| #
| #
| ############################################################
| #
#
| #         LOCATION and ATTRIBUTE SPECIFICATIONS            #
| #
#
| ############################################################
| # Pin and CLB location locking constraints                 #
| ############################################################
| #
| # -----------------------
| # Assign an IO pin number
| # -----------------------
| #INST io_buf_instance_name  LOC = P110 ;
| #NET io_net_name  LOC = P111 ;
| #
| # -----------------------
| # Assign a signal to a range of I/O pins
| # -----------------------
| #NET "signal_name" LOC=P32, P33, P34;
| #
| # -----------------------
| # Place a logic element(called a BEL) in a specific CLB location.
| # BEL = FF, LUT, RAM, etc...
| # -----------------------
| #INST instance_path/BEL_inst_name  LOC = CLB_R17C36 ;
| #
| # -----------------------
| # Place CLB in rectangular area from CLB R1C1 to CLB R5C7
| # -----------------------
| #INST /U1/U2/reg<0> LOC=clb_r1c1:clb_r5c7;
| #
| # -----------------------
| # Place hierarchical logic block in rectangular area from CLB R1C1 to CLB
R5C7
| # -----------------------
| #INST /U1* LOC=clb_r1c1:clb_r5c7;
| #
| # -----------------------
| # Prohibit IO pin P26 or CLBR5C3 from being used:
| # -----------------------
| #CONFIG PROHIBIT = P26 ;
| #CONFIG PROHIBIT = CLB_R5C3 ;
| # Config Prohibit is very important for forcing the software to not use
critical
| # configuration pins like INIT or DOUT on the FPGA.  The Mode pins and
JTAG
| # Pins require a special pad so they will not be available to this
constraint
| # prohibit all of the config-related pins for now.
| # -----------------------
| # Assign an OBUF to be FAST or SLOW:
| # -----------------------
| #INST obuf_instance_name FAST ;
| #INST obuf_instance_name SLOW ;
| #
| # -----------------------
| # FPGAs only:  IOB input Flip-flop delay specification
| # -----------------------
| # Declare an IOB input FF delay (default = MAXDELAY).
| # NOTE:  MEDDELAY/NODELAY can be attached to a CLB FF that is pushed
| # into an IOB by the "map -pr i" option.
| #INST input_ff_instance_name MEDDELAY ;
| #INST input_ff_instance_name NODELAY ;
| #
| # -----------------------
| # Assign Global Clock Buffers Lower Left Right Side
| # -----------------------
| # INST gbuf1 LOC=SSW
| #PINLOCK_BEGIN
| #Sat Oct 30 10:50:38 1999
| NET "hc11_memoe" LOC = "P39";
| NET "hc11_romcs" LOC = "P38";
| #NET "hc11_fa<1>" LOC = "P46";
| NET "hc11_d<0>" LOC = "P40";
| #NET "hc11_d<1>" LOC = "P44";
| NET "hc11_fa<0>" LOC = "P45";
| NET "hc11_e" LOC = "P10";
| NET "hc11_a<9>" LOC = "P25";
| NET "hc11_a<12>" LOC = "P20";
| NET "hc11_rw" LOC = "P27";
| NET "hc11_as" LOC = "P28";
| NET "hc11_a<15>" LOC = "P14";
| NET "hc11_a<8>" LOC = "P26";
| NET "hc11_a<10>" LOC = "P24";
| NET "hc11_a<11>" LOC = "P23";
| NET "hc11_a<14>" LOC = "P18";
| NET "hc11_a<13>" LOC = "P19";
| #NET "hc11_reset" LOC = "P9";
| #PINLOCK_END


Article: 19502
Subject: Specifying Virtex CLKDLL CLKDV_DIVIDE property in VHDL
From: "Matt Billenstein" <mbillens@one.net>
Date: Tue, 28 Dec 1999 05:05:14 GMT
Links: << >>  << T >>  << A >>
How does one specify the CLKDLL properties in VHDL?

thx

m

Matt Billenstein
http://w3.one.net/~mbillens/
mbillens@one.net




Article: 19503
Subject: Re: Specifying Virtex CLKDLL CLKDV_DIVIDE property in VHDL
From: "Simon Bacon" <simon@tile.demon.co.uk.notreally>
Date: Mon, 27 Dec 1999 23:23:55 -0700
Links: << >>  << T >>  << A >>
Well, I have never tried it, but will this work:

  ClockBlock: block
      attribute CLKDV_DIVIDE: string;
      attribute CLKDV_DIVIDE of InDLL: label is "2.5";
  begin
      InDLL:    CLKDLL port map ( CLK0    => ClkIn,
                                  CLK90   => open,
                                  CLK180  => open,
                                  CLK270  => open,
                                  CLK2X   => open,
                                  CLKDV   => FractionalClk,
                                  LOCKED  => ClkInLocked,
                                  CLKIN   => ClkFromPad,
                                  CLKFB   => ClkInBuf,
                                  RST     => '0'          );
      etc.
  end block ClockBlock;


Matt Billenstein <mbillens@one.net> wrote in message
news:eyX94.14982$DK1.305504@typhoon2.kc.rr.com...
> How does one specify the CLKDLL properties in VHDL?




Article: 19504
Subject: Re: xilinx help *desperately* needed
From: jonathan@canuck.com (Susan Deike)
Date: 28 Dec 1999 06:26:54 GMT
Links: << >>  << T >>  << A >>
Matt Billenstein (mbillens@one.net) wrote:
: You say that the "falling edge should latch the data off the bus..." but
: you're using if rising_edge(hc11_e) then

See the followup I posted a few minutes later.  I'd been messing around
a lot this morning with a lot of things, that included, and sloppily posted
the wrong version of the source.  It should read "falling_edge" and 
indeed still does not work that way.  An unfortunate typo, not the source
of my grief.

: ....  Also, take a look in the FPGA editor and actually follow the signal off
: of the input PAD, through the register, and out onto the output PAD checking
: along the way that you're really registering the data on the proper clock
: edge and that your clock enable looks good and so on and so forth...

It goes everywhere it should.  We even tried synthesizing with both
(foundation's) synopsys and synplicity.  Synopsys puts the register in
the data bus (input) IOB and synplicity uses the latch in the output IOB,
but otherwise they're identical.  The clock is routed properly (we tried
using both primary and secondary clock buffers and it didn't make any
difference).  The clock enable is routed properly.  About the only thing
that looks the slightest bit weird is that there's a connection made from
the register's reset input to the global set/reset bus, and that had us
thinking for a while that the register was being held in the reset state,
but we've been assured by the xilinx factory applications folks that what
we're seeing is normal - it's a default put in place that handles device
initialization.

Mystery remains.

Jonathan

p.s. Also a mystery why our nntp server plugged Susan's name into the header...

Article: 19505
Subject: Re: xilinx help *desperately* needed
From: Bonio Lopez <bonio.lopezNOboSPAM@gmx.ch.invalid>
Date: Tue, 28 Dec 1999 01:37:25 -0800
Links: << >>  << T >>  << A >>
Hi  Jonathan (and Susan ?),
I'm not sure if it is your problem but may be it is so.

I' have connected HC11 core with RAM (in FPGA) by following way

1)  if uc_e = '0' and uc_rxw = '1' then     RAM_noe_sig <= '0';   else
RAM_noe_sig <= '1';
2)  if uc_e = '1' and uc_rxw = '0' then     RAM_nwe_sig <= '0';    else
RAM_nwe_sig <= '1';

I have found out that  by reading from  RAM

RAM set  2 times data value on the bus because the valid address will
be set one noe tact  early.

That's why you must latch the data bus not when valid address is set on
the address bus and noe IS '0'
but when the valid address exists on the address bus at the time, when
noe GOES to '0'.

Hope it helps,
(You can write me if you have not understood, what i mean)


* Sent from RemarQ http://www.remarq.com The Internet's Discussion Network *
The fastest and easiest way to search and participate in Usenet - Free!

Article: 19506
Subject: Re: HDL to graphic conversion
From: Edwin Naroska <edwin@mira.e-technik.uni-dortmund.de>
Date: Tue, 28 Dec 1999 10:56:50 +0100
Links: << >>  << T >>  << A >>
Hi,

#YEO WEE KWONG# wrote:

> Hi,
>
> Anyone come across any tools that does the above.

You may take a look at the VHDL FAQ
(http://www.vhdl.org/comp.lang.vhdl/). Part 3
section 5 lists some VHDL <-> FSM/Schematic
translators.

--
Edwin


Article: 19507
Subject: Re: xilinx help *desperately* needed
From: a@z.com
Date: Tue, 28 Dec 1999 08:52:36 -0500
Links: << >>  << T >>  << A >>
Hi Jonathan,

The only suggestion I have concerns the VHDL coding of the D flip-flop (and not latch as you mention).

Instead of:

process (flashreg, hc11_d, hc11_e, hc11_reset)
begin
-- latch data lsb into flash address lsb
        if falling_edge(hc11_e) then
                if (flashreg = '1') then
                        hc11_fa(0) <= hc11_d(0);
                end if;
        end if;
end process;

I would use:

process (hc11_e, hc11_reset)
begin
        if hc11_reset='1' then             -- I presume active high reset here
           hc11_fa<=(others=>'0');
        elsif falling_edge(hc11_e) then
                if (flashreg = '1') then
                        hc11_fa <= hc11_d;
                end if;
        end if;
end process;

This removes a large number of warnings generated by the synthesis tool (Synplicity) concerning unused pin hc11_reset and
unused signal and pin hc11_fa(1). By the way, are you sure you are not looking at hc11_fa(1) instead of hc11_fa(0)?

Otherwise I see no problem with your code - I have extensively used this construct, including in SpartanXL FPGA without
any problem.

Susan Deike wrote:

> I'm working on a design of moderate complexity in 5V Spartan using
> Foundation 2.1i sp3 (yeah, I know.  just let me get over this problem,
> lord, and I'll move to the HP...).

De gustibus et de coloribus... I try to avoid workstations as much as I can.

Regards,

Catalin Baetoniu



Article: 19508
Subject: VGA controller in FPGA
From: "Larry Edington" <larryeSpam.Me.Not@centuryinter.net>
Date: Tue, 28 Dec 1999 08:46:50 -0600
Links: << >>  << T >>  << A >>
Would anyone know of a VGA controller I could license for a FPGA? Nothing
fancy needed. In fact,
640 x 480 would be fine. DAC of course would be external. Hoping to use
Altera Flex.

thanks,
Larry E.



Article: 19509
Subject: Re: How can I preset /prereset some Latches
From: eml@riverside-machines.com.NOSPAM
Date: Tue, 28 Dec 1999 16:30:10 GMT
Links: << >>  << T >>  << A >>
On Mon, 27 Dec 1999 22:40:36 -0500, Dave Vanden Bout <devb@xess.com>
wrote:

>Have you tried placing the register initialization into the user constraints file?  This is what I put in my .UCF file if I have a register called X in my VHDL that I have to initialize:
>
>INST X_reg INIT=S;    # this sets the X register to a logic 1
>INST X_reg INIT=R;    # this sets the X register to a logic 0
>
>
>
>Bonio Lopez wrote:
>
>> Hi friends,
>> I need that after downloading of my program in FPGA some latches will
>> be preseted and some prereseted (without any external reset).
>> I know it is possible but can you say me how?
>>
>> My tools : VHDL, Leonardo, Xilinx Alliance 2.1i, Virtex.
>>
>> * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network *
>> The fastest and easiest way to search and participate in Usenet - Free!

there's a simpler way, which is covered here fairly frequently. put an
asynchronous preset or reset in the vhdl code for your register. for
the sake of argument, use a signal called INIT_H. you then have to
make sure that INIT_H uses the GSR net on your device. there are a
number of ways to do this, but the common ones are:

1) make sure that every register with an async preset/reset on your
device uses INIT_H as the preset/reset signal, or

2) instantiate the appropriate STARTUP element for your device, and
connect INIT_H to the GSR pin on this element. this has the advantage
that you don't then have to explicitly code an async preset/reset for
every register on the device. your synth will produce async-reset
elements by default if you don't explicitly code an async preset.

evan

Article: 19510
Subject: Re: xilinx help *desperately* needed
From: "Andy Peters" <apeters.Nospam@nospam.noao.edu.nospam>
Date: Tue, 28 Dec 1999 10:23:45 -0700
Links: << >>  << T >>  << A >>
Susan Deike wrote in message <8495gu$q0j$1@cleavage.canuck.com>...

>The problem is that I can't get a D register in the device to latch data
>off of my microprocessor's (68HC11) data bus.  My original target is an
>XCS40, but I've built a proto using an XCS10 to try to isolate this
problem.


>Both protos exhibit exactly the same behaviour:  The combinatorial logic
>(address decoders) work just fine.  When I probe the clock enable signal
>(flashreg) out it's exactly what and where it should be, valid 50nS before
>and after the system (e) clock, the falling edge of which should latch the
>data off of the bus.  Scope shows the data to be good as well, just never
>appears on the register output


>process (flashreg, hc11_d, hc11_e, hc11_reset)
>begin
>-- latch data lsb into flash address lsb
>
> if rising_edge(hc11_e) then
> if (flashreg = '1') then
> hc11_fa(0) <= hc11_d(0);
> end if;
> end if;
>end process;
>end rtl;

The construct you describe - specifically, the sensitivity list - indicates
that a latch should be built, even though you want to use D flops. The
Spartan architecture doesn't have a latch, so the synthesis tool makes one
out of gates.   That's one of the problems - the other is related.  The
address decode flashreg is combinatorial.  Since the latch is also
combinatorial, the whole latch function might get really big and take much
longer to actually store the data than you might think.  Some things you
should do:

1) make a real flip-flop out of hc11_fa(0) by changing the sensitivity list
to just hc11_e and hc11_reset.

2) make sure the e-clock input uses a global clock buffer (this will happen
automagically iff your e-clock input only goes to flip-flop clock
registers).

3) set a period constraint on the e-clock equal to whatever the clock
frequency is.

4) put an offset constraint on the address and data inputs.

have fun.



--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu

The secret of Slurm is on a need-to-know basis.



Article: 19511
Subject: Re: VGA controller in FPGA
From: jhallen@world.std.com (Joseph H Allen)
Date: Tue, 28 Dec 1999 17:27:16 GMT
Links: << >>  << T >>  << A >>
In article <r34a4.968$B9.1198772@feed.centuryinter.net>,
Larry Edington <larryeSpam.Me.Not@centuryinter.net> wrote:
>Would anyone know of a VGA controller I could license for a FPGA? Nothing
>fancy needed. In fact, 640 x 480 would be fine. DAC of course would be
>external. Hoping to use Altera Flex.

Try Intrinsix (en engineering consulting company) in Westboro
(508)-836-4100.  A friend of mine used to work there on this very design.

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 19512
Subject: Re: VGA controller in FPGA
From: jhallen@world.std.com (Joseph H Allen)
Date: Tue, 28 Dec 1999 17:28:57 GMT
Links: << >>  << T >>  << A >>
In article <r34a4.968$B9.1198772@feed.centuryinter.net>,
Larry Edington <larryeSpam.Me.Not@centuryinter.net> wrote:
>Would anyone know of a VGA controller I could license for a FPGA? Nothing
>fancy needed. In fact, 640 x 480 would be fine. DAC of course would be
>external. Hoping to use Altera Flex.

Try Intrinsix (en engineering consulting company) in Westboro, MA
(508)-836-4100.  A friend of mine used to work there on this very design.

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 19513
Subject: Re: status during ISP
From: Bibico Cando <pobox303@usa.net>
Date: Tue, 28 Dec 1999 19:02:17 +0100
Links: << >>  << T >>  << A >>
For CPLDs of  XC9500 series it is weak pulled up if in ISP mode (programming)

David Geng wrote:

> Hi, there,
>
> can any one tell me what's the status(high, low or float) of the I/O pins
> when a EPLD or FPGA in ISP procedure?
>
> Thanks a lot
>
> David

Article: 19514
Subject: Re: VGA controller in FPGA
From: Dave Vanden Bout <devb@xess.com>
Date: Tue, 28 Dec 1999 15:17:22 -0500
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------3D9A5C8563D104C152D038B1
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

There is a VHDL and ABEL description of a VGA generator and output circuit for an FPGA at http://www.xess.com/vga.pdf.

Larry Edington wrote:

> Would anyone know of a VGA controller I could license for a FPGA? Nothing
> fancy needed. In fact,
> 640 x 480 would be fine. DAC of course would be external. Hoping to use
> Altera Flex.
>
> thanks,
> Larry E.

--------------3D9A5C8563D104C152D038B1
Content-Type: text/x-vcard; charset=us-ascii;
 name="devb.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Dave Vanden Bout
Content-Disposition: attachment;
 filename="devb.vcf"

begin:vcard 
n:Vanden Bout;David
tel;fax:(919) 387-1302
tel;work:(919) 387-0076
x-mozilla-html:FALSE
url:http://www.xess.com
org:XESS Corp.
adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
version:2.1
email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;28560
fn:Dave Vanden Bout
end:vcard

--------------3D9A5C8563D104C152D038B1--

Article: 19515
Subject: Re: VGA controller in FPGA
From: Dave Vanden Bout <devb@xess.com>
Date: Tue, 28 Dec 1999 15:17:22 -0500
Links: << >>  << T >>  << A >>
This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

------ =_NextPart_000_01BF51D9.7EC9ACC6
Content-Type: text/plain

There is a VHDL and ABEL description of a VGA generator and output
circuit for an FPGA at http://www.xess.com/vga.pdf.

Larry Edington wrote:

> Would anyone know of a VGA controller I could license for a FPGA?
Nothing
> fancy needed. In fact,
> 640 x 480 would be fine. DAC of course would be external. Hoping to
use
> Altera Flex.
>
> thanks,
> Larry E.


------ =_NextPart_000_01BF51D9.7EC9ACC6
Content-Type: text/x-vcard;
	name="devb.vcf"
Content-Disposition: attachment;
	filename="devb.vcf"
Content-Description: Card for Dave Vanden Bout

begin:vcard 
n:Vanden Bout;David
tel;fax:(919) 387-1302
tel;work:(919) 387-0076
x-mozilla-html:FALSE
url:http://www.xess.com
org:XESS Corp.
adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
version:2.1
email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;28560
fn:Dave Vanden Bout
end:vcard

------ =_NextPart_000_01BF51D9.7EC9ACC6--

Article: 19516
Subject: Re: xilinx help *desperately* needed
From: "Matt Billenstein" <mbillens@one.net>
Date: Tue, 28 Dec 1999 20:27:12 GMT
Links: << >>  << T >>  << A >>
Why not actually use a D register with feedback instead of a latch since the
spartan architecture doesn't have them anywho?  Thus, define the ELSE:


process (flashreg, hc11_d, hc11_e, hc11_reset)
begin
-- latch data lsb into flash address lsb
if rising_edge(hc11_e) then
  if (flashreg = '1') then
    hc11_fa(0) <= hc11_d(0);
  ELSE
    hc11_fa(0) <= hc11fa(0);
  end if;
end if;
end process;



m

Matt Billenstein
http://w3.one.net/~mbillens/
REMOVEmbillens@one.net


<a@z.com> wrote in message news:3868C0A4.66B8B230@z.com...
| Hi Jonathan,
|
| The only suggestion I have concerns the VHDL coding of the D flip-flop
(and not latch as you mention).
|
| Instead of:
|
| process (flashreg, hc11_d, hc11_e, hc11_reset)
| begin
| -- latch data lsb into flash address lsb
|         if falling_edge(hc11_e) then
|                 if (flashreg = '1') then
|                         hc11_fa(0) <= hc11_d(0);
|                 end if;
|         end if;
| end process;
|
| I would use:
|
| process (hc11_e, hc11_reset)
| begin
|         if hc11_reset='1' then             -- I presume active high reset
here
|            hc11_fa<=(others=>'0');
|         elsif falling_edge(hc11_e) then
|                 if (flashreg = '1') then
|                         hc11_fa <= hc11_d;
|                 end if;
|         end if;
| end process;
|
| This removes a large number of warnings generated by the synthesis tool
(Synplicity) concerning unused pin hc11_reset and
| unused signal and pin hc11_fa(1). By the way, are you sure you are not
looking at hc11_fa(1) instead of hc11_fa(0)?
|
| Otherwise I see no problem with your code - I have extensively used this
construct, including in SpartanXL FPGA without
| any problem.
|
| Susan Deike wrote:
|
| > I'm working on a design of moderate complexity in 5V Spartan using
| > Foundation 2.1i sp3 (yeah, I know.  just let me get over this problem,
| > lord, and I'll move to the HP...).
|
| De gustibus et de coloribus... I try to avoid workstations as much as I
can.
|
| Regards,
|
| Catalin Baetoniu
|
|
|


Article: 19517
Subject: Re: status during ISP
From: steve (Steve Rencontre)
Date: Wed, 29 Dec 1999 03:00 +0000 (GMT Standard Time)
Links: << >>  << T >>  << A >>
In article <3866ec0c@athene.hdm-stuttgart.de>, david_geng@yahoo.com 
(David Geng) wrote:

> Hi, there,
> 
> can any one tell me what's the status(high, low or float) of the I/O 
> pins
> when a EPLD or FPGA in ISP procedure?

I'd be surprised if there are any that don't go hi-Z during ISP, but 
it's not my board that'll smoke if I'm mistaken :-)

Try reading the data sheet or app notes for your particular device!

--
Steve Rencontre, Design Consultant
http://www.rsn-tech.demon.co.uk
Article: 19518
Subject: Re: HDL to graphic conversion
From: "peter dudley" <padudle@worldnet.att.net>
Date: Tue, 28 Dec 1999 20:13:00 -0700
Links: << >>  << T >>  << A >>
There is an tool set called Summit that convertes graphical entry to HDL and
can go the other way. The company was recently bought by Viewlogic and I
think the Summit tools are about $20K/seat.

Also the Symplify synthesis tool creates a pretty nice block diagram from
the structural parts of an HDL design. I've used it and it is super easy but
again it is not inexpensive.

--
Pete Dudley

Arroyo Grande Systems Incorporated

#YEO WEE KWONG# <P7102672H@ntu.edu.sg> wrote in message
news:0CF260C495FED111A6610000F866308D085379FA@mail3.ntu.edu.sg...
> Hi,
>
> Anyone come across any tools that does the above. By the way, does
> xilinx foundation s/w provide the above avenue.
>
> Thanks.
>


Article: 19519
Subject: Re: Dumb question springing from a discussion about chess on a chip...
From: krw@attglobal.net (Keith R. Williams)
Date: 29 Dec 1999 03:21:44 GMT
Links: << >>  << T >>  << A >>
On Sat, 25 Dec 1999 01:59:12, Dave Vanden Bout <devb@xess.com> 
wrote:

> This message is in MIME format. Since your mail reader does not understand
> this format, some or all of this message may not be legible.

Then *DON'T* post it to a USENET text only newsgroup!!! ...and it
has *nothing* to do with a mail reader (this is the USENET, 
dimwit).  If it is anything other than text it has no business 
being here!!!  Sheesh, kids...

Learn the medium and abide by its rules.

----
  Keith



Article: 19520
Subject: USB2 core call for Volunteers
From: Jamil Khaib <Khatib@ieee.org>
Date: Wed, 29 Dec 1999 11:34:12 +0200
Links: << >>  << T >>  << A >>
Hi
me as a memeber of  the OpenIPCore project are trying to develope a USB
2.0 core.
We need some designers to help us in this project you are welcome to
join us.

we need also a PCI 2.2 core, and any kind of contribution you can made
is more than welcomed

Thanks
OpenIP Organization   http://www.openip.org
OpenIPCore Project   http://www.openip.org/oc
OpenCores Project     http://www.opencore.org


Article: 19521
Subject: OpenIPCore call for examples
From: Jamil Khaib <Khatib@ieee.org>
Date: Wed, 29 Dec 1999 12:23:05 +0200
Links: << >>  << T >>  << A >>

We are in OpenIPCore and OpenCores projects are trying to increase the
popularity of free open hardware designs and free EDA tools.
For this reason we would like to ask from each EDA tool developer a
small contribution to our project by putting one of their examples in
OpenCores CVS "which is distributed by the tool" that shows the power
and the usfulness of the tool.
As a result we will put a link to your project and mark it with special
grade

you can visit the Tool.html page to see some links

To send your design please email me at khatib@ieee.org

You are welcome to join us

Thanks
OpenIP Organization  http://www.openip.org
OpenIPCore Project   http://www.openip.org/oc
OpenCores Project    http://www.opencores.org


Article: 19522
Subject: sim error & webfitter
From: Jamil Khaib <Khatib@ieee.org>
Date: Wed, 29 Dec 1999 12:49:35 +0200
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------1DC49E2AD00E320FCB88F6EB
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

I synthesized the attached files with the webfitter and tried to
simulate it but I got different results that what I got before
synthesis.
Data out and Flages do not change in the normal operation "other than
reset"

The attached ps file shows the results of simulation before synthesis

Can you help me?

Thanks

OpenIP Organization  http://www.openip.org
OpenIPCore Project   http://www.openip.org/oc
OpenCores Project    http://www.opencores.org


--------------1DC49E2AD00E320FCB88F6EB
Content-Type: text/plain; charset=us-ascii;
 name="FIFO_v5.vhd"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
 filename="FIFO_v5.vhd"

-------------------------------------------------------------------------------
-- 
-- Copyright Jamil Khatib 1999
-- 
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it under the terms of the Openip General Public
-- License as it is going to be published by the OpenIP Organization and any
-- coming versions of this license.
-- You can check the draft license at
-- http://www.openip.org/oc/license.html
--
--
-- Creator : Jamil Khatib
-- Date 10/10/99
--
-- version 0.19991226
--
-- This file was tested on the ModelSim 5.2EE
-- The test vecors for model sim is included in vectors.do file
-- This VHDL design file is proved through simulation but not verified on Silicon
-- 
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_signed.ALL;
USE ieee.std_logic_arith.ALL;


entity FIFO is
    
    generic (WIDTH : integer := 8;  	-- FIFO word width
	     ADD_WIDTH : integer := 3); -- Address Width

    port (Data_in : in std_logic_vector(WIDTH - 1 downto 0);  -- Input data
	  Data_out : out std_logic_vector(WIDTH - 1 downto 0);  -- Out put data
	  clk : in std_logic;  		-- System Clock
	  Reset : in std_logic;  	-- System global Reset
	  RE : in std_logic;  		-- Read Enable
	  WE : in std_logic;  		-- Write Enable
	  Full : buffer std_logic;  	-- Full Flag
	  Half_full : out std_logic;  	-- Half Full Flag
	  Empty : buffer std_logic); 	-- Empty Flag

end FIFO;



-------------------------------------------------------------------------------
-------------------------------------------------------------------------------

-- synthesized using webfitter
-- Input data is _NOT_ latched
-- The same as fifo_v3 but without the use of the variables in add_gen process
-- else case in add_gen "RE and WE" was removed

library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
USE ieee.std_logic_signed.ALL;
USE ieee.std_logic_arith.ALL;

-------------------------------------------------------------------------------
-- purpose: FIFO Architecture
architecture FIFO_v5 of FIFO is

-- constant values
	constant MAX_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '1');
	constant MIN_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) := (others => '0');
	constant HALF_ADDR:std_logic_vector(ADD_WIDTH -1 downto 0) :="011";--(ADD_WIDTH -1 downto ADD_WIDTH -1 => '0' ,others => '1');

    signal R_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Read Address
    signal W_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Write Address
	signal D_ADD   : std_logic_vector(ADD_WIDTH - 1 downto 0);  -- Diff Address

    signal REN_INT : std_logic;  		-- Internal Read Enable
    signal WEN_INT : std_logic;  		-- Internal Write Enable

	component dpmem
	    generic (ADD_WIDTH : integer := 3;
	   			 WIDTH : integer := 8 );

    	port (clk : in std_logic;
	    reset : in std_logic;
	  	w_add : in std_logic_vector(ADD_WIDTH - 1  downto 0 );
	    r_add : in std_logic_vector(ADD_WIDTH - 1 downto 0 );
	    data_in : in std_logic_vector(WIDTH - 1 downto 0);
	    data_out : out std_logic_vector(WIDTH - 1 downto 0 );
	    WR  : in std_logic;
	    RE  : in std_logic);
	end component;

	
    
begin  -- FIFO_v5

-------------------------------------------------------------------------------        

memcore: dpmem 
generic map (WIDTH => 8,
				ADD_WIDTH =>3)
	port map (clk => clk,
			 reset => reset,
			 w_add => w_add,
			 r_add => r_add,
			 Data_in => data_in,
			 data_out => data_out,
			 wr => wen_int,
			 re => ren_int);

-------------------------------------------------------------------------------

wen_int <= '1' when (WE = '1' and ( FULL = '0')) else '0';

ren_int <= '1' when RE = '1' and ( EMPTY = '0') else '0';


-------------------------------------------------------------------------------

Add_gen: process(clk,reset)    

   begin  -- process ADD_gen

       -- activities triggered by asynchronous reset (active low)
       if reset = '0' then
	   		W_ADD <= (others =>'0');
	   		R_ADD <= (others =>'0');
	   		D_ADD <= (others =>'0');
       -- activities triggered by rising edge of clock
       elsif clk'event and clk = '1'  then
		
		if WE = '1' and ( FULL = '0') then
	   		W_ADD <= W_ADD + 1;
			D_ADD <= D_ADD +1;
--        else
--	   		W_ADD <= W_ADD;
--			D_ADD <= D_ADD;

	    end if;

		if RE = '1' and ( EMPTY = '0') then
	   		R_ADD <= R_ADD + 1;
			D_ADD <= D_ADD -1;
--        else
--	   		R_ADD <= R_ADD;
--			D_ADD <= D_ADD;
	    end if;
			
       end if;
		
--	    R_ADD  <= q2;
--		W_ADD  <= q1;
--		D_ADD  <= q3;

   end process ADD_gen;

-------------------------------------------------------------------------------

	FULL      <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) = MAX_ADDR) else '0';
	EMPTY     <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) =  MIN_ADDR) else '0';
	HALF_FULL <=  '1'when (D_ADD(ADD_WIDTH - 1 downto 0) >  HALF_ADDR) else '0';


-------------------------------------------------------------------------------

        
end FIFO_v5;

-------------------------------------------------------------------------------
-------------------------------------------------------------------------------

--------------1DC49E2AD00E320FCB88F6EB
Content-Type: text/plain; charset=us-ascii;
 name="Dpmem.vhd"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
 filename="Dpmem.vhd"

-------------------------------------------------------------------------------
-- 
-- Copyright Jamil Khatib 1999
-- 
--
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it under the terms of the Openip General Public
-- License as it is going to be published by the OpenIP Organization and any
-- coming versions of this license.
-- You can check the draft license at
-- http://www.openip.org/oc/license.html
--
--
-- Creator : Jamil Khatib
-- Date 10/10/99
--
-- version 0.19991226
--
-- This file was tested on the ModelSim 5.2EE
-- The test vecors for model sim is included in vectors.do file
-- This VHDL design file is proved through simulation but not verified on Silicon
-- 
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_signed.ALL;



-- Dual port Memory core



ENTITY dpmem IS
generic ( ADD_WIDTH: integer := 3 ;
		 WIDTH : integer := 8);
  PORT (
    clk      : IN  std_logic;                                -- write clock
    reset    : IN  std_logic;                                -- System Reset
    W_add    : IN  std_logic_vector(add_width -1 downto 0);  -- Write Address
    R_add    : IN  std_logic_vector(add_width -1 downto 0);  -- Read Address
    Data_In  : IN  std_logic_vector(WIDTH - 1  DOWNTO 0);    -- input data
    Data_Out : OUT std_logic_vector(WIDTH -1   DOWNTO 0);    -- output Data
    WR       : IN  std_logic;                                -- Write Enable
    RE       : IN  std_logic);                               -- Read Enable
END dpmem;

-------------------------------------------------------------------------------
-------------------------------------------------------------------------------

ARCHITECTURE dpmem_v1 OF dpmem IS


  TYPE data_array IS ARRAY (integer range <>) OF std_logic_vector(WIDTH -1  DOWNTO 0);
                                        -- Memory Type
  SIGNAL data : data_array(0 to (2** add_width) );  -- Local data



  procedure init_mem(signal memory_cell : inout data_array ) is
  begin

    for i in 0 to (2** add_width) loop
      memory_cell(i) <= (others => '0');
    end loop;

  end init_mem;


BEGIN  -- dpmem_v1

  PROCESS (clk, reset)

  BEGIN  -- PROCESS


    -- activities triggered by asynchronous reset (active low)
    IF reset = '0' THEN
      data_out <= (OTHERS => 'Z');
      init_mem ( data);

      -- activities triggered by rising edge of clock
    ELSIF clk'event AND clk = '1' THEN
      IF RE = '1' THEN
        data_out <= data(conv_integer(R_add));
      else
        data_out <= (OTHERS => 'Z');    -- Defualt value
      END IF;

      IF WR = '1' THEN
        data(conv_integeR(W_add)) <= Data_In;
      END IF;
    END IF;



  END PROCESS;


END dpmem_v1;


-------------------------------------------------------------------------------

--------------1DC49E2AD00E320FCB88F6EB
Content-Type: application/postscript;
 name="FIFO_v5.ps"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline;
 filename="FIFO_v5.ps"

%!
/date (Mon Dec 27 22:00:14 1999) def
/design (Entity:fifo   Architecture:fifo_v5) def
/margin 28.3465 def
/time_per_point 0.56101 def
/pagewidth 841.89 def
/pageheight 595.276 def
%
%
% Copyright 1993 Model Technology Incorporated.   All rights reserved.
%
% @(#)vsim.ps	1.2 13 Mar 1994 
%
% This file is 'included' in the postscript output from the waveform display.
%
%

% pick the fonts
/fontheight 10 def
/mainfont {/Helvetica-Narrow findfont fontheight scalefont setfont } def
/smallfont {/Helvetica-Narrow findfont fontheight 3 sub scalefont setfont } def
mainfont
3 10 div setlinewidth

/signal_spacing fontheight 9 add def
/one_ht fontheight 2 sub def
/z_ht one_ht 2 div def
/ramp 2 def
/hz_tick_len 4 def

/footer {
	margin 2 add margin 2 add moveto

	design show
	(       Date: ) show
	date show
	(  ) show
	page_no show
} def

% draw a grid line in the background
/gridline {
	gsave
	0 setlinewidth
	[1] 0 setdash
	t_to_x time_y moveto
	0 pagetop time_y sub  rlineto

	% put hz ticks along the line
	base signal_spacing sub
	signal_spacing neg
	time_y 1 add
	{ 
		z_ht add				% draw it at the z level
		x hz_tick_len 2 div sub	% backup half the tick length
		exch
		moveto
		hz_tick_len 0 rlineto
	} for
	stroke
	grestore
} def

% draw the big tick marks
/big_tick {
	t_to_x time_y moveto
	0 big_tick_len rlineto
	stroke
} def

% label the big tick marks
% label x_pos 
/label_time {
	t_to_x time_y fontheight sub moveto
	dup stringwidth pop -2 div 0 rmoveto
	show
} def
/label_time_left {
	t_to_x time_y fontheight sub moveto
	%dup stringwidth pop -2 div 0 rmoveto
	show
} def
		
% draw the small tick marks
/small_ticks {
	{
		t_to_x time_y moveto
		0 small_tick_len rlineto
		stroke
	} for
} def

% show signal name and set the baseline
/signal {
	/name exch def

	%right justify the name
	margin namewidth add
	name stringwidth pop sub
	4 sub
	base moveto
	name show

	/last_was_change false def
	/is_change true def
	0 t_to_x base moveto
} def

/logic_1 {
	/y base one_ht add def
	x y lineto
	t_to_x y lineto
	stroke
	x y moveto
} def

/logic_H {
	[1] 0 setdash
	logic_1
	[] 0 setdash
} def

/logic_0 {
	/y base def
	x y lineto
	t_to_x y lineto
	stroke
	x y moveto
} def

/logic_L {
	[1] 0 setdash
	logic_0
	[] 0 setdash
} def

% alternate style for X - draw a box filled with gray
/logic_x_box {
	/y base one_ht add def
	/oldx x def
	t_to_x base moveto
	oldx base lineto
	oldx y    lineto
	x    y    lineto
	x    base lineto
	
	gsave
		0.7 setgray fill
	grestore
	stroke
	x base moveto
} def

/logic_X {
	/y base z_ht add def
	x y lineto
	t_to_x y lineto
	stroke
	x y moveto
} def

/logic_Z {
	[1] 0 setdash
	logic_X
	[] 0 setdash
} def

/logic_W {
	[2 1] 0 setdash
	logic_X
	[] 0 setdash
} def

/logic_U {
	[3 1] 0 setdash
	logic_X
	[] 0 setdash
} def

/logic_D {
	[1 2] 0 setdash
	logic_X
	[] 0 setdash
} def

/logic_- {
	[1 2] 0 setdash
	logic_X
	[] 0 setdash
} def

% stack => end_time is_change value_string
/vector {
	/value exch def
	/oldx x def
	t_to_x /newx exch def

	% draw the left edge
	last_was_change {left_change} if

	% print the value if there is room
	gsave
		smallfont
		newx oldx sub ramp sub
		value stringwidth pop
		gt { oldx ramp add base 1 add moveto value show } if
	grestore

	% draw the right edge
	is_change {right_change} if

	% draw the lines on top and bottom
	oldx base moveto
	newx base lineto
	oldx base one_ht add moveto
	newx base one_ht add lineto
	stroke
} def

/last_vector {
	/is_change false def
	vector
	/is_change true def
} def

/left_change {
	newx oldx sub ramp ge 
	{  % if there is room for ramp
		/oldx oldx ramp add def
		oldx base one_ht add moveto
		ramp neg z_ht neg rlineto
		ramp z_ht neg rlineto
	}
	{  % else just draw vertical line
		oldx base moveto
		0 one_ht rlineto
	}
	ifelse
} def

/right_change {
	newx oldx sub ramp ge
	{	% if there is room for ramp
		/newx newx ramp sub def
		newx base one_ht add moveto
		ramp z_ht neg rlineto
		ramp neg z_ht neg rlineto
		/last_was_change true def
	}
	{	% else just draw vertical line
		newx base moveto
		0 one_ht rlineto
	}
	ifelse
} def

/init_x2 {
	/x2 x def
} def

/vglitch {
	oldx base moveto
	0 one_ht rlineto
} def

/analog_backstep {
	/y exch base add def
	/x2 where {pop} {init_x2} ifelse
	x2 y lineto		% old x, old y, to old x, new y 
	/x2 x def
	x2 y lineto		% old x, new y, to new x, new y
	stroke
	x2 y moveto
	t_to_x pop
} def

/analog_interp {
	/y exch base add def
	t_to_x y lineto		% old x, old y, to new x, new y
	stroke
	x y moveto
} def

/analog {
	/y exch base add def
	x y lineto
	t_to_x y lineto
	stroke
	x y moveto
} def

/analog_blank {
	exch
	/x exch def
	x y moveto			% old x, old y, to new x, old y
	/y exch base add def
	x y moveto			% new x, old y, to new x, new y
} def

/big_tick_len 8 def
/small_tick_len 4 def
/time_y margin fontheight 3 mul add def
/t_to_x {
	dup /x exch def
} def

/namewidth 72 def
/pagetop pageheight margin sub def
/base pagetop def
/useable_ht pageheight margin 2 mul sub def
/useable_width pagewidth margin 2 mul sub def
/set_clip_region {
	newpath
		margin margin moveto
		0 useable_ht rlineto
		useable_width 0 rlineto
		0 useable_ht neg rlineto
	clip newpath
} def

% pick the fonts
/fontheight 8 def
/mainfont {/MSSansSerif findfont fontheight scalefont setfont } def
/smallfont {/MSSansSerif findfont fontheight 0.70 mul scalefont setfont } def
mainfont
/signal_spacing fontheight 9 add def
/one_ht fontheight 2 sub def
/z_ht one_ht 2 div def
/time_y margin fontheight 3 mul add def
/namewidth 72 def
/signal_spacing 19 def
 3 10 div setlinewidth
/base 566.929 def
%%Page: "1" 1
pageheight 0 translate 90 rotate
set_clip_region
  100.346 8.9125 813.346 small_ticks
  100.346 gridline
  100.346 big_tick
  (0) 100.346 label_time
  144.909 gridline
  144.909 big_tick
  (25) 144.909 label_time
  189.471 gridline
  189.471 big_tick
  (50) 189.471 label_time
  234.034 gridline
  234.034 big_tick
  (75) 234.034 label_time
  278.596 gridline
  278.596 big_tick
  (100) 278.596 label_time
  323.159 gridline
  323.159 big_tick
  (125) 323.159 label_time
  367.721 gridline
  367.721 big_tick
  (150) 367.721 label_time
  412.284 gridline
  412.284 big_tick
  (175) 412.284 label_time
  456.846 gridline
  456.846 big_tick
  (200) 456.846 label_time
  501.409 gridline
  501.409 big_tick
  (225) 501.409 label_time
  545.971 gridline
  545.971 big_tick
  (250) 545.971 label_time
  590.534 gridline
  590.534 big_tick
  (275) 590.534 label_time
  635.096 gridline
  635.096 big_tick
  (300) 635.096 label_time
  679.659 gridline
  679.659 big_tick
  (325) 679.659 label_time
  724.221 gridline
  724.221 big_tick
  (350) 724.221 label_time
  768.784 gridline
  768.784 big_tick
  (375) 768.784 label_time
 /page_no (Page 1) def
 footer
/base 547.929 def
(/fifo/data_in) signal
/x 100.346 def
newpath x base moveto
  100.346 (UUUUUUUU) vector
  242.946 (UUUUUUUU) vector
  314.246 (00000000) vector
  349.896 (00001111) vector
  385.546 (00000001) vector
  421.196 (00000011) vector
  528.146 (00000000) vector
  563.796 (00000111) vector
  599.446 (00001111) vector
  724.221 (00000000) vector
  795.521 (11111111) vector
/base 528.929 def
(/fifo/data_out) signal
/x 100.346 def
newpath x base moveto
  100.346 (U1111111) vector
  439.021 (ZZZZZZZZ) vector
  474.671 (00001111) vector
  510.321 (00000001) vector
  545.971 (00000011) vector
  581.621 (ZZZZZZZZ) vector
  617.271 (00000111) vector
  652.921 (ZZZZZZZZ) vector
  688.571 (00001111) vector
  795.521 (ZZZZZZZZ) vector
/base 509.929 def
(/fifo/clk) signal
/x 100.346 def
newpath x base moveto
 100.346 logic_U
 118.171 logic_U
 135.996 logic_1
 153.821 logic_0
 171.646 logic_1
 189.471 logic_0
 207.296 logic_1
 225.121 logic_0
 242.946 logic_1
 260.771 logic_0
 278.596 logic_1
 296.421 logic_0
 314.246 logic_1
 332.071 logic_0
 349.896 logic_1
 367.721 logic_0
 385.546 logic_1
 403.371 logic_0
 421.196 logic_1
 439.021 logic_0
 456.846 logic_1
 474.671 logic_0
 492.496 logic_1
 510.321 logic_0
 528.146 logic_1
 545.971 logic_0
 563.796 logic_1
 581.621 logic_0
 599.446 logic_1
 617.271 logic_0
 635.096 logic_1
 652.921 logic_0
 670.746 logic_1
 688.571 logic_0
 706.396 logic_1
 724.221 logic_0
 742.046 logic_1
 759.871 logic_0
 777.696 logic_1
 795.521 logic_0
/base 490.929 def
(/fifo/reset) signal
/x 100.346 def
newpath x base moveto
 100.346 logic_U
 100.346 logic_U
 171.646 logic_0
 688.571 logic_1
 724.221 logic_0
 795.521 logic_1
/base 471.929 def
(/fifo/re) signal
/x 100.346 def
newpath x base moveto
 100.346 logic_U
 242.946 logic_U
 421.196 logic_0
 795.521 logic_1
/base 452.929 def
(/fifo/we) signal
/x 100.346 def
newpath x base moveto
 100.346 logic_U
 242.946 logic_U
 314.246 logic_0
 421.196 logic_1
 528.146 logic_0
 795.521 logic_1
/base 433.929 def
(/fifo/full) signal
/x 100.346 def
newpath x base moveto
 100.346 logic_U
 100.346 logic_U
 795.521 logic_0
/base 414.929 def
(/fifo/half_full) signal
/x 100.346 def
newpath x base moveto
 100.346 logic_U
 100.346 logic_U
 795.521 logic_0
/base 395.929 def
(/fifo/empty) signal
/x 100.346 def
newpath x base moveto
 100.346 logic_U
 100.346 logic_0
 100.346 logic_0
 332.071 logic_1
 510.321 logic_0
 545.971 logic_1
 581.621 logic_0
 617.271 logic_1
 652.921 logic_0
 688.571 logic_1
 688.571 logic_0
 759.871 logic_1
 795.521 logic_0
/base 376.929 def
(/fifo/r_add) signal
/x 100.346 def
newpath x base moveto
  100.346 (U1111111) vector
  439.021 (00000000) vector
  474.671 (00000001) vector
  510.321 (00000010) vector
  581.621 (00000011) vector
  652.921 (00000100) vector
  688.571 (00000101) vector
  795.521 (00000000) vector
/base 357.929 def
(/fifo/w_add) signal
/x 100.346 def
newpath x base moveto
  100.346 (U0000001) vector
  332.071 (00000000) vector
  367.721 (00000001) vector
  403.371 (00000010) vector
  545.971 (00000011) vector
  581.621 (00000100) vector
  617.271 (00000101) vector
  652.921 (00000110) vector
  688.571 (00000111) vector
  759.871 (00000000) vector
  795.521 (00000001) vector
/base 338.929 def
(/fifo/d_add) signal
/x 100.346 def
newpath x base moveto
  100.346 (U0000010) vector
  332.071 (00000000) vector
  367.721 (00000001) vector
  403.371 (00000010) vector
  439.021 (00000011) vector
  474.671 (00000010) vector
  510.321 (00000001) vector
  545.971 (00000000) vector
  581.621 (00000001) vector
  617.271 (00000000) vector
  652.921 (00000001) vector
  688.571 (00000000) vector
  759.871 (00000000) vector
  795.521 (00000001) vector
/base 319.929 def
(/fifo/ren_int) signal
/x 100.346 def
newpath x base moveto
 100.346 logic_U
 100.346 logic_U
 421.196 logic_0
 510.321 logic_1
 545.971 logic_0
 581.621 logic_1
 617.271 logic_0
 652.921 logic_1
 688.571 logic_0
 688.571 logic_1
 759.871 logic_0
 795.521 logic_1
/base 300.929 def
(/fifo/wen_int) signal
/x 100.346 def
newpath x base moveto
 100.346 logic_U
 100.346 logic_U
 314.246 logic_0
 421.196 logic_1
 528.146 logic_0
 795.521 logic_1
showpage
%%EndPage: "1" 1
 3 10 div setlinewidth
/base 566.929 def
%%Page: "2" 2
pageheight 0 translate 90 rotate
set_clip_region
  28.3465 8.9125 812.646 small_ticks
  28.3465 gridline
  28.3465 big_tick
  (400) 28.3465 label_time_left
  72.909 gridline
  72.909 big_tick
  (425) 72.909 label_time
  117.471 gridline
  117.471 big_tick
  (450) 117.471 label_time
  162.034 gridline
  162.034 big_tick
  (475) 162.034 label_time
  206.596 gridline
  206.596 big_tick
  (500) 206.596 label_time
  251.159 gridline
  251.159 big_tick
  (525) 251.159 label_time
  295.721 gridline
  295.721 big_tick
  (550) 295.721 label_time
  340.284 gridline
  340.284 big_tick
  (575) 340.284 label_time
  384.846 gridline
  384.846 big_tick
  (600) 384.846 label_time
  429.409 gridline
  429.409 big_tick
  (625) 429.409 label_time
  473.971 gridline
  473.971 big_tick
  (650) 473.971 label_time
  518.534 gridline
  518.534 big_tick
  (675) 518.534 label_time
  563.096 gridline
  563.096 big_tick
  (700) 563.096 label_time
  607.659 gridline
  607.659 big_tick
  (725) 607.659 label_time
  652.221 gridline
  652.221 big_tick
  (750) 652.221 label_time
  696.784 gridline
  696.784 big_tick
  (775) 696.784 label_time
  741.346 gridline
  741.346 big_tick
  (800) 741.346 label_time
  785.909 gridline
  785.909 big_tick
  (825) 785.909 label_time
 /page_no (Page 2) def
 footer
/base 547.929 def
/x 28.3465 def
newpath x base moveto
  10.5215 (11111111) vector
/base 528.929 def
/x 28.3465 def
newpath x base moveto
/base 509.929 def
/x 28.3465 def
newpath x base moveto
/base 490.929 def
/x 28.3465 def
newpath x base moveto
 10.5215 logic_1
/base 471.929 def
/x 28.3465 def
newpath x base moveto
 10.5215 logic_1
/base 452.929 def
/x 28.3465 def
newpath x base moveto
 10.5215 logic_1
/base 433.929 def
/x 28.3465 def
newpath x base moveto
 10.5215 logic_0
/base 414.929 def
/x 28.3465 def
newpath x base moveto
 10.5215 logic_0
/base 395.929 def
/x 28.3465 def
newpath x base moveto
/base 376.929 def
/x 28.3465 def
newpath x base moveto
/base 357.929 def
/x 28.3465 def
newpath x base moveto
/base 338.929 def
/x 28.3465 def
newpath x base moveto
/base 319.929 def
/x 28.3465 def
newpath x base moveto
/base 300.929 def
/x 28.3465 def
newpath x base moveto
 10.5215 logic_1
showpage
%%EndPage: "2" 2
 3 10 div setlinewidth

--------------1DC49E2AD00E320FCB88F6EB--

Article: 19523
Subject: Re: USB2 core call for Volunteers
From: mcjy@my-deja.com
Date: Wed, 29 Dec 1999 11:42:37 GMT
Links: << >>  << T >>  << A >>
Hi!
Sounds interesting.
Will the core based on an existing CPU/MCU or
will it be a USB interface for typicl CPU?
I have heard of USB 2, but no about USB 2.2.
What is new in this version?

from
Joe

In article <3869D593.98FE8C34@ieee.org>,
  Jamil Khaib <Khatib@ieee.org> wrote:
> Hi
> me as a memeber of  the OpenIPCore project are trying to develope a
USB
> 2.0 core.
> We need some designers to help us in this project you are welcome to
> join us.
>
> we need also a PCI 2.2 core, and any kind of contribution you can made
> is more than welcomed
>
> Thanks
> OpenIP Organization   http://www.openip.org
> OpenIPCore Project   http://www.openip.org/oc
> OpenCores Project     http://www.opencore.org
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 19524
Subject: Re: USB2 core call for Volunteers
From: mcjy@my-deja.com
Date: Wed, 29 Dec 1999 11:53:57 GMT
Links: << >>  << T >>  << A >>
Ooops, sorry, I misread PCI2.2 as USB2.2
(In a flu at this moment.Not very awake.)

Anyway, USB 2.0 sounds interesting.
But Intel is now try to boost new USB speed
to 400Mbps (not very sure about this.)

For PCI core, now the market is moving
to PCI-133. But prototyping (for testing)
can be a big problem. Most FPGAs/CPLDs only
support up to PCI 66.  In addition, I think
that we need to "buy" PCI specification
document. Is it still true?

from
Joe



In article <84crif$jo9$1@nnrp1.deja.com>,
  mcjy@my-deja.com wrote:
> Hi!
> Sounds interesting.
> Will the core based on an existing CPU/MCU or
> will it be a USB interface for typicl CPU?
> I have heard of USB 2, but no about USB 2.2.
> What is new in this version?
>
> from
> Joe
>
> In article <3869D593.98FE8C34@ieee.org>,
>   Jamil Khaib <Khatib@ieee.org> wrote:
> > Hi
> > me as a memeber of  the OpenIPCore project are trying to develope a
> USB
> > 2.0 core.
> > We need some designers to help us in this project you are welcome to
> > join us.
> >
> > we need also a PCI 2.2 core, and any kind of contribution you can
made
> > is more than welcomed
> >
> > Thanks
> > OpenIP Organization   http://www.openip.org
> > OpenIPCore Project   http://www.openip.org/oc
> > OpenCores Project     http://www.opencore.org
> >
> >
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.
>


Sent via Deja.com http://www.deja.com/
Before you buy.


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search