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Messages from 19600

Article: 19600
Subject: Re: Design security
From: Ray Andraka <randraka@ids.net>
Date: Mon, 03 Jan 2000 21:04:01 -0500
Links: << >>  << T >>  << A >>
The cost is not the only issue.  As I understand it, adding the process steps
for the eprom option limits the amount of tweaking that can be done for the SRAM
process.  The FPGAs process is highly tweaked to get maximum switching
performance at the expense of static power among other things.

John Cain wrote:

> Ray,
>
> Your right about the added mask ? process steps. However, they do not
> represent a serious cost
> issue. CMOS masks are $1-2k per layer for ?0.5um, and several times that for
> ?0.5um.
> Worst case thats $15-30k as part of the large custom cmos chip that
> implements the FPGA device.
>
> I was thinking of an added 56bit onchip eeprom for the DES key as part of
> the FPGA device.  This leaves the SRAM CMOS device as is. Many ?0.5um
> processes offer an eeprom or eprom option. It bumps the total chip cost
> about 10%.
>
> John Cain, Power Processing, Inc., Phoenix, AZ
>  jjcain@goodnet.com
>
> ?Ray Andraka wrote in message ?3870B679.D84288FD@ids.net?...
> ?The problem with putting an OTP key in the device, is that the non-volatile
> ?cells can't be fabricated without additional process steps.  The FPGA
> ?process is essentially the same as DRAM, which lets it be done with
> bleeding
> ?edge process.  Put PROM cells on there, and you lose the speed.
>
> ?-Ray Andraka, P.E.
> ?President, the Andraka Consulting Group, Inc.
> ?401/884-7930     Fax 401/884-7950
> ?email randraka@ids.net
> ?http://users.ids.net/~randraka

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 19601
Subject: Actel repair assistance
From: John Larkin <jjlarkin@highland_SnipThis_technology.com>
Date: Mon, 03 Jan 2000 18:08:30 -0800
Links: << >>  << T >>  << A >>

Hi,

we have an existing product that uses an Actel A1280XL as the main controller.
We'd like to make a very simple change to some decode logic to activate a spare
D/A converter section that, unfortunately, overlaps another location in the
memory map. The fix will just involve a gate or two.

The FPGA was done as a schematic entry using the Actel Designer tools,
probably version 2.3.2 or 3.0, in mid 1995. We don't have anybody here
who is familiar with the tools,  although we do have the software and dongle.


We could furnish...

All the Actel design files

A hardcopy schematic with the required change redlined

A clear explanation of what we want to accomplish.


What I'd like is a fresh schematic and a new set of design files.

If anyone is familiar with this device and tools, and would like to do the rev
for us, please contact me so we can discuss the job.

Thanks,

John Larkin

jjlarkin (at) highlandtechnology (dot) com

800 473-4418

Article: 19602
Subject: Re: Using internal RAM in Altera Flex 10KE
From: "MK Yap" <mkyap@ieee.org>
Date: Tue, 4 Jan 2000 10:19:55 +0800
Links: << >>  << T >>  << A >>
Thanks for all the advices... I'm figuring out how to use the LPM now :-)

MKYap

Michael Vincze <vincze@home.com> wrote in message
news:PPbb4.11365$fH.675278@news1.rdc2.tx.home.com...
> Joe had suggested using LPMs.  Which is a nice choice.
>
> In order to use the RAMs, you need to use the EABs.  As
> a side note, the EABs may also be used for decode logic.
> At least last year MaxPlus2 was not capable of synthesizing
> EABs (i.e.:  If you had a decoder that would fit into an
> EAB it would not place it in the EAB automatically, unless
> you explicitly instantiated it.)  I suspect this had not
> changed.
>
> Other than using LPMs, Altera offers some type of
> macro generator that allows you to instantiate
> logic into the EABs.  Sorry I can't recall off the
> top of my head how its done, but it does take
> a few steps to set up.  The process incolves
> generating VHDL for simulation, and some
> form of netlist for synthesis.  Take a look in their
> bin directory for the executable that does it,
> and of course look in the Altera documentation.
>
> I've never tried the LPM solution, but it is
> probably closer to a "technology independent
> solution", so it may be more attractive.
>
> Good luck,
> Michael
>
>
> MK Yap <mkyap@ieee.org> wrote in message
> news:84hclo$ob8$1@clematis.singnet.com.sg...
> > Hi !
> >
> > I'm writing VHDL codes to be run on Altera Flex 10K100E. Currently using
> > Altera's Maxplus2 9.3.  From the specs, it has a total RAM of 49152
bits.
> >
> > My question is: how can i make use of the RAM? whenever i define an
array,
> > variable or signal in VHDL , I realize that the RAM is not being used.
> What
> > should I do to force it to use the RAM?
> >
> > Thank you!
> >
> >
> > MKYap
> >
> >
>
>


Article: 19603
Subject: Re: Design security
From: "John Cain" <jjcain@goodnet.com>
Date: Mon, 3 Jan 2000 18:46:06 -0800
Links: << >>  << T >>  << A >>
Hard tooling of an FPGA is a way of providing better device security.
However, It suffers from the added FPGA complexity cost together with the
cost multiplier
of buying from a sole source manufacturer. You loose all the advantages of
an FPGA
and gain none of the advantages of high VOLUME custom CMOS hard tooling
like: low cost.

Once you are facing a tooling issue, the tooling cost for FPGA hard tooling
is compariable
to CMOS full custom tooling. Typical custom CMOS full Mask production
tooling (>0.5um) and 1st 10 wafer run are $20K to 40k.

For me F_Programmable_GA  is what I use. If I am going to hard tool CMOS for
Volume Digital circuits then CMOS Standard Cells are where its at!

You can work up your CMOS standard cell design using a variety of schematic
tools, convert to a net list form and then watch your design autoplace and
autoroute to the Pads; automatically. It takes a few hours to
autoplace/autoroute 25k CMOS gates on a PC. CMOS Packaged Prototype Tooling
costs for a few (dozen) CMOS Standard Cell samples range from $1K -3K for
0.5um - 1.0um technology.

John Cain, Power Processing, Inc., Phoenix, AZ
jjcain@goodnet.com, 602 549 6604V, 480 759 4675V/F








Article: 19604
Subject: Re: An online division unit with constant divisor
From: khall@pacbell.net (Kelly Hall)
Date: Tue, 04 Jan 2000 04:16:35 GMT
Links: << >>  << T >>  << A >>
On 3 Jan 2000 16:03:59 GMT, Douglas W. Jones <jones@cs.uiowa.edu> wrote:
>See http://www.cs.uiowa.edu/bcd/divide.html
>for a tutorial on division by reciprocal multiplication.

404 - file not found.  I'd really love to read this paper!

Kelly
Article: 19605
Subject: Re: An online division unit with constant divisor
From: pmontgom@cwi.nl (Peter L. Montgomery)
Date: Tue, 4 Jan 2000 07:26:42 GMT
Links: << >>  << T >>  << A >>
In article <Duec4.660$II.77733@nntp1-sf.pbi.net> hall@iname.com writes:
>On 3 Jan 2000 16:03:59 GMT, Douglas W. Jones <jones@cs.uiowa.edu> wrote:
>>See http://www.cs.uiowa.edu/bcd/divide.html
>>for a tutorial on division by reciprocal multiplication.
>
>404 - file not found.  I'd really love to read this paper!
>
>Kelly

    Torbjorn Granlund and I published 
`Division by Invariant Integers using Multiplication'
in the 1994 PLDI (Programming Languages Design and Implementation)
proceedings -- see the June, 1994 SIGPLAN Notices or

     ftp.cwi.nl:/pub/pmontgom/divcsnt.{psa4,psl}.gz

The intended audience is compiler writers.

-- 
E = m c^2.  Einstein = Man of the Century.  Why the squaring?

        Peter-Lawrence.Montgomery@cwi.nl    Home: San Rafael, California
        Microsoft Research and CWI
Article: 19606
Subject: Re: Using internal RAM in Altera Flex 10KE
From: "goodkook" <goodkook@csvlsi.kyunghee.ac.kr>
Date: Tue, 4 Jan 2000 17:06:16 +0900
Links: << >>  << T >>  << A >>
LPM is nice choice.

Some Synthesizer, like Exemplar Spectrum, can extract LPM memory from VHDL
Source. but this is special case and they suggest coding-style guide. (Refer
to synthesis guide manual). to instanciate LPM memory you could have two
kind of vhdl. one for simulation model, and another for implementation. For
simulation model of RAM, you can use vendor specific memory model generator.
for altera maxplus2, there's "genmem.exe", which is in the maxplus2 folder.
Or you can write own vhdl model like this.

entity RAM256x8 is
port (
    data : in std_logic_vector(7 downto 0);
    addr : in std_logic_vector(7 downto 0);
    we : in std_logic;
    inclock : in std_logic;
    outclock : in std_logic;
    q : out std_logic_vector(7 downto 0));
end RAM256x8;

architecture ram_behave of RAM256x8 is
    constant low_address : natural := 0;
    constant high_address : natural := 255;
    subtype byte is std_logic_vector(7 downto 0);
    type memory_array is
         array (natural range low_address to high_address) of byte;
begin
    address_latch : process(addr, inclock)
    begin
        if (inclock'event and inclock='1') then
            address <= to_integer(unsigned(addr));
        end if;
    end process;

    mem_write : process(address, we)
    begin
        if(we='1') then
            mem(address) <= data(7 downto 0);
        wns if;
    end process;

    mem_read : process(address, outclock)
    begin
        if (outclock'event and outclock='1') then
            q<= mem(address);
        end if;
    end process;
end ram_behave;

above RAM vhdl is not so good for smulation. because, there's no set-up/hold
violation check utility. you can find more good RAM models which have
download and dump utility.

http://tech-www.informatik.uni-hamburg.de/vhdl/

to use LPM RAM,

package ram_constant is
    constant Data_Width  : natural := 16;
    constant Addr_Width  : natural := 8;
end;

LIBRARY lpm;
USE lpm.lpm_components.all;

entity RAM256x8 is
port (
    data : in std_logic_vector(Data_Width-1 downto 0);
    addr : in std_logic_vector(Addr_Width-1 downto 0);
    we : in std_logic;
    inclock : in std_logic;
    outclock : in std_logic;
    q : out std_logic_vector(7 downto 0));
end RAM256x8;

architecture LPM_RAM_Implement of RAM256x8 is
begin
    u_LPM_RAM : LPM_RAM_DQ
    generic map (
        lpm_widthad => Addr_width,
        lpm_width => Data_Width )
    port map (
        data => data,
        address => addr,
        we => we,
        inclock => inclock,
        outclock => outclock,
        q => q);
end;


--
----------------------------------
GoodKook
E-Mail : goodkook@nms.anslab.co.kr

AnsLab Co.,LTD
ASIC/IP Design in
  Muti-Media/Communication CODEC
  Intelligent-Peripherals for Mobile Computers
  URL: http://www.anslab.co.kr

GoodKook's VHDL Homepage
http://www.anslab.co.kr/goodkook

"MK Yap" <mkyap@ieee.org> wrote in message
news:84hclo$ob8$1@clematis.singnet.com.sg...
> Hi !
>
> I'm writing VHDL codes to be run on Altera Flex 10K100E. Currently using
> Altera's Maxplus2 9.3.  From the specs, it has a total RAM of 49152 bits.
>
> My question is: how can i make use of the RAM? whenever i define an array,
> variable or signal in VHDL , I realize that the RAM is not being used.
What
> should I do to force it to use the RAM?
>
> Thank you!
>
>
> MKYap
>
>


Article: 19607
Subject: Decoding RSPC (Reed Solomon Product Code)
From: "MK Yap" <mkyap@ieee.org>
Date: Tue, 4 Jan 2000 16:32:04 +0800
Links: << >>  << T >>  << A >>
Hi,

I'm writing a prog (VHDL or C) to enable block encoding and decoding of CD
sectors.  In the ECC (error correction coding) field, RSPC(Reed Solomon
Product Code) is used. The RSPC is a product code over GF(2^8) producing P
and Q parity bytes.  The GF(2^8) field is generated by the primitive
polynomial
P(x) = x^8 + x^4 + x^3 + x^2 + 1
The P parities are (26,24) RS codeword over GF(2^8) and the Q parities are
(45,43) RS codeword over GF(2^8).

My question is: How can I write the encoding and decoding algorithm for the
ECC field?? The RS used are non standard RS codes (n,k) in which n is
usually n=2^m -1 which m=8 in this case...
I tried to look for more info from books but it is really limited... I came
across some books saying that conventional RS decoding can be used.. that is
the berlekamp, Peterson and Weldon algorithm.  But I see no connection
between them coz the derivation is based on a fundamental which is
different.

Pls enlighten... by providing some books, paper, web site or perhaps
explanation of theory behind them...  Thank you very much!!

Happy Millenium 2000!!

MKYap



Article: 19608
Subject: Re: An online division unit with constant divisor
From: Terje Mathisen <Terje.Mathisen@hda.hydro.com>
Date: Tue, 04 Jan 2000 10:29:20 +0100
Links: << >>  << T >>  << A >>
"Peter L. Montgomery" wrote:
> 
> In article <Duec4.660$II.77733@nntp1-sf.pbi.net> hall@iname.com writes:
> >On 3 Jan 2000 16:03:59 GMT, Douglas W. Jones <jones@cs.uiowa.edu> wrote:
> >>See http://www.cs.uiowa.edu/bcd/divide.html
> >>for a tutorial on division by reciprocal multiplication.
> >
> >404 - file not found.  I'd really love to read this paper!
> >
> >Kelly
> 
>     Torbjorn Granlund and I published
> `Division by Invariant Integers using Multiplication'
> in the 1994 PLDI (Programming Languages Design and Implementation)
> proceedings -- see the June, 1994 SIGPLAN Notices or
> 
>      ftp.cwi.nl:/pub/pmontgom/divcsnt.{psa4,psl}.gz
> 
> The intended audience is compiler writers.

A few years ago, but after your paper which we didn't know about, Agner
Fog & myself did a similar exercise, the results are outlined on his
webpage:

  http://www.agner.org/assem/pentopt.htm#27

This page has x86 asm code which implements both locating the proper
reciprocal, and using it in code.

I disagree with the exact algorithm he chose for the cases where the
reciprocal value ends with a fraction which is less than 0.5, but the
final results are correct and the running speed is pretty much the same
anyway.

Terje

-- 
- <Terje.Mathisen@hda.hydro.com>
Using self-discipline, see http://www.eiffel.com/discipline
"almost all programming can be viewed as an exercise in caching"
Article: 19609
Subject: Re: Design security
From: Armin Mueller <armin.mueller@stud.uni-karlsruhe.de>
Date: Tue, 04 Jan 2000 12:03:20 +0100
Links: << >>  << T >>  << A >>


Stuart Clubb wrote:
 
> [...] A 56-bit key in DES would be quite strong,
> and while a 56-bit DES key has been recovered in around 2 hours, you
> have to remember that that was a "known plain text" attack (as the RSA
> ones have been as well, AFAIK).

Now, the "plain text" is (nearly) known. Altera config files consist 
of e.g. 90% zeroes, 9% single bit bytes.

Armin
Article: 19610
Subject: Re: Design security
From: rk <stellare@nospam.erols.com>
Date: Tue, 04 Jan 2000 06:55:48 -0500
Links: << >>  << T >>  << A >>
Steve Dewey wrote:

> In article <RB5b4.1138$B9.1418518@feed.centuryinter.net>, Larry Edington
> <larryeSpam.Me.Not@centuryinter.net> writes
> >I'm looking at an FPGA for project I'm working on and am concerned about
> >security. CPLD's and ASIC's I'm familiar with but FPGA's are a new trick for
> >me.
> >
> >I'm looking at Altera and Xilinx.
> >
> >It appears that most FPGA's are programmed with a serial eeprom. I'm
> >concerned about the security the data in the eeprom. What keeps someone from
> >simply copying your eeprom to duplicate your FPGA's programming?
> >
>
> One option that does not appear to have been suggested is to prototype
> using Altera chips and then go to Clear Logic's identical laser
> programmed parts for production. Best check which Altera parts Clear
> Logic support, though.

i do not have first-hand experience with the clear logic laser programmed parts.
however, other laser-programmed devices from chip express (note: prototypes
only), have cuts that are visible optically.  if otp is a possibility (the
original poster said no), then an antifuse, for example, would probably have
higher levels of security, as a programmed antifuse is not visible either
optically or with a sem, with two manufacturers making antifuse-based fpgas.

have a good evening,

----------------------------------------------------------------------
rk                               The world of space holds vast promise
stellar engineering, ltd.        for the service of man, and it is a
stellare@erols.com.NOSPAM        world we have only begun to explore.
Hi-Rel Digital Systems Design    -- James E. Webb, 1968

Article: 19611
Subject: Re: M1 timings
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 04 Jan 2000 12:06:54 +0000
Links: << >>  << T >>  << A >>


Christof Paar wrote:

> Just a brief question: How reliable are the timing results which the the
> M1 P&R tool (on Unix) provides for XC4000 family designs? In particular,
> how likely is it that the maximum critical path delay can be met in an
> actual design.
>
> Thanks,
>
> Christof
>
> ! WORKSHOP ON CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS (CHES 2000) !
> !                   WPI, August 17 & 18, 2000                         !
> !          http://www.ece.wpi.edu/Research/crypt/ches                 !
>
> ***********************************************************************
>                  Christof Paar,  Assistant Professor
>           Cryptography and Information Security (CRIS) Group
>       ECE Dept., WPI, 100 Institute Rd., Worcester, MA 01609, USA
> fon: (508) 831 5061    email: christof@ece.wpi.edu
> fax: (508) 831 5491    www:   http://ee.wpi.edu/People/faculty/cxp.html
> ***********************************************************************

I'm not sure about XC4K designs but for Virtex designs I've checked the
timing analyser results by running post-PAR simulations. The results seem to
be about right in that if I set the simulation clock to the value given by
the analyser it works o.k. but if I increase the speed by say 100ps I'll
start to see timing violations.

One thing to watch: The summary timing constraint results results reported
by PAR can be better than those reported by TRACE. The reason seems to be
that PAR does not allow for clock skew but TRACE does. For global clocks
this the biggest difference I've seen is about 0.4ns and I think this has
been fixed in 2.1iSP3 but I'm not sure yet.


Article: 19612
Subject: Re: Schematics for ISP
From: Wolfgang Freiberger <Wolfgang.Freiberger@ops.de>
Date: Tue, 04 Jan 2000 13:21:56 +0100
Links: << >>  << T >>  << A >>


Legista schrieb:
> 
> I search to see a design example of ISP of Xilinx's FPGA using EEPROM.
> Can someone tell me if I can see a schematics of that and where.
There are two "eeprom" devices that can be used for ISP of Xilinx FPGAs:
Atmel's AT17Cxxx and the brand new XC1800 series from Xilinx.
The XC1800 are programmed via JTAG. Please have a look on the accordant
application notes which you can find at www.xilinx.com .

The AT17Cxxx are I2C-programmable, and used just like the SROMs XC1700
(schematic as in the FPGA's databook). Difference: their default (but
programmable) reset polarity is inverted to the XC1700's.

HTH
Wolfgang
Article: 19613
Subject: Re: Schematics for ISP
From: Wolfgang Freiberger <Wolfgang.Freiberger@ops.de>
Date: Tue, 04 Jan 2000 13:28:36 +0100
Links: << >>  << T >>  << A >>
Sorry, forgot to give you a link to Atmel's AT17Cxxx homepage, where you
can find useful application notes:
http://www.euatmel.ac.psiweb.com/atmel/products/prod183.htm

Wolfgang
Article: 19614
Subject: Re: Decoding RSPC (Reed Solomon Product Code)
From: "John Janusson" <jjanusson@nospami-o.com>
Date: Tue, 04 Jan 2000 14:30:43 GMT
Links: << >>  << T >>  << A >>
Try http://www.fokus.gmd.de/research/cc/mobra/products/fec/ .  They have
some utilities (genenc and genrs) which, given m, n, and k as paramerters,
will generate a synthesizable VHDL design.  Perhaps a good starting point...

Good Luck,
John

MK Yap wrote in message <84savt$bo2$1@violet.singnet.com.sg>...
>Hi,
>
>I'm writing a prog (VHDL or C) to enable block encoding and decoding of CD
>sectors.  In the ECC (error correction coding) field, RSPC(Reed Solomon
>Product Code) is used. The RSPC is a product code over GF(2^8) producing P
>and Q parity bytes.  The GF(2^8) field is generated by the primitive
>polynomial
>P(x) = x^8 + x^4 + x^3 + x^2 + 1
>The P parities are (26,24) RS codeword over GF(2^8) and the Q parities are
>(45,43) RS codeword over GF(2^8).
>
>My question is: How can I write the encoding and decoding algorithm for the
>ECC field?? The RS used are non standard RS codes (n,k) in which n is
>usually n=2^m -1 which m=8 in this case...
>I tried to look for more info from books but it is really limited... I came
>across some books saying that conventional RS decoding can be used.. that
is
>the berlekamp, Peterson and Weldon algorithm.  But I see no connection
>between them coz the derivation is based on a fundamental which is
>different.
>
>Pls enlighten... by providing some books, paper, web site or perhaps
>explanation of theory behind them...  Thank you very much!!
>
>Happy Millenium 2000!!
>
>MKYap
>
>
>


Article: 19615
Subject: Re: An online division unit with constant divisor
From: jones@cs.uiowa.edu (Douglas W. Jones,201H MLH,3193350740,3193382879)
Date: 4 Jan 2000 17:11:46 GMT
Links: << >>  << T >>  << A >>
From article <Duec4.660$II.77733@nntp1-sf.pbi.net>,
by khall@pacbell.net (Kelly Hall):

> On 3 Jan 2000 16:03:59 GMT, Douglas W. Jones <jones@cs.uiowa.edu> wrote:
>>See http://www.cs.uiowa.edu/bcd/divide.html
>>for a tutorial on division by reciprocal multiplication.
> 
> 404 - file not found.  I'd really love to read this paper!

Sorry, I left a component out of the pathname.  The correct URL is:

    http://www.cs.uiowa.edu/~jones/bcd/divide.html

				Doug Jones
				jones@cs.uiowa.edu
Article: 19616
Subject: Re: CIC Filters in FPGA
From: "Morgan Colmer" <morgan@global-silicon.com>
Date: Tue, 4 Jan 2000 17:46:07 -0000
Links: << >>  << T >>  << A >>
Another book with a sensible explanation is "Digital Signal Processing in
Communication systems" by Marvin E Frerking (ISBN 0442016166).

I found the paper quite heavy as well, this book (and a few others) helped
clarify the subject. It should be noted that Hogenauer's paper was supposed
to primarily discuss the errors in such filters.

In order to make any proper use of CIC filters, you should consider
decimating in stages, introducing a conventional type FIR (usually bit
serial) to remove any unwanted signal images.


Morgan Colmer
Global Silicon

Ray Andraka <randraka@ids.net> wrote in message
news:385A472D.C07803D5@ids.net...
> CIC is just a rearrangement of the equation for a boxcar filter to get a
> recursive implementation.  A boxcar is an FIR filter with all the
coefficients
> set to unity (sometimes called a moving average filter).  Hogenauer's
paper
> introduces the filters and goes into considerable discussion on errors
caused by
> truncation.  I found it a somewhat less than easy read.  Marvin Frerking's
DSP
> in Communications text (kluwer) has a much more readable discussion on CIC
> filters.
>
> These work pretty well in FPGAs if the sinc spectral response suits your
> application.  They are really handy for high order interpolation and
> decimation.  If you cascade several, you do need to watch the wordsize.
You
> have to be extremely careful about truncating or your integrator will
overflow.
>
> Dave Decker wrote:
>
> > Eugene B. Hogenauer's paper, 'An Economical Class of Digital Filters
> > for Decimation and Interpolation' was published in:
> > IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol.
> > ASSP-29, NO. 2, April 1981.
> >
> > The Cascaded Integrator-Comb (CIC) filters work well in FPGAs whenever
> > you have to interpolate or decimate 2's compliment signals while
> > lowpass filtering them at the same time. The filters give the response
> > of FIR filters with all the coefficients set to 1. These are also
> > called 'box car' filters because their impulse response looks like a
> > rectangular box car. This type of filter requires no real
> > multiplication, which makes them relatively small and well suited for
> > FPGAs.
> >
> > The CIC implementation avoids the use of long shift register delay
> > lines you might think would be necessary for such a filter. This
> > efficiency is compounded because of the decimation/interpolation
> > especially when the CIC stages are cascaded.
> >
> > The architecture consists of accumulators, subtractors, and a small
> > number of pipeline delays. A 'must have' addition to your DSP bag of
> > tricks.
> >
> > Dave Decker
> > Diablo Research Co. LLC
> >
> > On Thu, 25 Nov 1999 10:57:12 GMT, "Mariotto" <mariotto@libero.it>
> > wrote:
> >
> > >Where I could find information on realizations of CIC filters supposed
from
> > >E.B. Hogenauer in FPGA?
> > >Thank you.
> > >
> > >Claudio Casagrande
> > >
> > >e-mail:mariotto@libero.it
> > >
> > >
>
>
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka
>
>


Article: 19617
Subject: Bad ALTERA data
From: "IC-BOOK" <food@alik.carrier.kiev.ua>
Date: Tue, 4 Jan 2000 20:19:34 +0200
Links: << >>  << T >>  << A >>
Dear All.


I never programm ALTERA's MAX7000 before.
What will do with EPM7064SLC (for exemple)
if I programm it with mistaked data and
after programm plug card with that chip
to computer's slot.
(I programm it by ISP)
MAX will crash?

When I programm GAL20V10 with mistaked data,
that the computer would not started, but
GAL and computer were alive.

Does everyone has some experience?

Thanks.

Alexandr Kouchtch
Entry Ltd.
http://ic.book.kiev.ua



Article: 19618
Subject: Re: HDL to graphic conversion
From: "goodkook" <goodkook@csvlsi.kyunghee.ac.kr>
Date: Wed, 5 Jan 2000 03:42:20 +0900
Links: << >>  << T >>  << A >>
If you have a hdl synthesizer, It generate netlist like edif.
Netlist is another form of schematic, i think.
Some tool, like Exemplar's "schview", can generate schematic view from edif
netlist.

"#YEO WEE KWONG#" <P7102672H@ntu.edu.sg> wrote in message
news:0CF260C495FED111A6610000F866308D085379FA@mail3.ntu.edu.sg...
> Hi,
>
> Anyone come across any tools that does the above. By the way, does
> xilinx foundation s/w provide the above avenue.
>
> Thanks.
>


Article: 19619
Subject: Re: M1 timings
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 04 Jan 2000 11:23:42 -0800
Links: << >>  << T >>  << A >>


Rick Filipkiewicz wrote:

> I'm not sure about XC4K designs but for Virtex designs I've checked the
> timing analyser results by running post-PAR simulations. The results seem to
> be about right in that if I set the simulation clock to the value given by
> the analyser it works o.k. but if I increase the speed by say 100ps I'll
> start to see timing violations.
>

I think the original question was about the relationship of timing analysis vs
physical reality. An the answer is that all numbers in the data book and in the
software are worst-case, covering Vcc, temperature and process variations. The
silicon is always faster than any of the published or otherwise derived numbers
say. We at Xilinx consider "typical" to be a dirty word.

It's a different matter that various methods of number crunching can achieve
slightly different results. That may be unavoidable, considering the complexity
of the methods.

But that has nothing to do with the real performance of the circuts.

Peter Alfke, Xilinx Applications

Article: 19620
Subject: Re: Design security
From: jim granville <jim.granville@DesignTools.co.nz>
Date: Wed, 05 Jan 2000 09:25:15 +1300
Links: << >>  << T >>  << A >>
Armin Mueller wrote:
> 
> Stuart Clubb wrote:
> 
> > [...] A 56-bit key in DES would be quite strong,
> > and while a 56-bit DES key has been recovered in around 2 hours, you
> > have to remember that that was a "known plain text" attack (as the RSA
> > ones have been as well, AFAIK).
> 
> Now, the "plain text" is (nearly) known. Altera config files consist
> of e.g. 90% zeroes, 9% single bit bytes.

Good point.
 So, how about these choices ?

- A Secured uC, with Loader SW + Bitstream all on chip, compression is a
candidate too.

- or - 

- A Small uC/SPLD that acts as a serial protocal converter, reading
from low cost i2c/SPI/DataFlash type memory, and loading the FPGA
 Simple encryption could be used on the memory, so the bitsteam is
copy protected.

 These are copy protection schemes, and do avoid copying, 
and production creepage issues, which are the majority concerns.

 This forces the code pirate to at least a PCB redesign, and
quite a bit of effort.

 For concerted reverse engineering protection, more work is needed, 
but a scheme where the FPGA interrogates the Loader uC/SPLD at 
runtime, for a certain response would create a FPGA 'dongle'.
 The response complexity is up to the designer, but anything that
froze the FPGA would suffice to raise the bar.
 Simple, multipath state machines would have low silicon cost on both
Loader and FPGA, but be seedable in nature

- jg

Article: 19621
Subject: Altera, Lattice, Xilinx
From: "Steve Sweet" <steves@2disk.com>
Date: Tue, 4 Jan 2000 13:07:58 -0800
Links: << >>  << T >>  << A >>
I've got a variety of surplus programmable logic, all
new, programmed once, available at great prices.
These include Altera, Lattice, Xilinx, Actel, AMD,
Quicklogic and more.

http://www.2disk.com/progic.htm

Offers will be accepted for quantity purchases.

Same day shipping. No minimum order.
Visa and Mastercard accepted.

Steve Sweet
2DISK
707-996-0108 x102





Article: 19622
Subject: synthesis opportunities
From: Eileen Haldeman <eileenh@chameleonsystems.com>
Date: 04 Jan 2000 16:39:06 EST
Links: << >>  << T >>  << A >>

Chameleon Systems is a  well-funded privately held fabless semiconductor
company that designs, markets and sells programmable system-on-a-chip (PSOC)
solutions for the communications electronics markets. Headquartered in Silicon
Valley, the company is developing the industry's first reconfigurable
communications processor platform - an
ideal solution for data-intensive Internet, DSP, networking and other
high-performance embedded telecom and datacom applications.  The
field-reconfigurable solution allows data and telecom equipment vendors to
create their own customized communications processors to more quickly adapt to
new requirements and standards, reduce time-to-market, lower development costs
and reduce risk.

We're looking for EDA Developers who want to make an impact in the following
exciting opportunities.

EDA Developer - Behavioral Synthesis
Our reconfigurable logic was architected as an ideal platform for
behavioral synthesis. This technology is a cornerstone of our product.
This position will interact intimately with parallel compiler and
hardware architecture group. Ideal candidate will have a strong R&D
background in behavioral synthesis, FPGA synthesis, and parallel
compilation, along with excellent programming skills in C++ and Java.

EDA Developer - Synthesis
Design and implement new algorithms and methodologies for the synthesis
onto Chameleon's novel reconfigurable datapath and control fabric.
Extend Chameleon's existing synthesis capabilities. Ideal candidate will
have a strong synthesis background in several of the following areas:
datapath synthesis, arithmetic optimization, control synthesis,
sequential synthesis, sequential analysis, logic synthesis, and logic
partitioning. Excellent software engineering and programming skills
required.

Please send your resume to jobs@chameleonsystems.com

Check us out on the web at:

        www.chameleonsystems.com

Article: 19623
Subject: GSR pulse
From: erika_uk@my-deja.com
Date: Wed, 05 Jan 2000 01:03:47 GMT
Links: << >>  << T >>  << A >>
hi all,

I see that even without instantiating VIRTEX_STARTUP, a GSR pulse is
generated whenever i do the timing simulation

My design does not need VIRTEX_STARTUP, so has this GSR effect on my
design , should i take its width into account to specify the clock freq.

thanks in advance...

--erika


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 19624
Subject: Re: An online division unit with constant divisor
From: christer_ericson@playstation.sony.nospam.com (Christer Ericson)
Date: Wed, 05 Jan 2000 01:08:47 GMT
Links: << >>  << T >>  << A >>
On Tue, 04 Jan 2000 10:29:20 +0100, Terje Mathisen
<Terje.Mathisen@hda.hydro.com> wrote:
>[...]
>I disagree with the exact algorithm he chose for the cases where the
>reciprocal value ends with a fraction which is less than 0.5, but the
>final results are correct and the running speed is pretty much the same
>anyway.

Terje, could you please elaborate on your prefered alternative
version for that case?


Christer Ericson
989 Studios, Santa Monica


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